diff --git a/.vscode/launch.json b/.vscode/launch.json new file mode 100644 index 0000000..d4b30e6 --- /dev/null +++ b/.vscode/launch.json @@ -0,0 +1,22 @@ +{ + // 使用 IntelliSense 了解相关属性。 + // 悬停以查看现有属性的描述。 + // 欲了解更多信息，请访问: https://go.microsoft.com/fwlink/?linkid=830387 + "version": "0.2.0", + "configurations": [ + { + "type": "stlinkgdbtarget", + "request": "launch", + "name": "STM32Cube: STM32 Launch ST-Link GDB Server", + "origin": "snippet", + "cwd": "${workspaceFolder}", + "preBuild": "${command:st-stm32-ide-debug-launch.build}", + "runEntry": "main", + "imagesAndSymbols": [ + { + "imageFileName": "${command:st-stm32-ide-debug-launch.get-projects-binary-from-context1}" + } + ] + } + ] +} \ No newline at end of file diff --git a/.vscode/tasks.json b/.vscode/tasks.json new file mode 100644 index 0000000..afb879e --- /dev/null +++ b/.vscode/tasks.json @@ -0,0 +1,17 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "type": "cmake", + "label": "CMake: 清理重新生成", + "command": "cleanRebuild", + "targets": [ + "all" + ], + "preset": "Debug", + "group": "build", + "problemMatcher": [], + "detail": "CMake 模板 清理重新生成 任务" + } + ] +} \ No newline at end of file diff --git a/CMakeLists.txt b/CMakeLists.txt index 8862c33..1509fe2 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -45,11 +45,17 @@ target_link_directories(${CMAKE_PROJECT_NAME} PRIVATE # Add sources to executable target_sources(${CMAKE_PROJECT_NAME} PRIVATE # Add user sources here + Core/Src/easylogger/src/elog.c + Core/Src/easylogger/src/elog_utils.c + Core/Src/easylogger/port/elog_port.c + Core/Src/motor_driver.c + Core/Src/screen.c ) # Add include paths target_include_directories(${CMAKE_PROJECT_NAME} PRIVATE # Add user defined include paths + Core/Src/easylogger/inc ) # Add project symbols (macros) @@ -66,3 +72,8 @@ target_link_libraries(${CMAKE_PROJECT_NAME} # Add user defined libraries ) + +# Enable float support for printf +target_link_options(${CMAKE_PROJECT_NAME} PRIVATE + -u _printf_float +) diff --git a/Core/Inc/FreeRTOSConfig.h b/Core/Inc/FreeRTOSConfig.h index c437c9c..fea531e 100644 --- a/Core/Inc/FreeRTOSConfig.h +++ b/Core/Inc/FreeRTOSConfig.h @@ -64,7 +64,7 @@ #define configTICK_RATE_HZ ((TickType_t)1000) #define configMAX_PRIORITIES ( 56 ) #define configMINIMAL_STACK_SIZE ((uint16_t)128) -#define configTOTAL_HEAP_SIZE ((size_t)3072) +#define configTOTAL_HEAP_SIZE ((size_t)15000) #define configMAX_TASK_NAME_LEN ( 16 ) #define configUSE_TRACE_FACILITY 1 #define configUSE_16_BIT_TICKS 0 diff --git a/Core/Inc/main.h b/Core/Inc/main.h index 9f839eb..38bc400 100644 --- a/Core/Inc/main.h +++ b/Core/Inc/main.h @@ -57,6 +57,8 @@ void Error_Handler(void); /* USER CODE END EFP */ /* Private defines -----------------------------------------------------------*/ +#define HOT_Pin GPIO_PIN_1 +#define HOT_GPIO_Port GPIOA #define RUN_LED_Pin GPIO_PIN_12 #define RUN_LED_GPIO_Port GPIOB #define ERR_LED_Pin GPIO_PIN_13 diff --git a/Core/Inc/screen.h b/Core/Inc/screen.h new file mode 100644 index 0000000..65b731d --- /dev/null +++ b/Core/Inc/screen.h @@ -0,0 +1,73 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file screen.h + * @brief 串口屏驱动接口（用于 JC 系列串口屏，使用 USART1） + ****************************************************************************** + */ +/* USER CODE END Header */ + +#ifndef __SCREEN_H__ +#define __SCREEN_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +/** + * @brief 发送原始命令字符串到屏幕（阻塞直到发送完成） + * @param cmd C 字符串，命令应以";\r\n"结尾 + * @return 0 成功, 负值 错误 + */ +int Screen_SendCmd(const char *cmd); + + +/* 常用封装 - 简短说明见各函数 */ +/** 清屏，layer: 要清除的层号（通常为0） */ +void Screen_Clear(uint8_t layer); +/** 按地址显示图片（addr 为闪存地址） */ +void Screen_DisplayImage(uint32_t addr); +/** 设置背光，val: 0 最亮，255 最暗 */ +void Screen_SetBrightness(uint8_t val); +/** 绘制 16 字号文本（不带背景） */ +void Screen_DrawText16(uint16_t x, uint16_t y, const char *text, uint8_t color); + +/* 额外封装命令 */ +void Screen_SetRotation(uint8_t dir); +void Screen_SetBaud(uint32_t baud); +void Screen_DisplayImageAtAddr(uint32_t addr, uint16_t x, uint16_t y, uint16_t w, uint16_t h, uint8_t mode); +void Screen_DisplayImageByIndex(uint32_t index, uint16_t x, uint16_t y, uint16_t w, uint16_t h, uint8_t mode); +void Screen_Pixel(uint16_t x, uint16_t y, uint8_t color); +void Screen_Line(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint8_t color); +void Screen_Box(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint8_t color); +void Screen_BoxFill(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint8_t color); +void Screen_Circle(uint16_t x, uint16_t y, uint16_t r, uint8_t color); +void Screen_CircleFill(uint16_t x, uint16_t y, uint16_t r, uint8_t color); +void Screen_SetBGColor(uint8_t color); + +/* 带/不带背景的文本 */ +void Screen_DrawText16V(uint16_t x, uint16_t y, const char *text, uint8_t color); +void Screen_DrawText24(uint16_t x, uint16_t y, const char *text, uint8_t color); +void Screen_DrawText24V(uint16_t x, uint16_t y, const char *text, uint8_t color); +void Screen_DrawText32(uint16_t x, uint16_t y, const char *text, uint8_t color); +void Screen_DrawText32V(uint16_t x, uint16_t y, const char *text, uint8_t color); +void Screen_DrawText48(uint16_t x, uint16_t y, const char *text, uint8_t color, uint8_t transparent); + +/* Button */ +void Screen_Button(uint16_t x, uint16_t y, uint16_t w, uint16_t h, const char *label, uint8_t fontColor, uint8_t bgColor, uint8_t pressFlag, uint8_t style); + +/* Qrcode */ +void Screen_QRCode(uint16_t x, uint16_t y, const char *url); +void Screen_QRCodeEx(uint16_t x, uint16_t y, const char *url, uint16_t size, uint8_t color); + +/* 版本信息 */ +void Screen_Ver(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SCREEN_H__ */ diff --git a/Core/Src/adc.c b/Core/Src/adc.c index f0fbcf2..ff62fdc 100644 --- a/Core/Src/adc.c +++ b/Core/Src/adc.c @@ -44,7 +44,7 @@ void MX_ADC1_Init(void) */ hadc1.Instance = ADC1; hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE; - hadc1.Init.ContinuousConvMode = DISABLE; + hadc1.Init.ContinuousConvMode = ENABLE; hadc1.Init.DiscontinuousConvMode = DISABLE; hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; @@ -58,7 +58,7 @@ void MX_ADC1_Init(void) */ sConfig.Channel = ADC_CHANNEL_0; sConfig.Rank = ADC_REGULAR_RANK_1; - sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; + sConfig.SamplingTime = ADC_SAMPLETIME_239CYCLES_5; if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { Error_Handler(); diff --git a/Core/Src/easylogger/inc/elog.h b/Core/Src/easylogger/inc/elog.h new file mode 100644 index 0000000..840ebc2 --- /dev/null +++ b/Core/Src/easylogger/inc/elog.h @@ -0,0 +1,272 @@ +// +// Created by wangb on 25-6-4. +// + +#ifndef ELOG_H +#define ELOG_H + +#include "elog_cfg.h" +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* output log's level */ +#define ELOG_LVL_ASSERT 0 +#define ELOG_LVL_ERROR 1 +#define ELOG_LVL_WARN 2 +#define ELOG_LVL_INFO 3 +#define ELOG_LVL_DEBUG 4 +#define ELOG_LVL_VERBOSE 5 + + +/* the output silent level and all level for filter setting */ +#define ELOG_FILTER_LVL_SILENT ELOG_LVL_ASSERT +#define ELOG_FILTER_LVL_ALL ELOG_LVL_VERBOSE + +/* output log's level total number */ +#define ELOG_LVL_TOTAL_NUM 6 + +/* EasyLogger software version number */ +#define ELOG_SW_VERSION "2.2.99" + +/* EasyLogger assert for developer. */ +#ifdef ELOG_ASSERT_ENABLE + #define ELOG_ASSERT(EXPR) \ + if (!(EXPR)) \ + { \ + if (elog_assert_hook == NULL) { \ + elog_a("elog", "(%s) has assert failed at %s:%ld.", #EXPR, __FUNCTION__, __LINE__); \ + while (1); \ + } else { \ + elog_assert_hook(#EXPR, __FUNCTION__, __LINE__); \ + } \ + } +#else + #define ELOG_ASSERT(EXPR) ((void)0); +#endif + +#ifndef ELOG_OUTPUT_ENABLE + #define elog_raw(...) + #define elog_assert(tag, ...) + #define elog_error(tag, ...) + #define elog_warn(tag, ...) + #define elog_info(tag, ...) + #define elog_debug(tag, ...) + #define elog_verbose(tag, ...) +#else /* ELOG_OUTPUT_ENABLE */ + + #ifdef ELOG_FMT_USING_FUNC + #define ELOG_OUTPUT_FUNC __FUNCTION__ + #else + #define ELOG_OUTPUT_FUNC NULL + #endif + + #ifdef ELOG_FMT_USING_DIR + #define ELOG_OUTPUT_DIR __FILE__ + #else + #define ELOG_OUTPUT_DIR NULL + #endif + + #ifdef ELOG_FMT_USING_LINE + #define ELOG_OUTPUT_LINE __LINE__ + #else + #define ELOG_OUTPUT_LINE 0 + #endif + + #define elog_raw(...) elog_raw_output(__VA_ARGS__) + #if ELOG_OUTPUT_LVL >= ELOG_LVL_ASSERT + #define elog_assert(tag, ...) \ + elog_output(ELOG_LVL_ASSERT, tag, ELOG_OUTPUT_DIR, ELOG_OUTPUT_FUNC, ELOG_OUTPUT_LINE, __VA_ARGS__) + #else + #define elog_assert(tag, ...) + #endif /* ELOG_OUTPUT_LVL >= ELOG_LVL_ASSERT */ + + #if ELOG_OUTPUT_LVL >= ELOG_LVL_ERROR + #define elog_error(tag, ...) \ + elog_output(ELOG_LVL_ERROR, tag, ELOG_OUTPUT_DIR, ELOG_OUTPUT_FUNC, ELOG_OUTPUT_LINE, __VA_ARGS__) + #else + #define elog_error(tag, ...) + #endif /* ELOG_OUTPUT_LVL >= ELOG_LVL_ERROR */ + + #if ELOG_OUTPUT_LVL >= ELOG_LVL_WARN + #define elog_warn(tag, ...) \ + elog_output(ELOG_LVL_WARN, tag, ELOG_OUTPUT_DIR, ELOG_OUTPUT_FUNC, ELOG_OUTPUT_LINE, __VA_ARGS__) + #else + #define elog_warn(tag, ...) + #endif /* ELOG_OUTPUT_LVL >= ELOG_LVL_WARN */ + + #if ELOG_OUTPUT_LVL >= ELOG_LVL_INFO + #define elog_info(tag, ...) \ + elog_output(ELOG_LVL_INFO, tag, ELOG_OUTPUT_DIR, ELOG_OUTPUT_FUNC, ELOG_OUTPUT_LINE, __VA_ARGS__) + #else + #define elog_info(tag, ...) + #endif /* ELOG_OUTPUT_LVL >= ELOG_LVL_INFO */ + + #if ELOG_OUTPUT_LVL >= ELOG_LVL_DEBUG + #define elog_debug(tag, ...) \ + elog_output(ELOG_LVL_DEBUG, tag, ELOG_OUTPUT_DIR, ELOG_OUTPUT_FUNC, ELOG_OUTPUT_LINE, __VA_ARGS__) + #else + #define elog_debug(tag, ...) + #endif /* ELOG_OUTPUT_LVL >= ELOG_LVL_DEBUG */ + + #if ELOG_OUTPUT_LVL == ELOG_LVL_VERBOSE + #define elog_verbose(tag, ...) \ + elog_output(ELOG_LVL_VERBOSE, tag, ELOG_OUTPUT_DIR, ELOG_OUTPUT_FUNC, ELOG_OUTPUT_LINE, __VA_ARGS__) + #else + #define elog_verbose(tag, ...) + #endif /* ELOG_OUTPUT_LVL == ELOG_LVL_VERBOSE */ +#endif /* ELOG_OUTPUT_ENABLE */ + +/* all formats index */ +typedef enum { + ELOG_FMT_LVL = 1 << 0, /**< level */ + ELOG_FMT_TAG = 1 << 1, /**< tag */ + ELOG_FMT_TIME = 1 << 2, /**< current time */ + ELOG_FMT_P_INFO = 1 << 3, /**< process info */ + ELOG_FMT_T_INFO = 1 << 4, /**< thread info */ + ELOG_FMT_DIR = 1 << 5, /**< file directory and name */ + ELOG_FMT_FUNC = 1 << 6, /**< function name */ + ELOG_FMT_LINE = 1 << 7, /**< line number */ +} ElogFmtIndex; + +/* macro definition for all formats */ +#define ELOG_FMT_ALL (ELOG_FMT_LVL|ELOG_FMT_TAG|ELOG_FMT_TIME|ELOG_FMT_P_INFO|ELOG_FMT_T_INFO| \ + ELOG_FMT_DIR|ELOG_FMT_FUNC|ELOG_FMT_LINE) + +/* output log's tag filter */ +typedef struct { + uint8_t level; + char tag[ELOG_FILTER_TAG_MAX_LEN + 1]; + bool tag_use_flag; /**< false : tag is no used true: tag is used */ +} ElogTagLvlFilter, *ElogTagLvlFilter_t; + +/* output log's filter */ +typedef struct { + uint8_t level; + char tag[ELOG_FILTER_TAG_MAX_LEN + 1]; + char keyword[ELOG_FILTER_KW_MAX_LEN + 1]; + ElogTagLvlFilter tag_lvl[ELOG_FILTER_TAG_LVL_MAX_NUM]; +} ElogFilter, *ElogFilter_t; + +/* easy logger */ +typedef struct { + ElogFilter filter; + size_t enabled_fmt_set[ELOG_LVL_TOTAL_NUM]; + bool init_ok; + bool output_enabled; + bool output_lock_enabled; + bool output_is_locked_before_enable; + bool output_is_locked_before_disable; + +#ifdef ELOG_COLOR_ENABLE + bool text_color_enabled; +#endif + +}EasyLogger, *EasyLogger_t; + +/* EasyLogger error code */ +typedef enum { + ELOG_NO_ERR, +} ElogErrCode; + +/* elog.c */ +ElogErrCode elog_init(void); +void elog_deinit(void); +void elog_start(void); +void elog_stop(void); +void elog_set_output_enabled(bool enabled); +bool elog_get_output_enabled(void); +void elog_set_text_color_enabled(bool enabled); +bool elog_get_text_color_enabled(void); +void elog_set_fmt(uint8_t level, size_t set); +void elog_set_filter(uint8_t level, const char *tag, const char *keyword); +void elog_set_filter_lvl(uint8_t level); +void elog_set_filter_tag(const char *tag); +void elog_set_filter_kw(const char *keyword); +void elog_set_filter_tag_lvl(const char *tag, uint8_t level); +uint8_t elog_get_filter_tag_lvl(const char *tag); +void elog_raw_output(const char *format, ...); +void elog_output(uint8_t level, const char *tag, const char *file, const char *func, + const long line, const char *format, ...); +void elog_output_lock_enabled(bool enabled); +extern void (*elog_assert_hook)(const char* expr, const char* func, size_t line); +void elog_assert_set_hook(void (*hook)(const char* expr, const char* func, size_t line)); +int8_t elog_find_lvl(const char *log); +const char *elog_find_tag(const char *log, uint8_t lvl, size_t *tag_len); +void elog_hexdump(const char *name, uint8_t width, const void *buf, uint16_t size); + +#define elog_a(tag, ...) elog_assert(tag, __VA_ARGS__) +#define elog_e(tag, ...) elog_error(tag, __VA_ARGS__) +#define elog_w(tag, ...) elog_warn(tag, __VA_ARGS__) +#define elog_i(tag, ...) elog_info(tag, __VA_ARGS__) +#define elog_d(tag, ...) elog_debug(tag, __VA_ARGS__) +#define elog_v(tag, ...) elog_verbose(tag, __VA_ARGS__) + +/** + * log API short definition + * NOTE: The `LOG_TAG` and `LOG_LVL` must defined before including the when you want to use log_x API. + */ +#if !defined(LOG_TAG) + #define LOG_TAG "NO_TAG" +#endif +#if !defined(LOG_LVL) + #define LOG_LVL ELOG_LVL_VERBOSE +#endif +#if LOG_LVL >= ELOG_LVL_ASSERT + #define log_a(...) elog_a(LOG_TAG, __VA_ARGS__) +#else + #define log_a(...) ((void)0); +#endif +#if LOG_LVL >= ELOG_LVL_ERROR + #define log_e(...) elog_e(LOG_TAG, __VA_ARGS__) +#else + #define log_e(...) ((void)0); +#endif +#if LOG_LVL >= ELOG_LVL_WARN + #define log_w(...) elog_w(LOG_TAG, __VA_ARGS__) +#else + #define log_w(...) ((void)0); +#endif +#if LOG_LVL >= ELOG_LVL_INFO + #define log_i(...) elog_i(LOG_TAG, __VA_ARGS__) +#else + #define log_i(...) ((void)0); +#endif +#if LOG_LVL >= ELOG_LVL_DEBUG + #define log_d(...) elog_d(LOG_TAG, __VA_ARGS__) +#else + #define log_d(...) ((void)0); +#endif +#if LOG_LVL >= ELOG_LVL_VERBOSE + #define log_v(...) elog_v(LOG_TAG, __VA_ARGS__) +#else + #define log_v(...) ((void)0); +#endif + +/* assert API short definition */ +#if !defined(assert) + #define assert ELOG_ASSERT +#endif + +/* elog_buf.c */ +void elog_buf_enabled(bool enabled); +void elog_flush(void); + +/* elog_async.c */ +void elog_async_enabled(bool enabled); +size_t elog_async_get_log(char *log, size_t size); +size_t elog_async_get_line_log(char *log, size_t size); + +/* elog_utils.c */ +size_t elog_strcpy(size_t cur_len, char *dst, const char *src); +size_t elog_cpyln(char *line, const char *log, size_t len); +void *elog_memcpy(void *dst, const void *src, size_t count); +void easylogger_init(void); +#ifdef __cplusplus +} +#endif +#endif //ELOG_H diff --git a/Core/Src/easylogger/inc/elog_cfg.h b/Core/Src/easylogger/inc/elog_cfg.h new file mode 100644 index 0000000..8304b83 --- /dev/null +++ b/Core/Src/easylogger/inc/elog_cfg.h @@ -0,0 +1,59 @@ +// +// Created by wangb on 25-6-4. +// + +#ifndef _ELOG_CFG_H_ +#define _ELOG_CFG_H_ +/*---------------------------------------------------------------------------*/ +/* enable log output. */ +#define ELOG_OUTPUT_ENABLE +/* setting static output log level. range: from ELOG_LVL_ASSERT to ELOG_LVL_VERBOSE */ +#define ELOG_OUTPUT_LVL ELOG_LVL_VERBOSE +/* enable assert check */ +#define ELOG_ASSERT_ENABLE +/* buffer size for every line's log */ +#define ELOG_LINE_BUF_SIZE 1024 +/* output line number max length */ +#define ELOG_LINE_NUM_MAX_LEN 5 +/* output filter's tag max length */ +#define ELOG_FILTER_TAG_MAX_LEN 30 +/* output filter's keyword max length */ +#define ELOG_FILTER_KW_MAX_LEN 16 +/* output filter's tag level max num */ +#define ELOG_FILTER_TAG_LVL_MAX_NUM 5 +/* output newline sign */ +#define ELOG_NEWLINE_SIGN "\r\n" //换行 +/*---------------------------------------------------------------------------*/ +/* enable log color */ +#define ELOG_COLOR_ENABLE +/* change the some level logs to not default color if you want */ +#define ELOG_COLOR_ASSERT (F_MAGENTA B_NULL S_NORMAL) +#define ELOG_COLOR_ERROR (F_RED B_NULL S_NORMAL) +#define ELOG_COLOR_WARN (F_YELLOW B_NULL S_NORMAL) +#define ELOG_COLOR_INFO (F_CYAN B_NULL S_NORMAL) +#define ELOG_COLOR_DEBUG (F_GREEN B_NULL S_NORMAL) +#define ELOG_COLOR_VERBOSE (F_BLUE B_NULL S_NORMAL) +/*---------------------------------------------------------------------------*/ +/* enable log fmt */ +/* comment it if you don't want to output them at all */ +#define ELOG_FMT_USING_FUNC +#define ELOG_FMT_USING_DIR +#define ELOG_FMT_USING_LINE +/*---------------------------------------------------------------------------*/ +/* enable asynchronous output mode */ +//#define ELOG_ASYNC_OUTPUT_ENABLE +/* the highest output level for async mode, other level will sync output */ +#define ELOG_ASYNC_OUTPUT_LVL ELOG_LVL_ASSERT +/* buffer size for asynchronous output mode */ +#define ELOG_ASYNC_OUTPUT_BUF_SIZE (ELOG_LINE_BUF_SIZE * 10) +/* each asynchronous output's log which must end with newline sign */ +#define ELOG_ASYNC_LINE_OUTPUT +/* asynchronous output mode using POSIX pthread implementation */ +#define ELOG_ASYNC_OUTPUT_USING_PTHREAD +/*---------------------------------------------------------------------------*/ +/* enable buffered output mode */ +//#define ELOG_BUF_OUTPUT_ENABLE +/* buffer size for buffered output mode */ +#define ELOG_BUF_OUTPUT_BUF_SIZE (ELOG_LINE_BUF_SIZE * 10) + +#endif /* _ELOG_CFG_H_ */ diff --git a/Core/Src/easylogger/port/elog_port.c b/Core/Src/easylogger/port/elog_port.c new file mode 100644 index 0000000..4c28405 --- /dev/null +++ b/Core/Src/easylogger/port/elog_port.c @@ -0,0 +1,114 @@ +// +// Created by wangb on 25-6-4. +// + +#include "elog.h" + +#include +#include "main.h" + +/** + * EasyLogger port initialize + * + * @return result + */ +ElogErrCode elog_port_init(void) { + ElogErrCode result = ELOG_NO_ERR; + + /* add your code here */ + + + return result; +} + +/** + * EasyLogger port deinitialize + * + */ +void elog_port_deinit(void) { + /* add your code here */ +} + +/** + * output log port interface + * + * @param log output of log + * @param size log size + */ +void elog_port_output(const char *log, size_t size) { + /* add your code here */ + printf("%.*s", size, log); //elog 的输出 +} + +/** + * output lock + */ +void elog_port_output_lock(void) { + /* add your code here */ + + __disable_irq(); //关闭全局中断 +} + +/** + * output unlock + */ +void elog_port_output_unlock(void) { + /* add your code here */ + __enable_irq(); //开启全局中断 +} + + + +#include + +/** + * get current time interface + * + * @return current time + */ +const char *elog_port_get_time(void) { + + + return ""; +} + + +/** + * get current process name interface + * + * @return current process name + */ +const char *elog_port_get_p_info(void) { + /* add your code here */ + return ""; +} + +/** + * get current thread name interface + * + * @return current thread name + */ +const char *elog_port_get_t_info(void) { + /* add your code here */ + //获取STM32 的线程接口 + + + return ""; +} + +void easylogger_init(void) { + /* init Easylogger */ + elog_init(); + + /* set EasyLogger log format */ + elog_set_fmt(ELOG_LVL_ASSERT, ELOG_FMT_ALL & ~ELOG_FMT_P_INFO); + elog_set_fmt(ELOG_LVL_ERROR, ELOG_FMT_LVL | ELOG_FMT_TAG | ELOG_FMT_TIME); + elog_set_fmt(ELOG_LVL_WARN, ELOG_FMT_LVL | ELOG_FMT_TAG | ELOG_FMT_TIME); + elog_set_fmt(ELOG_LVL_INFO, ELOG_FMT_LVL | ELOG_FMT_TAG | ELOG_FMT_TIME); + elog_set_fmt(ELOG_LVL_DEBUG, ELOG_FMT_ALL & ~(ELOG_FMT_FUNC | ELOG_FMT_P_INFO)); + elog_set_fmt(ELOG_LVL_VERBOSE, ELOG_FMT_ALL & ~(ELOG_FMT_FUNC | ELOG_FMT_P_INFO)); + + + /* start EasyLogger */ + elog_start(); +} diff --git a/Core/Src/easylogger/src/elog.c b/Core/Src/easylogger/src/elog.c new file mode 100644 index 0000000..245284d --- /dev/null +++ b/Core/Src/easylogger/src/elog.c @@ -0,0 +1,912 @@ +// +// Created by wangb on 25-6-4. +// + + +#define LOG_TAG "elog" + +#include "elog.h" +#include +#include +#include + +#if !defined(ELOG_OUTPUT_LVL) + #error "Please configure static output log level (in elog_cfg.h)" +#endif + +#if !defined(ELOG_LINE_NUM_MAX_LEN) + #error "Please configure output line number max length (in elog_cfg.h)" +#endif + +#if !defined(ELOG_LINE_BUF_SIZE) + #error "Please configure buffer size for every line's log (in elog_cfg.h)" +#endif + +#if !defined(ELOG_FILTER_TAG_MAX_LEN) + #error "Please configure output filter's tag max length (in elog_cfg.h)" +#endif + +#if !defined(ELOG_FILTER_KW_MAX_LEN) + #error "Please configure output filter's keyword max length (in elog_cfg.h)" +#endif + +#if !defined(ELOG_NEWLINE_SIGN) + #error "Please configure output newline sign (in elog_cfg.h)" +#endif + +/* output filter's tag level max num */ +#ifndef ELOG_FILTER_TAG_LVL_MAX_NUM +#define ELOG_FILTER_TAG_LVL_MAX_NUM 4 +#endif + +#ifdef ELOG_COLOR_ENABLE +/** + * CSI(Control Sequence Introducer/Initiator) sign + * more information on https://en.wikipedia.org/wiki/ANSI_escape_code + */ +#define CSI_START "\033[" +#define CSI_END "\033[0m" +/* output log front color */ +#define F_BLACK "30;" +#define F_RED "31;" +#define F_GREEN "32;" +#define F_YELLOW "33;" +#define F_BLUE "34;" +#define F_MAGENTA "35;" +#define F_CYAN "36;" +#define F_WHITE "37;" +/* output log background color */ +#define B_NULL +#define B_BLACK "40;" +#define B_RED "41;" +#define B_GREEN "42;" +#define B_YELLOW "43;" +#define B_BLUE "44;" +#define B_MAGENTA "45;" +#define B_CYAN "46;" +#define B_WHITE "47;" +/* output log fonts style */ +#define S_BOLD "1m" +#define S_UNDERLINE "4m" +#define S_BLINK "5m" +#define S_NORMAL "22m" +/* output log default color definition: [front color] + [background color] + [show style] */ +#ifndef ELOG_COLOR_ASSERT +#define ELOG_COLOR_ASSERT (F_MAGENTA B_NULL S_NORMAL) +#endif +#ifndef ELOG_COLOR_ERROR +#define ELOG_COLOR_ERROR (F_RED B_NULL S_NORMAL) +#endif +#ifndef ELOG_COLOR_WARN +#define ELOG_COLOR_WARN (F_YELLOW B_NULL S_NORMAL) +#endif +#ifndef ELOG_COLOR_INFO +#define ELOG_COLOR_INFO (F_CYAN B_NULL S_NORMAL) +#endif +#ifndef ELOG_COLOR_DEBUG +#define ELOG_COLOR_DEBUG (F_GREEN B_NULL S_NORMAL) +#endif +#ifndef ELOG_COLOR_VERBOSE +#define ELOG_COLOR_VERBOSE (F_BLUE B_NULL S_NORMAL) +#endif +#endif /* ELOG_COLOR_ENABLE */ + +/* EasyLogger object */ +static EasyLogger elog; +/* every line log's buffer */ +static char log_buf[ELOG_LINE_BUF_SIZE] = { 0 }; +/* level output info */ +static const char *level_output_info[] = { + [ELOG_LVL_ASSERT] = "ASSERT/", + [ELOG_LVL_ERROR] = "ERROR/", + [ELOG_LVL_WARN] = "WARN/", + [ELOG_LVL_INFO] = "INFO/", + [ELOG_LVL_DEBUG] = "DEBUG/", + [ELOG_LVL_VERBOSE] = "VERBOS/", +}; + +#ifdef ELOG_COLOR_ENABLE +/* color output info */ +static const char *color_output_info[] = { + [ELOG_LVL_ASSERT] = ELOG_COLOR_ASSERT, + [ELOG_LVL_ERROR] = ELOG_COLOR_ERROR, + [ELOG_LVL_WARN] = ELOG_COLOR_WARN, + [ELOG_LVL_INFO] = ELOG_COLOR_INFO, + [ELOG_LVL_DEBUG] = ELOG_COLOR_DEBUG, + [ELOG_LVL_VERBOSE] = ELOG_COLOR_VERBOSE, +}; +#endif /* ELOG_COLOR_ENABLE */ + +static bool get_fmt_enabled(uint8_t level, size_t set); +static bool get_fmt_used_and_enabled_u32(uint8_t level, size_t set, uint32_t arg); +static bool get_fmt_used_and_enabled_ptr(uint8_t level, size_t set, const char* arg); +static void elog_set_filter_tag_lvl_default(void); + +/* EasyLogger assert hook */ +void (*elog_assert_hook)(const char* expr, const char* func, size_t line); + +extern void elog_port_output(const char *log, size_t size); +extern void elog_port_output_lock(void); +extern void elog_port_output_unlock(void); + +/** + * EasyLogger initialize. + * + * @return result + */ +ElogErrCode elog_init(void) { + extern ElogErrCode elog_port_init(void); + extern ElogErrCode elog_async_init(void); + + ElogErrCode result = ELOG_NO_ERR; + + if (elog.init_ok == true) { + return result; + } + + /* port initialize */ + result = elog_port_init(); + if (result != ELOG_NO_ERR) { + return result; + } + +#ifdef ELOG_ASYNC_OUTPUT_ENABLE + result = elog_async_init(); + if (result != ELOG_NO_ERR) { + return result; + } +#endif + + /* enable the output lock */ + elog_output_lock_enabled(true); + /* output locked status initialize */ + elog.output_is_locked_before_enable = false; + elog.output_is_locked_before_disable = false; + +#ifdef ELOG_COLOR_ENABLE + /* enable text color by default */ + elog_set_text_color_enabled(true); +#endif + + /* set level is ELOG_LVL_VERBOSE */ + elog_set_filter_lvl(ELOG_LVL_VERBOSE); + + /* set tag_level to default val */ + elog_set_filter_tag_lvl_default(); + + elog.init_ok = true; + + return result; +} + +/** + * EasyLogger deinitialize. + * + */ +void elog_deinit(void) { + extern ElogErrCode elog_port_deinit(void); + extern ElogErrCode elog_async_deinit(void); + + if (!elog.init_ok) { + return ; + } + +#ifdef ELOG_ASYNC_OUTPUT_ENABLE + elog_async_deinit(); +#endif + + /* port deinitialize */ + elog_port_deinit(); + + elog.init_ok = false; +} + + +/** + * EasyLogger start after initialize. + */ +void elog_start(void) { + if (!elog.init_ok) { + return ; + } + + /* enable output */ + elog_set_output_enabled(true); + +#if defined(ELOG_ASYNC_OUTPUT_ENABLE) + elog_async_enabled(true); +#elif defined(ELOG_BUF_OUTPUT_ENABLE) + elog_buf_enabled(true); +#endif + + +} + +/** + * EasyLogger stop after initialize. + */ +void elog_stop(void) { + if (!elog.init_ok) { + return ; + } + + /* disable output */ + elog_set_output_enabled(false); + +#if defined(ELOG_ASYNC_OUTPUT_ENABLE) + elog_async_enabled(false); +#elif defined(ELOG_BUF_OUTPUT_ENABLE) + elog_buf_enabled(false); +#endif + + /* show version */ + log_i("EasyLogger V%s is deinitialize success.", ELOG_SW_VERSION); +} + + +/** + * set output enable or disable + * + * @param enabled TRUE: enable FALSE: disable + */ +void elog_set_output_enabled(bool enabled) { + ELOG_ASSERT((enabled == false) || (enabled == true)); + + elog.output_enabled = enabled; +} + +#ifdef ELOG_COLOR_ENABLE +/** + * set log text color enable or disable + * + * @param enabled TRUE: enable FALSE:disable + */ +void elog_set_text_color_enabled(bool enabled) { + ELOG_ASSERT((enabled == false) || (enabled == true)); + + elog.text_color_enabled = enabled; +} + +/** + * get log text color enable status + * + * @return enable or disable + */ +bool elog_get_text_color_enabled(void) { + return elog.text_color_enabled; +} +#endif /* ELOG_COLOR_ENABLE */ + +/** + * get output is enable or disable + * + * @return enable or disable + */ +bool elog_get_output_enabled(void) { + return elog.output_enabled; +} + +/** + * set log output format. only enable or disable + * + * @param level level + * @param set format set + */ +void elog_set_fmt(uint8_t level, size_t set) { + ELOG_ASSERT(level <= ELOG_LVL_VERBOSE); + + elog.enabled_fmt_set[level] = set; +} + +/** + * set log filter all parameter + * + * @param level level + * @param tag tag + * @param keyword keyword + */ +void elog_set_filter(uint8_t level, const char *tag, const char *keyword) { + ELOG_ASSERT(level <= ELOG_LVL_VERBOSE); + + elog_set_filter_lvl(level); + elog_set_filter_tag(tag); + elog_set_filter_kw(keyword); +} + +/** + * set log filter's level + * + * @param level level + */ +void elog_set_filter_lvl(uint8_t level) { + ELOG_ASSERT(level <= ELOG_LVL_VERBOSE); + + elog.filter.level = level; +} + +/** + * set log filter's tag + * + * @param tag tag + */ +void elog_set_filter_tag(const char *tag) { + strncpy(elog.filter.tag, tag, ELOG_FILTER_TAG_MAX_LEN); +} + +/** + * set log filter's keyword + * + * @param keyword keyword + */ +void elog_set_filter_kw(const char *keyword) { + strncpy(elog.filter.keyword, keyword, ELOG_FILTER_KW_MAX_LEN); +} + +/** + * lock output + */ +void elog_output_lock(void) { + if (elog.output_lock_enabled) { + elog_port_output_lock(); + elog.output_is_locked_before_disable = true; + } else { + elog.output_is_locked_before_enable = true; + } +} + +/** + * unlock output + */ +void elog_output_unlock(void) { + if (elog.output_lock_enabled) { + elog_port_output_unlock(); + elog.output_is_locked_before_disable = false; + } else { + elog.output_is_locked_before_enable = false; + } +} + +/** + * set log filter's tag level val to default + */ +static void elog_set_filter_tag_lvl_default(void) +{ + uint8_t i = 0; + + for (i =0; i< ELOG_FILTER_TAG_LVL_MAX_NUM; i++){ + memset(elog.filter.tag_lvl[i].tag, '\0', ELOG_FILTER_TAG_MAX_LEN + 1); + elog.filter.tag_lvl[i].level = ELOG_FILTER_LVL_SILENT; + elog.filter.tag_lvl[i].tag_use_flag = false; + } +} + +/** + * Set the filter's level by different tag. + * The log on this tag which level is less than it will stop output. + * + * example: + * // the example tag log enter silent mode + * elog_set_filter_tag_lvl("example", ELOG_FILTER_LVL_SILENT); + * // the example tag log which level is less than INFO level will stop output + * elog_set_filter_tag_lvl("example", ELOG_LVL_INFO); + * // remove example tag's level filter, all level log will resume output + * elog_set_filter_tag_lvl("example", ELOG_FILTER_LVL_ALL); + * + * @param tag log tag + * @param level The filter level. When the level is ELOG_FILTER_LVL_SILENT, the log enter silent mode. + * When the level is ELOG_FILTER_LVL_ALL, it will remove this tag's level filer. + * Then all level log will resume output. + * + */ +void elog_set_filter_tag_lvl(const char *tag, uint8_t level) +{ + ELOG_ASSERT(level <= ELOG_LVL_VERBOSE); + ELOG_ASSERT(tag != ((void *)0)); + uint8_t i = 0; + + if (!elog.init_ok) { + return; + } + + elog_output_lock(); + /* find the tag in arr */ + for (i =0; i< ELOG_FILTER_TAG_LVL_MAX_NUM; i++){ + if (elog.filter.tag_lvl[i].tag_use_flag == true && + !strncmp(tag, elog.filter.tag_lvl[i].tag,ELOG_FILTER_TAG_MAX_LEN)){ + break; + } + } + + if (i < ELOG_FILTER_TAG_LVL_MAX_NUM){ + /* find OK */ + if (level == ELOG_FILTER_LVL_ALL){ + /* remove current tag's level filter when input level is the lowest level */ + elog.filter.tag_lvl[i].tag_use_flag = false; + memset(elog.filter.tag_lvl[i].tag, '\0', ELOG_FILTER_TAG_MAX_LEN + 1); + elog.filter.tag_lvl[i].level = ELOG_FILTER_LVL_SILENT; + } else{ + elog.filter.tag_lvl[i].level = level; + } + } else{ + /* only add the new tag's level filer when level is not ELOG_FILTER_LVL_ALL */ + if (level != ELOG_FILTER_LVL_ALL){ + for (i =0; i< ELOG_FILTER_TAG_LVL_MAX_NUM; i++){ + if (elog.filter.tag_lvl[i].tag_use_flag == false){ + strncpy(elog.filter.tag_lvl[i].tag, tag, ELOG_FILTER_TAG_MAX_LEN); + elog.filter.tag_lvl[i].level = level; + elog.filter.tag_lvl[i].tag_use_flag = true; + break; + } + } + } + } + elog_output_unlock(); +} + +/** + * get the level on tag's level filer + * + * @param tag tag + * + * @return It will return the lowest level when tag was not found. + * Other level will return when tag was found. + */ +uint8_t elog_get_filter_tag_lvl(const char *tag) +{ + ELOG_ASSERT(tag != ((void *)0)); + uint8_t i = 0; + uint8_t level = ELOG_FILTER_LVL_ALL; + + if (!elog.init_ok) { + return level; + } + + elog_output_lock(); + /* find the tag in arr */ + for (i =0; i< ELOG_FILTER_TAG_LVL_MAX_NUM; i++){ + if (elog.filter.tag_lvl[i].tag_use_flag == true && + !strncmp(tag, elog.filter.tag_lvl[i].tag,ELOG_FILTER_TAG_MAX_LEN)){ + level = elog.filter.tag_lvl[i].level; + break; + } + } + elog_output_unlock(); + + return level; +} + +/** + * output RAW format log + * + * @param format output format + * @param ... args + */ +void elog_raw_output(const char *format, ...) { + va_list args; + size_t log_len = 0; + int fmt_result; + + /* check output enabled */ + if (!elog.output_enabled) { + return; + } + + /* args point to the first variable parameter */ + va_start(args, format); + + /* lock output */ + elog_output_lock(); + + /* package log data to buffer */ + fmt_result = vsnprintf(log_buf, ELOG_LINE_BUF_SIZE, format, args); + + /* output converted log */ + if ((fmt_result > -1) && (fmt_result <= ELOG_LINE_BUF_SIZE)) { + log_len = fmt_result; + } else { + log_len = ELOG_LINE_BUF_SIZE; + } + /* output log */ +#if defined(ELOG_ASYNC_OUTPUT_ENABLE) + extern void elog_async_output(uint8_t level, const char *log, size_t size); + /* raw log will using assert level */ + elog_async_output(ELOG_LVL_ASSERT, log_buf, log_len); +#elif defined(ELOG_BUF_OUTPUT_ENABLE) + extern void elog_buf_output(const char *log, size_t size); + elog_buf_output(log_buf, log_len); +#else + elog_port_output(log_buf, log_len); +#endif + /* unlock output */ + elog_output_unlock(); + + va_end(args); +} + +/** + * output the log + * + * @param level level + * @param tag tag + * @param file file name + * @param func function name + * @param line line number + * @param format output format + * @param ... args + * + */ +void elog_output(uint8_t level, const char *tag, const char *file, const char *func, + const long line, const char *format, ...) { + extern const char *elog_port_get_time(void); + extern const char *elog_port_get_p_info(void); + extern const char *elog_port_get_t_info(void); + + size_t tag_len = strlen(tag), log_len = 0, newline_len = strlen(ELOG_NEWLINE_SIGN); + char line_num[ELOG_LINE_NUM_MAX_LEN + 1] = { 0 }; + char tag_sapce[ELOG_FILTER_TAG_MAX_LEN / 2 + 1] = { 0 }; + va_list args; + int fmt_result; + + ELOG_ASSERT(level <= ELOG_LVL_VERBOSE); + + /* check output enabled */ + if (!elog.output_enabled) { + return; + } + /* level filter */ + if (level > elog.filter.level || level > elog_get_filter_tag_lvl(tag)) { + return; + } else if (!strstr(tag, elog.filter.tag)) { /* tag filter */ + return; + } + /* args point to the first variable parameter */ + va_start(args, format); + /* lock output */ + elog_output_lock(); + +#ifdef ELOG_COLOR_ENABLE + /* add CSI start sign and color info */ + if (elog.text_color_enabled) { + log_len += elog_strcpy(log_len, log_buf + log_len, CSI_START); + log_len += elog_strcpy(log_len, log_buf + log_len, color_output_info[level]); + } +#endif + + /* package level info */ + if (get_fmt_enabled(level, ELOG_FMT_LVL)) { + log_len += elog_strcpy(log_len, log_buf + log_len, level_output_info[level]); + } + /* package tag info */ + if (get_fmt_enabled(level, ELOG_FMT_TAG)) { + log_len += elog_strcpy(log_len, log_buf + log_len, tag); + /* if the tag length is less than 50% ELOG_FILTER_TAG_MAX_LEN, then fill space */ + if (tag_len <= ELOG_FILTER_TAG_MAX_LEN / 2) { + memset(tag_sapce, ' ', ELOG_FILTER_TAG_MAX_LEN / 2 - tag_len); + log_len += elog_strcpy(log_len, log_buf + log_len, tag_sapce); + } + log_len += elog_strcpy(log_len, log_buf + log_len, " "); + } + /* package time, process and thread info */ + if (get_fmt_enabled(level, ELOG_FMT_TIME | ELOG_FMT_P_INFO | ELOG_FMT_T_INFO)) { + log_len += elog_strcpy(log_len, log_buf + log_len, "["); + /* package time info */ + if (get_fmt_enabled(level, ELOG_FMT_TIME)) { + log_len += elog_strcpy(log_len, log_buf + log_len, elog_port_get_time()); + if (get_fmt_enabled(level, ELOG_FMT_P_INFO | ELOG_FMT_T_INFO)) { + log_len += elog_strcpy(log_len, log_buf + log_len, " "); + } + } + /* package process info */ + if (get_fmt_enabled(level, ELOG_FMT_P_INFO)) { + log_len += elog_strcpy(log_len, log_buf + log_len, elog_port_get_p_info()); + if (get_fmt_enabled(level, ELOG_FMT_T_INFO)) { + log_len += elog_strcpy(log_len, log_buf + log_len, " "); + } + } + /* package thread info */ + if (get_fmt_enabled(level, ELOG_FMT_T_INFO)) { + log_len += elog_strcpy(log_len, log_buf + log_len, elog_port_get_t_info()); + } + log_len += elog_strcpy(log_len, log_buf + log_len, "] "); + } + /* package file directory and name, function name and line number info */ + if (get_fmt_used_and_enabled_ptr(level, ELOG_FMT_DIR, file) || + get_fmt_used_and_enabled_ptr(level, ELOG_FMT_FUNC, func) || + get_fmt_used_and_enabled_u32(level, ELOG_FMT_LINE, line)) { + log_len += elog_strcpy(log_len, log_buf + log_len, "("); + /* package file info */ + if (get_fmt_used_and_enabled_ptr(level, ELOG_FMT_DIR, file)) { + log_len += elog_strcpy(log_len, log_buf + log_len, file); + if (get_fmt_used_and_enabled_ptr(level, ELOG_FMT_FUNC, func)) { + log_len += elog_strcpy(log_len, log_buf + log_len, ":"); + } else if (get_fmt_used_and_enabled_u32(level, ELOG_FMT_LINE, line)) { + log_len += elog_strcpy(log_len, log_buf + log_len, " "); + } + } + /* package line info */ + if (get_fmt_used_and_enabled_u32(level, ELOG_FMT_LINE, line)) { + snprintf(line_num, ELOG_LINE_NUM_MAX_LEN, "%ld", line); + log_len += elog_strcpy(log_len, log_buf + log_len, line_num); + if (get_fmt_used_and_enabled_ptr(level, ELOG_FMT_FUNC, func)) { + log_len += elog_strcpy(log_len, log_buf + log_len, " "); + } + } + /* package func info */ + if (get_fmt_used_and_enabled_ptr(level, ELOG_FMT_FUNC, func)) { + log_len += elog_strcpy(log_len, log_buf + log_len, func); + + } + log_len += elog_strcpy(log_len, log_buf + log_len, ")"); + } + /* package other log data to buffer. '\0' must be added in the end by vsnprintf. */ + fmt_result = vsnprintf(log_buf + log_len, ELOG_LINE_BUF_SIZE - log_len, format, args); + + va_end(args); + /* calculate log length */ + if ((log_len + fmt_result <= ELOG_LINE_BUF_SIZE) && (fmt_result > -1)) { + log_len += fmt_result; + } else { + /* using max length */ + log_len = ELOG_LINE_BUF_SIZE; + } + /* overflow check and reserve some space for CSI end sign and newline sign */ +#ifdef ELOG_COLOR_ENABLE + if (log_len + (sizeof(CSI_END) - 1) + newline_len > ELOG_LINE_BUF_SIZE) { + /* using max length */ + log_len = ELOG_LINE_BUF_SIZE; + /* reserve some space for CSI end sign */ + log_len -= (sizeof(CSI_END) - 1); +#else + if (log_len + newline_len > ELOG_LINE_BUF_SIZE) { + /* using max length */ + log_len = ELOG_LINE_BUF_SIZE; +#endif /* ELOG_COLOR_ENABLE */ + /* reserve some space for newline sign */ + log_len -= newline_len; + } + /* keyword filter */ + if (elog.filter.keyword[0] != '\0') { + /* add string end sign */ + log_buf[log_len] = '\0'; + /* find the keyword */ + if (!strstr(log_buf, elog.filter.keyword)) { + /* unlock output */ + elog_output_unlock(); + return; + } + } + +#ifdef ELOG_COLOR_ENABLE + /* add CSI end sign */ + if (elog.text_color_enabled) { + log_len += elog_strcpy(log_len, log_buf + log_len, CSI_END); + } +#endif + + /* package newline sign */ + log_len += elog_strcpy(log_len, log_buf + log_len, ELOG_NEWLINE_SIGN); + /* output log */ +#if defined(ELOG_ASYNC_OUTPUT_ENABLE) + extern void elog_async_output(uint8_t level, const char *log, size_t size); + elog_async_output(level, log_buf, log_len); +#elif defined(ELOG_BUF_OUTPUT_ENABLE) + extern void elog_buf_output(const char *log, size_t size); + elog_buf_output(log_buf, log_len); +#else + elog_port_output(log_buf, log_len); +#endif + /* unlock output */ + elog_output_unlock(); +} + +/** + * get format enabled + * + * @param level level + * @param set format set + * + * @return enable or disable + */ +static bool get_fmt_enabled(uint8_t level, size_t set) { + ELOG_ASSERT(level <= ELOG_LVL_VERBOSE); + + if (elog.enabled_fmt_set[level] & set) { + return true; + } else { + return false; + } +} + +static bool get_fmt_used_and_enabled_u32(uint8_t level, size_t set, uint32_t arg) { + return arg && get_fmt_enabled(level, set); +} +static bool get_fmt_used_and_enabled_ptr(uint8_t level, size_t set, const char* arg) { + return arg && get_fmt_enabled(level, set); +} + +/** + * enable or disable logger output lock + * @note disable this lock is not recommended except you want output system exception log + * + * @param enabled true: enable false: disable + */ +void elog_output_lock_enabled(bool enabled) { + elog.output_lock_enabled = enabled; + /* it will re-lock or re-unlock before output lock enable */ + if (elog.output_lock_enabled) { + if (!elog.output_is_locked_before_disable && elog.output_is_locked_before_enable) { + /* the output lock is unlocked before disable, and the lock will unlocking after enable */ + elog_port_output_lock(); + } else if (elog.output_is_locked_before_disable && !elog.output_is_locked_before_enable) { + /* the output lock is locked before disable, and the lock will locking after enable */ + elog_port_output_unlock(); + } + } +} + +/** + * Set a hook function to EasyLogger assert. It will run when the expression is false. + * + * @param hook the hook function + */ +void elog_assert_set_hook(void (*hook)(const char* expr, const char* func, size_t line)) { + elog_assert_hook = hook; +} + +/** + * find the log level + * @note make sure the log level is output on each format + * + * @param log log buffer + * + * @return log level, found failed will return -1 + */ +int8_t elog_find_lvl(const char *log) { + ELOG_ASSERT(log); + /* make sure the log level is output on each format */ + ELOG_ASSERT(elog.enabled_fmt_set[ELOG_LVL_ASSERT] & ELOG_FMT_LVL); + ELOG_ASSERT(elog.enabled_fmt_set[ELOG_LVL_ERROR] & ELOG_FMT_LVL); + ELOG_ASSERT(elog.enabled_fmt_set[ELOG_LVL_WARN] & ELOG_FMT_LVL); + ELOG_ASSERT(elog.enabled_fmt_set[ELOG_LVL_INFO] & ELOG_FMT_LVL); + ELOG_ASSERT(elog.enabled_fmt_set[ELOG_LVL_DEBUG] & ELOG_FMT_LVL); + ELOG_ASSERT(elog.enabled_fmt_set[ELOG_LVL_VERBOSE] & ELOG_FMT_LVL); + +#ifdef ELOG_COLOR_ENABLE + uint8_t i; + size_t csi_start_len = strlen(CSI_START); + for(i = 0; i < ELOG_LVL_TOTAL_NUM; i ++) { + if (!strncmp(color_output_info[i], log + csi_start_len, strlen(color_output_info[i]))) { + return i; + } + } + /* found failed */ + return -1; +#else + switch (log[0]) { + case 'A': return ELOG_LVL_ASSERT; + case 'E': return ELOG_LVL_ERROR; + case 'W': return ELOG_LVL_WARN; + case 'I': return ELOG_LVL_INFO; + case 'D': return ELOG_LVL_DEBUG; + case 'V': return ELOG_LVL_VERBOSE; + default: return -1; + } +#endif +} + +/** + * find the log tag + * @note make sure the log tag is output on each format + * @note the tag don't have space in it + * + * @param log log buffer + * @param lvl log level, you can get it by @see elog_find_lvl + * @param tag_len found tag length + * + * @return log tag, found failed will return NULL + */ +const char *elog_find_tag(const char *log, uint8_t lvl, size_t *tag_len) { + const char *tag = NULL, *tag_end = NULL; + + ELOG_ASSERT(log); + ELOG_ASSERT(tag_len); + ELOG_ASSERT(lvl < ELOG_LVL_TOTAL_NUM); + /* make sure the log tag is output on each format */ + ELOG_ASSERT(elog.enabled_fmt_set[lvl] & ELOG_FMT_TAG); + +#ifdef ELOG_COLOR_ENABLE + tag = log + strlen(CSI_START) + strlen(color_output_info[lvl]) + strlen(level_output_info[lvl]); +#else + tag = log + strlen(level_output_info[lvl]); +#endif + /* find the first space after tag */ + if ((tag_end = memchr(tag, ' ', ELOG_FILTER_TAG_MAX_LEN)) != NULL) { + *tag_len = tag_end - tag; + } else { + tag = NULL; + } + + return tag; +} + +/** + * dump the hex format data to log + * + * @param name name for hex object, it will show on log header + * @param width hex number for every line, such as: 16, 32 + * @param buf hex buffer + * @param size buffer size + */ +void elog_hexdump(const char *name, uint8_t width, const void *buf, uint16_t size) +{ +#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ') + + uint16_t i, j; + uint16_t log_len = 0; + const uint8_t *buf_p = buf; + char dump_string[8] = {0}; + int fmt_result; + + if (!elog.output_enabled) { + return; + } + + /* level filter */ + if (ELOG_LVL_DEBUG > elog.filter.level) { + return; + } else if (!strstr(name, elog.filter.tag)) { /* tag filter */ + return; + } + + /* lock output */ + elog_output_lock(); + + for (i = 0; i < size; i += width) { + /* package header */ + fmt_result = snprintf(log_buf, ELOG_LINE_BUF_SIZE, "D/HEX %s: %04X-%04X: ", name, i, i + width - 1); + /* calculate log length */ + if ((fmt_result > -1) && (fmt_result <= ELOG_LINE_BUF_SIZE)) { + log_len = fmt_result; + } else { + log_len = ELOG_LINE_BUF_SIZE; + } + /* dump hex */ + for (j = 0; j < width; j++) { + if (i + j < size) { + snprintf(dump_string, sizeof(dump_string), "%02X ", buf_p[i + j]); + } else { + strncpy(dump_string, " ", sizeof(dump_string)); + } + log_len += elog_strcpy(log_len, log_buf + log_len, dump_string); + if ((j + 1) % 8 == 0) { + log_len += elog_strcpy(log_len, log_buf + log_len, " "); + } + } + log_len += elog_strcpy(log_len, log_buf + log_len, " "); + /* dump char for hex */ + for (j = 0; j < width; j++) { + if (i + j < size) { + snprintf(dump_string, sizeof(dump_string), "%c", __is_print(buf_p[i + j]) ? buf_p[i + j] : '.'); + log_len += elog_strcpy(log_len, log_buf + log_len, dump_string); + } + } + /* overflow check and reserve some space for newline sign */ + if (log_len + strlen(ELOG_NEWLINE_SIGN) > ELOG_LINE_BUF_SIZE) { + log_len = ELOG_LINE_BUF_SIZE - strlen(ELOG_NEWLINE_SIGN); + } + /* package newline sign */ + log_len += elog_strcpy(log_len, log_buf + log_len, ELOG_NEWLINE_SIGN); + /* do log output */ +#if defined(ELOG_ASYNC_OUTPUT_ENABLE) + extern void elog_async_output(uint8_t level, const char *log, size_t size); + elog_async_output(ELOG_LVL_DEBUG, log_buf, log_len); +#elif defined(ELOG_BUF_OUTPUT_ENABLE) + extern void elog_buf_output(const char *log, size_t size); + elog_buf_output(log_buf, log_len); +#else + elog_port_output(log_buf, log_len); +#endif + } + /* unlock output */ + elog_output_unlock(); +} diff --git a/Core/Src/easylogger/src/elog_utils.c b/Core/Src/easylogger/src/elog_utils.c new file mode 100644 index 0000000..4aa9a19 --- /dev/null +++ b/Core/Src/easylogger/src/elog_utils.c @@ -0,0 +1,79 @@ +// +// Created by wangb on 25-6-4. +// + +#include "elog.h" +#include + +/** + * another copy string function + * + * @param cur_len current copied log length, max size is ELOG_LINE_BUF_SIZE + * @param dst destination + * @param src source + * + * @return copied length + */ +size_t elog_strcpy(size_t cur_len, char *dst, const char *src) { + const char *src_old = src; + + assert(dst); + assert(src); + + while (*src != 0) { + /* make sure destination has enough space */ + if (cur_len++ < ELOG_LINE_BUF_SIZE) { + *dst++ = *src++; + } else { + break; + } + } + return src - src_old; +} + +/** + * Copy line log split by newline sign. It will copy all log when the newline sign isn't find. + * + * @param line line log buffer + * @param log origin log buffer + * @param len origin log buffer length + * + * @return copy size + */ +size_t elog_cpyln(char *line, const char *log, size_t len) { + size_t newline_len = strlen(ELOG_NEWLINE_SIGN), copy_size = 0; + + assert(line); + assert(log); + + while (len--) { + *line++ = *log++; + copy_size++; + if (copy_size >= newline_len && !strncmp(log - newline_len, ELOG_NEWLINE_SIGN, newline_len)) { + break; + } + } + return copy_size; +} + +/** + * This function will copy memory content from source address to destination + * address. + * + * @param dst the address of destination memory + * @param src the address of source memory + * @param count the copied length + * + * @return the address of destination memory + */ +void *elog_memcpy(void *dst, const void *src, size_t count) { + char *tmp = (char *) dst, *s = (char *) src; + + assert(dst); + assert(src); + + while (count--) + *tmp++ = *s++; + + return dst; +} diff --git a/Core/Src/freertos.c b/Core/Src/freertos.c index 5203fd5..dcd6831 100644 --- a/Core/Src/freertos.c +++ b/Core/Src/freertos.c @@ -25,6 +25,16 @@ /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ +#include "usart.h" +#include "adc.h" +#include "tim.h" +#include "motor_driver.h" +#include "elog.h" +#include +#include +#include "screen.h" +#include +#include /* USER CODE END Includes */ @@ -40,12 +50,29 @@ /* Private macro -------------------------------------------------------------*/ /* USER CODE BEGIN PM */ +#ifdef __GNUC__ +#define PUTCHAR_PROTOTYPE int __io_putchar(int ch) +#else +#define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f) +#endif +PUTCHAR_PROTOTYPE { + HAL_UART_Transmit(&huart5, (uint8_t *) &ch, 1, HAL_MAX_DELAY); + return ch; +} /* USER CODE END PM */ /* Private variables ---------------------------------------------------------*/ /* USER CODE BEGIN Variables */ +/* 按键状态位: bit0..bit3 分别对应 M__KEY, M__KEYC7, HOT_KEY, TIME_KEY, 为1表示按下 */ +volatile uint8_t key_state = 0; +volatile uint8_t key_state_prev = 0; /* 上一次的按键状态，用于检测按键变化 */ + +/* 设备状态标志：0表示关闭，1表示打开 */ +static uint8_t hot_state = 0; /* HOT 设备状态 */ +static uint8_t time_state = 0; /* TIME_KEY 时间状态 */ + /* USER CODE END Variables */ /* Definitions for defaultTask */ osThreadId_t defaultTaskHandle; @@ -54,6 +81,41 @@ const osThreadAttr_t defaultTask_attributes = { .stack_size = 128 * 4, .priority = (osPriority_t) osPriorityNormal, }; +/* Definitions for KeyTask */ +osThreadId_t KeyTaskHandle; +const osThreadAttr_t KeyTask_attributes = { + .name = "KeyTask", + .stack_size = 512 * 4, + .priority = (osPriority_t) osPriorityRealtime, +}; +/* Definitions for Sensor_Task */ +osThreadId_t Sensor_TaskHandle; +const osThreadAttr_t Sensor_Task_attributes = { + .name = "Sensor_Task", + .stack_size = 512 * 4, + .priority = (osPriority_t) osPriorityHigh7, +}; +/* Definitions for Temp_Task */ +osThreadId_t Temp_TaskHandle; +const osThreadAttr_t Temp_Task_attributes = { + .name = "Temp_Task", + .stack_size = 256 * 4, + .priority = (osPriority_t) osPriorityNormal, +}; +/* Definitions for Motor_Task */ +osThreadId_t Motor_TaskHandle; +const osThreadAttr_t Motor_Task_attributes = { + .name = "Motor_Task", + .stack_size = 512 * 4, + .priority = (osPriority_t) osPriorityNormal1, +}; +/* Definitions for Screen_Tsak */ +osThreadId_t Screen_TsakHandle; +const osThreadAttr_t Screen_Tsak_attributes = { + .name = "Screen_Tsak", + .stack_size = 1024 * 4, + .priority = (osPriority_t) osPriorityNormal, +}; /* Private function prototypes -----------------------------------------------*/ /* USER CODE BEGIN FunctionPrototypes */ @@ -61,6 +123,11 @@ const osThreadAttr_t defaultTask_attributes = { /* USER CODE END FunctionPrototypes */ void StartDefaultTask(void *argument); +void Key(void *argument); +void Sensor(void *argument); +void Temp(void *argument); +void Motor(void *argument); +void Screen(void *argument); void MX_FREERTOS_Init(void); /* (MISRA C 2004 rule 8.1) */ @@ -71,7 +138,9 @@ void MX_FREERTOS_Init(void); /* (MISRA C 2004 rule 8.1) */ */ void MX_FREERTOS_Init(void) { /* USER CODE BEGIN Init */ - + easylogger_init(); /* 初始化 EasyLogger */ + __enable_irq(); //开启全局中断 + elog_i("task_init", "任务初始！"); /* USER CODE END Init */ /* USER CODE BEGIN RTOS_MUTEX */ @@ -94,6 +163,21 @@ void MX_FREERTOS_Init(void) { /* creation of defaultTask */ defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes); + /* creation of KeyTask */ + KeyTaskHandle = osThreadNew(Key, NULL, &KeyTask_attributes); + + /* creation of Sensor_Task */ + Sensor_TaskHandle = osThreadNew(Sensor, NULL, &Sensor_Task_attributes); + + /* creation of Temp_Task */ + Temp_TaskHandle = osThreadNew(Temp, NULL, &Temp_Task_attributes); + + /* creation of Motor_Task */ + Motor_TaskHandle = osThreadNew(Motor, NULL, &Motor_Task_attributes); + + /* creation of Screen_Tsak */ + Screen_TsakHandle = osThreadNew(Screen, NULL, &Screen_Tsak_attributes); + /* USER CODE BEGIN RTOS_THREADS */ /* add threads, ... */ /* USER CODE END RTOS_THREADS */ @@ -114,14 +198,312 @@ void MX_FREERTOS_Init(void) { void StartDefaultTask(void *argument) { /* USER CODE BEGIN StartDefaultTask */ + // 初始化命令 + uint8_t init_cmd1[] = {0x7E, 0xFF, 0x06, 0x06, 0x00, 0x00, 0x1E, 0xFE, 0xD7, 0xEF}; // 开启声音 + uint8_t init_cmd2[] = {0x7E, 0xFF, 0x06, 0x09, 0x00, 0x00, 0x02, 0xFE, 0xF0, 0xEF}; // 指定播放设备为TF卡 + + // 定义测试指令数据 + uint8_t test_cmd[] = {0x7E, 0xFF, 0x06, 0x12, 0x00, 0x00, 0x01, 0xFE, 0xE8, 0xEF}; + + // 先让模块稳定 + osDelay(2000); + + // 初始化：先发送开启声音指令，再发送指定播放设备指令 + HAL_UART_Transmit(&huart3, init_cmd1, sizeof(init_cmd1), 1000); + osDelay(1500); // 重要：等待模块响应 + + HAL_UART_Transmit(&huart3, init_cmd2, sizeof(init_cmd2), 1000); + osDelay(1500); // 重要：等待初始化完成 + /* Infinite loop */ for(;;) { - osDelay(1); + // 直接整包发送测试指令 + HAL_UART_Transmit(&huart3, test_cmd, sizeof(test_cmd), 1000); + // 把发送的数据打印出来 + //elog_d("mp3_cmd","发送测试指令: %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X", test_cmd[0], test_cmd[1], test_cmd[2], test_cmd[3], test_cmd[4], test_cmd[5], test_cmd[6], test_cmd[7], test_cmd[8], test_cmd[9]); + // 可选：等待发送完成 + // while(__HAL_UART_GET_FLAG(&huart3, UART_FLAG_TC) == RESET); + + HAL_GPIO_TogglePin(RUN_LED_GPIO_Port, RUN_LED_Pin); + + osDelay(1000); // 延时1秒 } /* USER CODE END StartDefaultTask */ } +/* USER CODE BEGIN Header_Key */ +/** +* @brief Function implementing the KeyTask thread. +* @param argument: Not used +* @retval None +*/ +/* USER CODE END Header_Key */ +void Key(void *argument) +{ + /* USER CODE BEGIN Key */ + /* 防抖轮询实现四个低电平有效按键检测 */ + GPIO_TypeDef* key_ports[4] = {M__KEY_GPIO_Port, M__KEYC7_GPIO_Port, HOT_KEY_GPIO_Port, TIME_KEY_GPIO_Port}; + const uint16_t key_pins[4] = {M__KEY_Pin, M__KEYC7_Pin, HOT_KEY_Pin, TIME_KEY_Pin}; + + uint8_t press_count[4] = {0}; + uint8_t release_count[4] = {0}; + uint8_t pressed[4] = {0}; + const uint8_t THRESH = 3; /* 3 * 10ms = 30ms 防抖 */ + + for(;;) + { + for (int i = 0; i < 4; i++) { + GPIO_PinState level = HAL_GPIO_ReadPin(key_ports[i], key_pins[i]); + if (level == GPIO_PIN_RESET) { /* 低电平有效 */ + press_count[i]++; + release_count[i] = 0; + if (!pressed[i] && press_count[i] >= THRESH) { + pressed[i] = 1; + key_state |= (1 << i); /* bit0..3 分别对应四个按键按下状态 */ + } + } else { + release_count[i]++; + press_count[i] = 0; + if (pressed[i] && release_count[i] >= THRESH) { + pressed[i] = 0; + key_state &= ~(1 << i); + } + } + } + osDelay(10); /* 10ms 轮询间隔 */ + } + /* USER CODE END Key */ +} + +/* USER CODE BEGIN Header_Sensor */ +/** +* @brief Function implementing the Sensor_Task thread. +* @param argument: Not used +* @retval None +*/ +/* USER CODE END Header_Sensor */ +void Sensor(void *argument) +{ + /* USER CODE BEGIN Sensor */ + /* 按键处理任务 - 按键状态切换控制 */ + + /* Infinite loop */ + for(;;) + { + /* 检测新按下的按键 */ + uint8_t key_pressed = key_state & ~key_state_prev; + key_state_prev = key_state; + + /* ===== M__KEY (bit0) 控制 ===== */ + if (key_pressed & (1 << 0)) { + /* M__KEY 按下：加档（提高转速） */ + elog_i("Key", "M__KEY按下 - 加档"); + if (Motor_GetGear() == 0) { + Motor_StartupBoost(); + } else { + Motor_GearUp(); + } + } + + /* ===== M__KEYC7 (bit1) 控制 ===== */ + if (key_pressed & (1 << 1)) { + /* M__KEYC7 按下：降档（降低转速） */ + elog_i("Key", "M__KEYC7按下 - 降档"); + Motor_GearDown(); + } + + /* ===== HOT_KEY (bit2) 控制 ===== */ + if (key_pressed & (1 << 2)) { + /* HOT_KEY 按下：切换热功能 */ + hot_state = !hot_state; + HAL_GPIO_WritePin(HOT_GPIO_Port, HOT_Pin, hot_state ? GPIO_PIN_SET : GPIO_PIN_RESET); + } + + /* ===== TIME_KEY (bit3) 控制 ===== */ + if (key_pressed & (1 << 3)) { + /* TIME_KEY 按下：切换定时 */ + time_state = !time_state; + if (time_state) { + // TODO: 添加定时启动逻辑 + } else { + // TODO: 添加定时关闭逻辑 + } + } + + osDelay(20); /* 20ms 检查一次按键状态 */ + } + /* USER CODE END Sensor */ +} + +/* USER CODE BEGIN Header_Temp */ +/** +* @brief Function implementing the Temp_Task thread. +* @param argument: Not used +* @retval None +*/ +/* USER CODE END Header_Temp */ +void Temp(void *argument) +{ + /* USER CODE BEGIN Temp */ + +#ifdef ENABLE_TEMP_SENSOR + + /* ADC采集参数 */ + uint32_t adc_raw = 0; /* ADC原始值 */ + uint32_t adc_sum = 0; /* 累加和（用于平均） */ + uint16_t sample_count = 32; /* 采样次数 */ + float voltage = 0.0f; /* 转换后的电压 */ + float temperature = 0.0f; /* 转换后的温度 */ + + /* 电路参数 */ + const float VREF = 3.3f; /* 参考电压 */ + + /* 一阶低通滤波器 */ + float adc_filtered = 0.0f; /* 滤波后的ADC值 */ + const float FILTER_ALPHA = 0.1f; /* 滤波系数 */ + + /* NTC 10K 3950参数 */ + const float NTC_B_VALUE = 3950.0f; /* NTC B值 */ + const float NTC_R0 = 10000.0f; /* 25°C时电阻10K */ + const float NTC_T0 = 298.15f; /* 25°C对应的绝对温度(K) */ + const float R_FIXED = 10000.0f; /* 分压电阻10K */ + + /* ADC校准 */ + HAL_ADCEx_Calibration_Start(&hadc1); + + /* 预热：先采集几次丢弃，稳定ADC */ + for (uint16_t i = 0; i < 10; i++) { + HAL_ADC_Start(&hadc1); + HAL_ADC_PollForConversion(&hadc1, 100); + HAL_ADC_GetValue(&hadc1); + HAL_ADC_Stop(&hadc1); + osDelay(10); + } + + /* Infinite loop */ + for(;;) + { + /* 采集多次求平均，提高精度 */ + adc_sum = 0; + for (uint16_t i = 0; i < sample_count; i++) { + HAL_ADC_Start(&hadc1); + if (HAL_ADC_PollForConversion(&hadc1, 100) == HAL_OK) { + adc_sum += HAL_ADC_GetValue(&hadc1); + } + HAL_ADC_Stop(&hadc1); + osDelay(20); + } + + /* 计算平均值 */ + adc_raw = adc_sum / sample_count; + + /* 一阶低通滤波 */ + if (adc_filtered == 0.0f) { + adc_filtered = (float)adc_raw; + } else { + adc_filtered = FILTER_ALPHA * (float)adc_raw + (1.0f - FILTER_ALPHA) * adc_filtered; + } + adc_raw = (uint32_t)(adc_filtered + 0.5f); + + /* 转换为电压 */ + voltage = ((float)adc_raw / 4095.0f) * VREF; + + /* ==================== NTC 10K 3950 温度计算 ==================== + * 电路：3.3V ──[10K固定电阻]──┬── PA0 (ADC) + * │ + * [NTC 10K] + * │ + * GND + * + * Steinhart-Hart简化方程： + * 1/T = 1/T0 + (1/B) * ln(R/R0) + */ + { + /* 计算NTC电阻值 */ + float ntc_resistance = R_FIXED * voltage / (VREF - voltage); + + /* Steinhart-Hart方程计算温度(K) */ + float steinhart = logf(ntc_resistance / NTC_R0) / NTC_B_VALUE + 1.0f / NTC_T0; + temperature = 1.0f / steinhart - 273.15f; /* 转换为摄氏度 */ + + elog_i("Temp", "ADC:%lu 电压:%.3fV NTC:%.1fΩ 温度:%.1f°C", + adc_raw, voltage, ntc_resistance, temperature); + } + + osDelay(1000); + } + +#else + /* 温度传感器未启用，任务空转 */ + elog_i("Temp", "温度传感器未启用，等待NTC改装..."); + + for(;;) + { + osDelay(5000); + elog_i("Temp", "温度传感器未启用，等待NTC改装..."); + } + +#endif /* ENABLE_TEMP_SENSOR */ + + /* USER CODE END Temp */ +} + +/* USER CODE BEGIN Header_Motor */ +/** +* @brief Function implementing the Motor_Task thread. +* @param argument: Not used +* @retval None +*/ +/* USER CODE END Header_Motor */ +void Motor(void *argument) +{ + /* USER CODE BEGIN Motor */ + + /* 电机驱动初始化 */ + Motor_Init(); + + /* Infinite loop */ + for(;;) + { + /* 电机任务主要功能： + * - 监控电机状态（超温保护、过流保护等） + * - 定期打印状态信息 + * - 响应紧急停止信号 + */ + + /* 每1秒打印一次电机状态 */ + uint8_t current_gear = Motor_GetGear(); + elog_i("Motor", "当前档位: %u (0=停止,1=低,2=中,3=高)", current_gear); + + osDelay(1000); + } + /* USER CODE END Motor */ +} + +/* USER CODE BEGIN Header_Screen */ +/** +* @brief Function implementing the Screen_Tsak thread. +* @param argument: Not used +* @retval None +*/ +/* USER CODE END Header_Screen */ +void Screen(void *argument) +{ + /* USER CODE BEGIN Screen */ + char buf[100]; + sprintf(buf, "CLR(1);\r\n"); + //HAL_UART_Transmit(&huart1, (uint8_t *)buf, strlen(buf), HAL_MAX_DELAY); + /* Infinite loop */ + for(;;) + { + HAL_UART_Transmit(&huart1, (uint8_t *)buf, strlen(buf), HAL_MAX_DELAY); + + osDelay(2000); + } + /* USER CODE END Screen */ +} + /* Private application code --------------------------------------------------*/ /* USER CODE BEGIN Application */ diff --git a/Core/Src/gpio.c b/Core/Src/gpio.c index b7cf305..f296918 100644 --- a/Core/Src/gpio.c +++ b/Core/Src/gpio.c @@ -50,9 +50,19 @@ void MX_GPIO_Init(void) __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE(); + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(HOT_GPIO_Port, HOT_Pin, GPIO_PIN_RESET); + /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, RUN_LED_Pin|ERR_LED_Pin, GPIO_PIN_RESET); + /*Configure GPIO pin : HOT_Pin */ + GPIO_InitStruct.Pin = HOT_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_PULLDOWN; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(HOT_GPIO_Port, &GPIO_InitStruct); + /*Configure GPIO pins : RUN_LED_Pin ERR_LED_Pin */ GPIO_InitStruct.Pin = RUN_LED_Pin|ERR_LED_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; @@ -63,7 +73,7 @@ void MX_GPIO_Init(void) /*Configure GPIO pins : M__KEY_Pin M__KEYC7_Pin HOT_KEY_Pin TIME_KEY_Pin */ GPIO_InitStruct.Pin = M__KEY_Pin|M__KEYC7_Pin|HOT_KEY_Pin|TIME_KEY_Pin; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Pull = GPIO_PULLUP; HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); } diff --git a/Core/Src/motor_driver.c b/Core/Src/motor_driver.c new file mode 100644 index 0000000..0fae06f --- /dev/null +++ b/Core/Src/motor_driver.c @@ -0,0 +1,128 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file motor_driver.c + * @brief 电机驱动实现 - 双路AT8236-MS H桥驱动 + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "motor_driver.h" +#include "elog.h" +#include "stm32f1xx_hal.h" +#include "stm32f1xx_hal_tim.h" +#include "cmsis_os.h" +#include "tim.h" + +/* Private defines -----------------------------------------------------------*/ +/* TIM4自动重装载值是99 (100-1)，所以PWM值范围是0-99 */ + + +/* Private function prototypes -----------------------------------------------*/ + +/* PWM parameters */ +#define PWM_ARR 99 +#define PWM_STEPS (PWM_ARR + 1) + +/* 三档占空比（百分比），索引为 0..2 对应 档位 1..3（档位0为停止） */ +static const uint8_t gears_percent[3] = {75, 80, 85}; +/* current_gear: 0 = 停止, 1 = 低, 2 = 中, 3 = 高 */ +static uint8_t current_gear = 0; /* 0..3 */ + +static inline uint32_t percent_to_compare(uint8_t percent) { + return ((uint32_t)percent * PWM_STEPS) / 100U; +} + +/* 将两个电机都设置为指定占空比（只使用 TIM4_CH2, TIM4_CH4 输出，CH1/CH3 停止以保持单方向） */ +static void set_both_motors_percent(uint8_t percent) { + uint32_t cmp = percent_to_compare(percent); + + /* 停止并关闭 CH1、使用 CH2 输出 */ + HAL_TIM_PWM_Stop(&htim4, TIM_CHANNEL_1); + __HAL_TIM_SET_COMPARE(&htim4, TIM_CHANNEL_2, (uint16_t)cmp); + + /* 停止并关闭 CH3、使用 CH4 输出 */ + HAL_TIM_PWM_Stop(&htim4, TIM_CHANNEL_3); + __HAL_TIM_SET_COMPARE(&htim4, TIM_CHANNEL_4, (uint16_t)cmp); +} + +/* 启动时短暂提升到 90% 并保持 500ms，然后降到一档（档位1） */ +void Motor_StartupBoost(void) { + set_both_motors_percent(90); + osDelay(1500); + current_gear = 1; /* 启动后回到档位1（最低速） */ + set_both_motors_percent(gears_percent[current_gear - 1]); +} + +/* 设置挡位（0..3），0=停止 */ +void Motor_SetGear(uint8_t gear) { + if (gear > 3) gear = 3; + current_gear = gear; + if (current_gear == 0) { + set_both_motors_percent(0); + } else { + set_both_motors_percent(gears_percent[current_gear - 1]); + } +} + +/* 切换到下一档（0->1->2->3->0 循环） */ +void Motor_NextGear(void) { + current_gear++; + if (current_gear > 3) current_gear = 0; + if (current_gear == 0) { + set_both_motors_percent(0); + } else { + set_both_motors_percent(gears_percent[current_gear - 1]); + } +} + +/* 向上加档（与按键配合使用） */ +void Motor_GearUp(void) { + Motor_NextGear(); +} + +/* 向下减档（循环） */ +void Motor_GearDown(void) { + if (current_gear == 0) { + current_gear = 3; + } else { + current_gear--; + } + if (current_gear == 0) { + set_both_motors_percent(0); + } else { + set_both_motors_percent(gears_percent[current_gear - 1]); + } +} + +uint8_t Motor_GetGear(void) { + return current_gear; +} + + +/* Exported functions --------------------------------------------------------*/ + +/** + * @brief 电机驱动初始化 + */ +void Motor_Init(void) { + /* 启动TIM4 PWM输出 */ + HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_1); + HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_2); + HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_3); + HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_4); + + // 初始完全停止电机 + Motor_Stop(); + + +} + +void Motor_Stop(void) { + // 所有引脚输出0 - 完全停止 + __HAL_TIM_SET_COMPARE(&htim4, TIM_CHANNEL_1, 0); + __HAL_TIM_SET_COMPARE(&htim4, TIM_CHANNEL_2, 0); + __HAL_TIM_SET_COMPARE(&htim4, TIM_CHANNEL_3, 0); + __HAL_TIM_SET_COMPARE(&htim4, TIM_CHANNEL_4, 0); +} diff --git a/Core/Src/motor_driver.h b/Core/Src/motor_driver.h new file mode 100644 index 0000000..085de49 --- /dev/null +++ b/Core/Src/motor_driver.h @@ -0,0 +1,40 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file motor_driver.h + * @brief 电机驱动头文件 - 双路AT8236-MS H桥驱动 + ****************************************************************************** + * @attention + * + * AT8236-MS 双路H桥电机驱动芯片 + * - 芯片1: TIM4_CH1 -> AIN1, TIM4_CH2 -> AIN2 + * - 芯片2: TIM4_CH3 -> BIN1, TIM4_CH4 -> BIN2 + * - 两路电机同步控制：同时启动、同时停止 + ****************************************************************************** + */ +/* USER CODE END Header */ + +#ifndef __MOTOR_DRIVER_H__ +#define __MOTOR_DRIVER_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +void Motor_Init(void); +void Motor_Stop(void) ; +void Motor_StartupBoost(void); +void Motor_SetGear(uint8_t gear); +void Motor_NextGear(void); +void Motor_GearUp(void); +void Motor_GearDown(void); +uint8_t Motor_GetGear(void); +#ifdef __cplusplus + +} +#endif + +#endif /* __MOTOR_DRIVER_H__ */ diff --git a/Core/Src/screen.c b/Core/Src/screen.c new file mode 100644 index 0000000..e8fca4a --- /dev/null +++ b/Core/Src/screen.c @@ -0,0 +1,189 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file screen.c + * @brief 串口屏驱动实现（JC系列），使用 USART1 + ****************************************************************************** + */ +/* USER CODE END Header */ + +#include "screen.h" +#include "main.h" +#include "usart.h" +#include "cmsis_os.h" +#include +#include + +/* 模块初始化：不要使用 MP3 的二进制初始化指令，改为屏幕清屏作为默认初始化 */ + +/* 发送缓冲 */ +static char txbuf[256]; + + +/** + * @brief 发送字符串到串口屏（阻塞直到发送完成） + * @param cmd: 要发送的C字符串（不强制包含结尾CR/LF） + * @retval 0=OK, <0=错误 + */ +int Screen_SendCmd(const char *cmd) { + if (cmd == NULL) return -1; + size_t len = strlen(cmd); + if (len == 0) return -1; + HAL_StatusTypeDef st = HAL_UART_Transmit(&huart1, (uint8_t *)cmd, (uint16_t)len, HAL_MAX_DELAY); + return (st == HAL_OK) ? 0 : -2; +} + +/** + * @brief 发送命令并等待模块返回 "OK\r\n"，超时返回非0 + */ +int Screen_SendCmdWaitOK(const char *cmd, uint32_t timeout_ms) { + (void)timeout_ms; + /* 保留接口：当前不等待屏幕回包，直接发送后返回发送状态 */ + return Screen_SendCmd(cmd); +} + +void Screen_Init(void) { + /* + * 屏幕初始化：简单实现为上电等待并清除屏幕 + * 若需要按照厂商例程发送更多配置指令，可在此扩展 + */ + osDelay(1000); + Screen_Clear(0); + osDelay(200); +} + +/* 简单封装接口示例 */ +void Screen_Clear(uint8_t layer) { + sprintf(txbuf, "DIR(1);CLR(%u);\r\n", (unsigned)layer); + Screen_SendCmd(txbuf); +} + +void Screen_DisplayImage(uint32_t addr) { + sprintf(txbuf, "DIR(1);FSIMG(%lu,0,0,128,128,0);\r\n", (unsigned long)addr); + Screen_SendCmd(txbuf); +} + +void Screen_SetBrightness(uint8_t val) { + sprintf(txbuf, "BL(%u);\r\n", (unsigned)val); + Screen_SendCmd(txbuf); +} + +void Screen_DrawText16(uint16_t x, uint16_t y, const char *text, uint8_t color) { + sprintf(txbuf, "SBC(%u);DC16(%u,%u,'%s',%u);\r\n", (unsigned)color, (unsigned)x, (unsigned)y, text, (unsigned)color); + Screen_SendCmd(txbuf); +} + +/* 额外封装实现 */ +/* 以下为屏幕命令封装函数实现，均以字符串形式发送到串口屏 */ +/* 函数内部不等待屏幕回包，调用者若需确认执行结果请自行实现回包处理 */ + +void Screen_SetRotation(uint8_t dir) { + sprintf(txbuf, "DIR(%u);\r\n", dir); + Screen_SendCmd(txbuf); +} + +void Screen_SetBaud(uint32_t baud) { + sprintf(txbuf, "BPS(%lu);\r\n", (unsigned long)baud); + Screen_SendCmd(txbuf); +} +void Screen_DisplayImageAtAddr(uint32_t addr, uint16_t x, uint16_t y, uint16_t w, uint16_t h, uint8_t mode) { + sprintf(txbuf, "FSIMG(%lu,%u,%u,%u,%u,%u);\r\n", (unsigned long)addr, (unsigned)x, (unsigned)y, (unsigned)w, (unsigned)h, (unsigned)mode); + Screen_SendCmd(txbuf); +} + +void Screen_DisplayImageByIndex(uint32_t index, uint16_t x, uint16_t y, uint16_t w, uint16_t h, uint8_t mode) { + sprintf(txbuf, "FSIMG(%u,%u,%u,%u,%u,%u);\r\n", (unsigned)index, (unsigned)x, (unsigned)y, (unsigned)w, (unsigned)h, (unsigned)mode); + Screen_SendCmd(txbuf); +} + +void Screen_Pixel(uint16_t x, uint16_t y, uint8_t color) { + sprintf(txbuf, "PS(%u,%u,%u);\r\n", (unsigned)x, (unsigned)y, (unsigned)color); + Screen_SendCmd(txbuf); +} + +void Screen_Line(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint8_t color) { + sprintf(txbuf, "PL(%u,%u,%u,%u,%u);\r\n", (unsigned)x1, (unsigned)y1, (unsigned)x2, (unsigned)y2, (unsigned)color); + Screen_SendCmd(txbuf); +} + +void Screen_Box(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint8_t color) { + sprintf(txbuf, "BOX(%u,%u,%u,%u,%u);\r\n", (unsigned)x1, (unsigned)y1, (unsigned)x2, (unsigned)y2, (unsigned)color); + Screen_SendCmd(txbuf); +} + +void Screen_BoxFill(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint8_t color) { + sprintf(txbuf, "BOXF(%u,%u,%u,%u,%u);\r\n", (unsigned)x1, (unsigned)y1, (unsigned)x2, (unsigned)y2, (unsigned)color); + Screen_SendCmd(txbuf); +} + +void Screen_Circle(uint16_t x, uint16_t y, uint16_t r, uint8_t color) { + sprintf(txbuf, "CIR(%u,%u,%u,%u);\r\n", (unsigned)x, (unsigned)y, (unsigned)r, (unsigned)color); + Screen_SendCmd(txbuf); +} + +void Screen_CircleFill(uint16_t x, uint16_t y, uint16_t r, uint8_t color) { + sprintf(txbuf, "CIRF(%u,%u,%u,%u);\r\n", (unsigned)x, (unsigned)y, (unsigned)r, (unsigned)color); + Screen_SendCmd(txbuf); +} + +void Screen_SetBGColor(uint8_t color) { + sprintf(txbuf, "SBC(%u);\r\n", (unsigned)color); + Screen_SendCmd(txbuf); +} + +void Screen_DrawText16V(uint16_t x, uint16_t y, const char *text, uint8_t color) { + sprintf(txbuf, "DCV16(%u,%u,'%s',%u);\r\n", (unsigned)x, (unsigned)y, text, (unsigned)color); + Screen_SendCmd(txbuf); +} + +void Screen_DrawText24(uint16_t x, uint16_t y, const char *text, uint8_t color) { + sprintf(txbuf, "DC24(%u,%u,'%s',%u);\r\n", (unsigned)x, (unsigned)y, text, (unsigned)color); + Screen_SendCmd(txbuf); +} + +void Screen_DrawText24V(uint16_t x, uint16_t y, const char *text, uint8_t color) { + sprintf(txbuf, "DCV24(%u,%u,'%s',%u);\r\n", (unsigned)x, (unsigned)y, text, (unsigned)color); + Screen_SendCmd(txbuf); +} + +void Screen_DrawText32(uint16_t x, uint16_t y, const char *text, uint8_t color) { + sprintf(txbuf, "DC32(%u,%u,'%s',%u);\r\n", (unsigned)x, (unsigned)y, text, (unsigned)color); + Screen_SendCmd(txbuf); +} + +void Screen_DrawText32V(uint16_t x, uint16_t y, const char *text, uint8_t color) { + sprintf(txbuf, "DCV32(%u,%u,'%s',%u);\r\n", (unsigned)x, (unsigned)y, text, (unsigned)color); + Screen_SendCmd(txbuf); +} + +void Screen_DrawText48(uint16_t x, uint16_t y, const char *text, uint8_t color, uint8_t transparent) { + sprintf(txbuf, "DC48(%u,%u,'%s',%u,%u);\r\n", (unsigned)x, (unsigned)y, text, (unsigned)color, (unsigned)transparent); + Screen_SendCmd(txbuf); +} + +void Screen_Button(uint16_t x, uint16_t y, uint16_t w, uint16_t h, const char *label, uint8_t fontColor, uint8_t bgColor, uint8_t pressFlag, uint8_t style) { + sprintf(txbuf, "BTN(%u,%u,%u,%u,'%s',%u,%u,%u,%u);\r\n", (unsigned)x, (unsigned)y, (unsigned)w, (unsigned)h, label, (unsigned)fontColor, (unsigned)bgColor, (unsigned)pressFlag, (unsigned)style); + Screen_SendCmd(txbuf); +} + +void Screen_QRCode(uint16_t x, uint16_t y, const char *url) { + sprintf(txbuf, "QRCODE(%u,%u,%s);\r\n", (unsigned)x, (unsigned)y, url); + Screen_SendCmd(txbuf); +} + +void Screen_QRCodeEx(uint16_t x, uint16_t y, const char *url, uint16_t size, uint8_t color) { + sprintf(txbuf, "QRCODE(%u,%u,%s,%u,%u);\r\n", (unsigned)x, (unsigned)y, url, (unsigned)size, (unsigned)color); + Screen_SendCmd(txbuf); +} + +void Screen_Ver(void) { + sprintf(txbuf, "VER();\r\n"); + Screen_SendCmd(txbuf); +} + +/* USER CODE BEGIN AdditionalFunctions */ +/* 可以在这里扩展更多绘图/控件函数供应用层调用 */ + +/* USER CODE END AdditionalFunctions */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Src/tim.c b/Core/Src/tim.c index 2236c81..3fb5301 100644 --- a/Core/Src/tim.c +++ b/Core/Src/tim.c @@ -34,6 +34,7 @@ void MX_TIM4_Init(void) /* USER CODE END TIM4_Init 0 */ + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; TIM_MasterConfigTypeDef sMasterConfig = {0}; TIM_OC_InitTypeDef sConfigOC = {0}; @@ -41,11 +42,20 @@ void MX_TIM4_Init(void) /* USER CODE END TIM4_Init 1 */ htim4.Instance = TIM4; - htim4.Init.Prescaler = 0; + htim4.Init.Prescaler = 71; htim4.Init.CounterMode = TIM_COUNTERMODE_UP; - htim4.Init.Period = 65535; + htim4.Init.Period = 99; htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; - htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; + if (HAL_TIM_Base_Init(&htim4) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) { Error_Handler(); @@ -83,10 +93,10 @@ void MX_TIM4_Init(void) } -void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* tim_pwmHandle) +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) { - if(tim_pwmHandle->Instance==TIM4) + if(tim_baseHandle->Instance==TIM4) { /* USER CODE BEGIN TIM4_MspInit 0 */ @@ -117,7 +127,7 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); /* USER CODE BEGIN TIM4_MspPostInit 1 */ @@ -127,10 +137,10 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) } -void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef* tim_pwmHandle) +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle) { - if(tim_pwmHandle->Instance==TIM4) + if(tim_baseHandle->Instance==TIM4) { /* USER CODE BEGIN TIM4_MspDeInit 0 */ diff --git a/README.md b/README.md new file mode 100644 index 0000000..1b57d40 --- /dev/null +++ b/README.md @@ -0,0 +1,27 @@ +CLR(1); //使用红色填充整个屏幕,1为红色的色表编号 +DIR(1); //屏幕旋转方向: 0 竖向显示 1 旋转90°显示 2 竖向旋转180° 3 横向旋转180° +BPS(115200); //修改波特率为115200,掉电后自动保存设置,但注意波特率在修改过程中不允许掉电，建议只脱机修改一次 +BPS(38400); //支持波特率2 +BPS(19200); //支持的波特率3 +BPS(9600); //支持的波特率4 +FSIMG(2097152,0,0,176,220,0); //在MODE_CFG(0)/MODE_CFG(1)下,从(0,0)开始的位置显示第1张图片,图片的宽度是176 高度是220，最后的参数0表示正常显示。此为地址模式下显示图片指令 +FSIMG(0,0,0,176,220,0); //在MODE_CFG(2)下,从(0,0)开始的位置显示第1张图片,图片的宽度是176 高度是220，最后的参数0表示正常显示。此为编号模式下显示图片指令 +BL(20); //调整背光的亮度到20 范围：0为最亮 255为最暗 +PS(20,20,1); //在屏幕的(20,20) 位置用红色描绘一个点,1为红色的色表编号 +PL(0,0,90,90,1); //将屏幕的(0,0) 位置的点和(90,90)位置的点用红色的直线连起来 ,1为红色的色表编号 +BOX(20,20,40,40,1); //对角线(20,20)和(40,40)画线框 ,1为红色的色表编号 +BOXF(20,20,40,40,1); //对角线(20,20)和(40,40)画填充框 ,1为红色的色表编号 +CIR(60,60,3,1); //(60,60)为圆心 3为半径用红色画一个线圆 ,1为红色的色表编号 +CIRF(60,60,3,1); //(60,60)为圆心 3为半径用红色画一个填充圆, ,1为红色的色表编号 +SBC(1); //设置背景色为红色,此命令配合DCV和DC48指令一起使用 ,1为红色的色表编号 +DC16(30,30,'串口模块',1); // 用红色以(30,30)为起点,在屏幕上显示透明的'串口模块'这四个字,字体大小为16,1为红色的色表编号 +DCV16(30,30,'串口模块',1); //用红色以(30,30)为起点,在屏幕显示带背景色的'串口模块'这四个字,字体大小为16,1为红色的色表编号 +DC24(30,30,'串口模块',1); // 用红色以(30,30)为起点,在屏幕上显示透明的'串口模块'这四个字，字体大小为24,1为红色的色表编号 +DCV24(30,30,'串口模块',1); //用红色以(30,30)为起点,在屏幕显示带背景色的'串口模块'这四个字，字体大小为24,1为红色的色表编号 +DC32(30,30,'串口模块',1); //用红色以(30,30)为起点,在屏幕上显示透明的'串口模块'这四个字，字体大小为32,1为红色的色表编号 +DCV32(30,30,'串口模块',1); //用红色以(30,30)为起点,在屏幕显示带背景色的'串口模块'这四个字，字体大小为32,1为红色的色表编号 +DC48(30,46,'串口模块',1,0); //用红色以(30,46)为起点,在屏幕上显示透明的'串口模块'四个字，字体大小为48,1为红色的色表编号 参数0表示透明显示 +BTN(80,80,32,16,'按钮',1,0,1,4); //在(80,80)的位置显示一个下压的按钮，按钮字体为红色,背景为黄色 +QRCODE(10,10,www.sun-lcm.com); //在(10,10)的位置显示一个二维码，扫码后指向一个网页链接 注意目前只有MF022支持此指令 +QRCODE(10,10,www.sun-lcm.com,100,1); //在(10,10)的位置 显示限定大小为100（模块内部根据版本大小会自适应）颜色值为1（红色）的一个二维码，扫码后指向一个网页链接 注意目前只有MF219支持此指令 +VER(); //获取模块的固件版本信息 \ No newline at end of file diff --git a/anmo.ioc b/anmo.ioc index 7bceadd..b07e16e 100644 --- a/anmo.ioc +++ b/anmo.ioc @@ -1,17 +1,20 @@ #MicroXplorer Configuration settings - do not modify ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_0 -ADC1.IPParameters=Rank-0\#ChannelRegularConversion,master,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag +ADC1.ContinuousConvMode=ENABLE +ADC1.IPParameters=Rank-0\#ChannelRegularConversion,master,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag,ContinuousConvMode ADC1.NbrOfConversionFlag=1 ADC1.Rank-0\#ChannelRegularConversion=1 -ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5 +ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_239CYCLES_5 ADC1.master=1 CAD.formats= CAD.pinconfig= CAD.provider= -FREERTOS.IPParameters=Tasks01 -FREERTOS.Tasks01=defaultTask,24,128,StartDefaultTask,Default,NULL,Dynamic,NULL,NULL +FREERTOS.FootprintOK=false +FREERTOS.IPParameters=Tasks01,FootprintOK,configTOTAL_HEAP_SIZE +FREERTOS.Tasks01=defaultTask,24,128,StartDefaultTask,Default,NULL,Dynamic,NULL,NULL;KeyTask,48,512,Key,Default,NULL,Dynamic,NULL,NULL;Sensor_Task,47,512,Sensor,Default,NULL,Dynamic,NULL,NULL;Temp_Task,24,256,Temp,Default,NULL,Dynamic,NULL,NULL;Motor_Task,25,512,Motor,Default,NULL,Dynamic,NULL,NULL;Screen_Tsak,24,1024,Screen,Default,NULL,Dynamic,NULL,NULL +FREERTOS.configTOTAL_HEAP_SIZE=15000 File.Version=6 -GPIO.groupedBy= +GPIO.groupedBy=Group By Peripherals KeepUserPlacement=false Mcu.CPN=STM32F103RCT6 Mcu.Family=STM32F1 @@ -29,28 +32,30 @@ Mcu.Name=STM32F103R(C-D-E)Tx Mcu.Package=LQFP64 Mcu.Pin0=PD0-OSC_IN Mcu.Pin1=PD1-OSC_OUT -Mcu.Pin10=PC9 -Mcu.Pin11=PA9 -Mcu.Pin12=PA10 -Mcu.Pin13=PA13 -Mcu.Pin14=PA14 -Mcu.Pin15=PC12 -Mcu.Pin16=PD2 -Mcu.Pin17=PB6 -Mcu.Pin18=PB7 -Mcu.Pin19=PB8 +Mcu.Pin10=PC8 +Mcu.Pin11=PC9 +Mcu.Pin12=PA9 +Mcu.Pin13=PA10 +Mcu.Pin14=PA13 +Mcu.Pin15=PA14 +Mcu.Pin16=PC12 +Mcu.Pin17=PD2 +Mcu.Pin18=PB6 +Mcu.Pin19=PB7 Mcu.Pin2=PA0-WKUP -Mcu.Pin20=PB9 -Mcu.Pin21=VP_FREERTOS_VS_CMSIS_V2 -Mcu.Pin22=VP_SYS_VS_tim8 -Mcu.Pin3=PB10 -Mcu.Pin4=PB11 -Mcu.Pin5=PB12 -Mcu.Pin6=PB13 -Mcu.Pin7=PC6 -Mcu.Pin8=PC7 -Mcu.Pin9=PC8 -Mcu.PinsNb=23 +Mcu.Pin20=PB8 +Mcu.Pin21=PB9 +Mcu.Pin22=VP_FREERTOS_VS_CMSIS_V2 +Mcu.Pin23=VP_SYS_VS_tim8 +Mcu.Pin24=VP_TIM4_VS_ClockSourceINT +Mcu.Pin3=PA1 +Mcu.Pin4=PB10 +Mcu.Pin5=PB11 +Mcu.Pin6=PB12 +Mcu.Pin7=PB13 +Mcu.Pin8=PC6 +Mcu.Pin9=PC7 +Mcu.PinsNb=25 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32F103RCTx @@ -74,6 +79,12 @@ NVIC.TimeBase=TIM8_UP_IRQn NVIC.TimeBaseIP=TIM8 NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false PA0-WKUP.Signal=ADCx_IN0 +PA1.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultOutputPP +PA1.GPIO_Label=HOT +PA1.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_PP +PA1.GPIO_PuPd=GPIO_PULLDOWN +PA1.Locked=true +PA1.Signal=GPIO_Output PA10.Locked=true PA10.Mode=Asynchronous PA10.Signal=USART1_RX @@ -96,26 +107,38 @@ PB13.GPIOParameters=GPIO_Label PB13.GPIO_Label=ERR_LED PB13.Locked=true PB13.Signal=GPIO_Output +PB6.GPIOParameters=GPIO_Speed +PB6.GPIO_Speed=GPIO_SPEED_FREQ_HIGH PB6.Signal=S_TIM4_CH1 +PB7.GPIOParameters=GPIO_Speed +PB7.GPIO_Speed=GPIO_SPEED_FREQ_HIGH PB7.Signal=S_TIM4_CH2 +PB8.GPIOParameters=GPIO_Speed +PB8.GPIO_Speed=GPIO_SPEED_FREQ_HIGH PB8.Signal=S_TIM4_CH3 +PB9.GPIOParameters=GPIO_Speed +PB9.GPIO_Speed=GPIO_SPEED_FREQ_HIGH PB9.Signal=S_TIM4_CH4 PC12.Mode=Asynchronous PC12.Signal=UART5_TX -PC6.GPIOParameters=GPIO_Label +PC6.GPIOParameters=GPIO_PuPd,GPIO_Label PC6.GPIO_Label=M+_KEY +PC6.GPIO_PuPd=GPIO_PULLUP PC6.Locked=true PC6.Signal=GPIO_Input -PC7.GPIOParameters=GPIO_Label +PC7.GPIOParameters=GPIO_PuPd,GPIO_Label PC7.GPIO_Label=M-_KEY +PC7.GPIO_PuPd=GPIO_PULLUP PC7.Locked=true PC7.Signal=GPIO_Input -PC8.GPIOParameters=GPIO_Label +PC8.GPIOParameters=GPIO_PuPd,GPIO_Label PC8.GPIO_Label=HOT_KEY +PC8.GPIO_PuPd=GPIO_PULLUP PC8.Locked=true PC8.Signal=GPIO_Input -PC9.GPIOParameters=GPIO_Label +PC9.GPIOParameters=GPIO_PuPd,GPIO_Label PC9.GPIO_Label=TIME_KEY +PC9.GPIO_PuPd=GPIO_PULLUP PC9.Locked=true PC9.Signal=GPIO_Input PCC.Checker=false @@ -201,11 +224,14 @@ SH.S_TIM4_CH3.0=TIM4_CH3,PWM Generation3 CH3 SH.S_TIM4_CH3.ConfNb=1 SH.S_TIM4_CH4.0=TIM4_CH4,PWM Generation4 CH4 SH.S_TIM4_CH4.ConfNb=1 +TIM4.AutoReloadPreload=TIM_AUTORELOAD_PRELOAD_ENABLE TIM4.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1 TIM4.Channel-PWM\ Generation2\ CH2=TIM_CHANNEL_2 TIM4.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3 TIM4.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4 -TIM4.IPParameters=Channel-PWM Generation1 CH1,Channel-PWM Generation2 CH2,Channel-PWM Generation3 CH3,Channel-PWM Generation4 CH4 +TIM4.IPParameters=Channel-PWM Generation2 CH2,Channel-PWM Generation4 CH4,Prescaler,Period,AutoReloadPreload,Channel-PWM Generation1 CH1,Channel-PWM Generation3 CH3 +TIM4.Period=99 +TIM4.Prescaler=71 UART5.IPParameters=VirtualMode UART5.VirtualMode=Asynchronous USART1.IPParameters=VirtualMode @@ -216,4 +242,7 @@ VP_FREERTOS_VS_CMSIS_V2.Mode=CMSIS_V2 VP_FREERTOS_VS_CMSIS_V2.Signal=FREERTOS_VS_CMSIS_V2 VP_SYS_VS_tim8.Mode=TIM8 VP_SYS_VS_tim8.Signal=SYS_VS_tim8 +VP_TIM4_VS_ClockSourceINT.Mode=Internal +VP_TIM4_VS_ClockSourceINT.Signal=TIM4_VS_ClockSourceINT board=custom +rtos.0.ip=FREERTOS diff --git a/开发资料/Gerber_多功能的按摩仪器_2026-01-22.zip b/开发资料/串口屏资料/Gerber_多功能的按摩仪器_2026-01-22.zip similarity index 100% rename from 开发资料/Gerber_多功能的按摩仪器_2026-01-22.zip rename to 开发资料/串口屏资料/Gerber_多功能的按摩仪器_2026-01-22.zip diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART.rar b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART.rar new file mode 100644 index 0000000..a34d58d Binary files /dev/null and b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART.rar differ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/CORE/arm_common_tables.h b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/CORE/arm_common_tables.h new file mode 100644 index 0000000..7245c4f --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/CORE/arm_common_tables.h @@ -0,0 +1,35 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 11. November 2010 +* $Revision: V1.0.2 +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern uint16_t armBitRevTable[256]; +extern q15_t armRecipTableQ15[64]; +extern q31_t armRecipTableQ31[64]; +extern const q31_t realCoefAQ31[1024]; +extern const q31_t realCoefBQ31[1024]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/CORE/arm_math.h b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/CORE/arm_math.h new file mode 100644 index 0000000..ffa03b6 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/CORE/arm_math.h @@ -0,0 +1,7051 @@ +/* ---------------------------------------------------------------------- + * Copyright (C) 2010 ARM Limited. All rights reserved. + * + * $Date: 15. July 2011 + * $Revision: V1.0.10 + * + * Project: CMSIS DSP Library + * Title: arm_math.h + * + * Description: Public header file for CMSIS DSP Library + * + * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 + * + * Version 1.0.10 2011/7/15 + * Big Endian support added and Merged M0 and M3/M4 Source code. + * + * Version 1.0.3 2010/11/29 + * Re-organized the CMSIS folders and updated documentation. + * + * Version 1.0.2 2010/11/11 + * Documentation updated. + * + * Version 1.0.1 2010/10/05 + * Production release and review comments incorporated. + * + * Version 1.0.0 2010/09/20 + * Production release and review comments incorporated. + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of modules each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Processor Support + * + * The library is completely written in C and is fully CMSIS compliant. + * High performance is achieved through maximum use of Cortex-M4 intrinsics. + * + * The supplied library source code also builds and runs on the Cortex-M3 and Cortex-M0 processor, + * with the DSP intrinsics being emulated through software. + * + * + * Toolchain Support + * + * The library has been developed and tested with MDK-ARM version 4.21. + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Using the Library + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 depending on the target processor in the application. + * + * Examples + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Building the Library + * + * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\DSP_Lib\Source\ARM folder. + * - arm_cortexM0b_math.uvproj + * - arm_cortexM0l_math.uvproj + * - arm_cortexM3b_math.uvproj + * - arm_cortexM3l_math.uvproj + * - arm_cortexM4b_math.uvproj + * - arm_cortexM4l_math.uvproj + * - arm_cortexM4bf_math.uvproj + * - arm_cortexM4lf_math.uvproj + * + * Each library project have differant pre-processor macros. + * + * ARM_MATH_CMx: + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on cortex-M0 target. + * + * ARM_MATH_BIG_ENDIAN: + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * ARM_MATH_MATRIX_CHECK: + * Define macro for checking on the input and output sizes of matrices + * + * ARM_MATH_ROUNDING: + * Define macro for rounding on support functions + * + * __FPU_PRESENT: + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + * + * The project can be built by opening the appropriate project in MDK-ARM 4.21 chain and defining the optional pre processor MACROs detailed above. + * + * Copyright Notice + * + * Copyright (C) 2010 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the #define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined (ARM_MATH_CM4) + #include "core_cm4.h" +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" +#else +#include "ARMCM4.h" +#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....." +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" + #include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#define PI 3.14159265358979f + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x800000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#define __SIMD32(addr) (*(int32_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) + +#endif + + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + static __INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + static __INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + static __INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + static __INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + +#if defined (ARM_MATH_CM0) && defined ( __CC_ARM ) +#define __CLZ __clz +#endif + +#if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) + + static __INLINE uint32_t __CLZ(q31_t data); + + + static __INLINE uint32_t __CLZ(q31_t data) + { + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return(count); + + } + +#endif + + /** + * @brief Function to Calculates 1/in(reciprocal) value of Q31 Data type. + */ + + static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + + uint32_t out, tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) + { + signBits = __CLZ(in) - 1; + } + else + { + signBits = __CLZ(-in) - 1; + } + + /* Convert input sample to 1.31 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = (uint32_t) (in >> 24u); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (q31_t) (((q63_t) in * out) >> 31u); + tempVal = 0x7FFFFFFF - tempVal; + /* 1.31 with exp 1 */ + //out = (q31_t) (((q63_t) out * tempVal) >> 30u); + out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + + } + + /** + * @brief Function to Calculates 1/in(reciprocal) value of Q15 Data type. + */ + static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + + uint32_t out = 0, tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) + { + signBits = __CLZ(in) - 17; + } + else + { + signBits = __CLZ(-in) - 17; + } + + /* Convert input sample to 1.15 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = in >> 8; + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0; i < 2; i++) + { + tempVal = (q15_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFF - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + + } + + + /* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0) + + static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) + { + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if(x > 0) + { + posMax = (posMax - 1); + + if(x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if(x < negMin) + { + x = negMin; + } + } + return (x); + + + } + +#endif /* end of ARM_MATH_CM0 */ + + + + /* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + static __INLINE q31_t __QADD8( + q31_t x, + q31_t y) + { + + q31_t sum; + q7_t r, s, t, u; + + r = (char) x; + s = (char) y; + + r = __SSAT((q31_t) (r + s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); + t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); + u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); + + sum = (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | + (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); + + return sum; + + } + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB8( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s, t, u; + + r = (char) x; + s = (char) y; + + r = __SSAT((r - s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; + t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; + u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; + + sum = + (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & 0x000000FF); + + return sum; + } + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + static __INLINE q31_t __QADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = __SSAT(r + s, 16); + s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + static __INLINE q31_t __SHADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) + (s >> 1)); + s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = __SSAT(r - s, 16); + s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __SHSUB16( + q31_t x, + q31_t y) + { + + q31_t diff; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) - (s >> 1)); + s = (((x >> 17) - (y >> 17)) << 16); + + diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return diff; + } + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + static __INLINE q31_t __QASX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) + + clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + static __INLINE q31_t __SHASX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) - (y >> 17)); + s = (((x >> 17) + (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + static __INLINE q31_t __QSAX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) + + clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + static __INLINE q31_t __SHSAX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) + (y >> 17)); + s = (((x >> 17) - (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMUSDX( + q31_t x, + q31_t y) + { + + return ((q31_t)(((short) x * (short) (y >> 16)) - + ((short) (x >> 16) * (short) y))); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + static __INLINE q31_t __SMUADX( + q31_t x, + q31_t y) + { + + return ((q31_t)(((short) x * (short) (y >> 16)) + + ((short) (x >> 16) * (short) y))); + } + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + static __INLINE q31_t __QADD( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x + y); + } + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + static __INLINE q31_t __QSUB( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x - y); + } + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + static __INLINE q31_t __SMLAD( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y >> 16)) + + ((short) x * (short) y)); + } + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + static __INLINE q31_t __SMLADX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y)) + + ((short) x * (short) (y >> 16))); + } + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMLSDX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum - ((short) (x >> 16) * (short) (y)) + + ((short) x * (short) (y >> 16))); + } + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + static __INLINE q63_t __SMLALD( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y >> 16)) + + ((short) x * (short) y)); + } + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + static __INLINE q63_t __SMLALDX( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((short) (x >> 16) * (short) y)) + + ((short) x * (short) (y >> 16)); + } + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + static __INLINE q31_t __SMUAD( + q31_t x, + q31_t y) + { + + return (((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + static __INLINE q31_t __SMUSD( + q31_t x, + q31_t y) + { + + return (-((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + + + +#endif /* (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] *S points to an instance of the Q7 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] *S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + * @return none + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] *S points to an instance of the Q15 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] *S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] *S points to an instance of the Q31 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] *S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] *S points to an instance of the floating-point FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] *S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q15; + + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + + + } arm_biquad_casd_df1_inst_f32; + + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q31; + + + + /** + * @brief Floating-point matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q31 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] *pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] *pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t *pData); + + /** + * @brief Q15 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t *pData); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t *pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + #ifdef ARM_MATH_CM0 + q15_t A1; + q15_t A2; + #else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ + #endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] *S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @return none + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @return none + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the q15 PID Control structure + * @return none + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; + float32_t x1; + float32_t xSpacing; + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + + /** + * @brief Processing function for the Q15 CFFT/CIFFT. + * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure. + * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. + * @return none. + */ + + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Initialization function for the Q15 CFFT/CIFFT. + * @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure. + * @param[in] fftLen length of the FFT. + * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. + */ + + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Processing function for the Q31 CFFT/CIFFT. + * @param[in] *S points to an instance of the Q31 CFFT/CIFFT structure. + * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. + * @return none. + */ + + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Initialization function for the Q31 CFFT/CIFFT. + * @param[in,out] *S points to an instance of the Q31 CFFT/CIFFT structure. + * @param[in] fftLen length of the FFT. + * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. + */ + + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Processing function for the floating-point CFFT/CIFFT. + * @param[in] *S points to an instance of the floating-point CFFT/CIFFT structure. + * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. + * @return none. + */ + + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Initialization function for the floating-point CFFT/CIFFT. + * @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure. + * @param[in] fftLen length of the FFT. + * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. + */ + + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + + + /*---------------------------------------------------------------------- + * Internal functions prototypes FFT function + ----------------------------------------------------------------------*/ + + /** + * @brief Core function for the floating-point CFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to the twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_f32( + float32_t * pSrc, + uint16_t fftLen, + float32_t * pCoef, + uint16_t twidCoefModifier); + + /** + * @brief Core function for the floating-point CIFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @param[in] onebyfftLen value of 1/fftLen. + * @return none. + */ + + void arm_radix4_butterfly_inverse_f32( + float32_t * pSrc, + uint16_t fftLen, + float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen); + + /** + * @brief In-place bit reversal function. + * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. + * @param[in] fftSize length of the FFT. + * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table. + * @param[in] *pBitRevTab points to the bit reversal table. + * @return none. + */ + + void arm_bitreversal_f32( + float32_t *pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + uint16_t *pBitRevTab); + + /** + * @brief Core function for the Q31 CFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_q31( + q31_t *pSrc, + uint32_t fftLen, + q31_t *pCoef, + uint32_t twidCoefModifier); + + /** + * @brief Core function for the Q31 CIFFT butterfly process. + * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + q31_t * pCoef, + uint32_t twidCoefModifier); + + /** + * @brief In-place bit reversal function. + * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. + * @param[in] fftLen length of the FFT. + * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table + * @param[in] *pBitRevTab points to bit reversal table. + * @return none. + */ + + void arm_bitreversal_q31( + q31_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + uint16_t *pBitRevTab); + + /** + * @brief Core function for the Q15 CFFT butterfly process. + * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef16 points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_q15( + q15_t *pSrc16, + uint32_t fftLen, + q15_t *pCoef16, + uint32_t twidCoefModifier); + + /** + * @brief Core function for the Q15 CIFFT butterfly process. + * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type. + * @param[in] fftLen length of the FFT. + * @param[in] *pCoef16 points to twiddle coefficient buffer. + * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + * @return none. + */ + + void arm_radix4_butterfly_inverse_q15( + q15_t *pSrc16, + uint32_t fftLen, + q15_t *pCoef16, + uint32_t twidCoefModifier); + + /** + * @brief In-place bit reversal function. + * @param[in, out] *pSrc points to the in-place buffer of Q15 data type. + * @param[in] fftLen length of the FFT. + * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table + * @param[in] *pBitRevTab points to bit reversal table. + * @return none. + */ + + void arm_bitreversal_q15( + q15_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + uint16_t *pBitRevTab); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint32_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint32_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + /** + * @brief Processing function for the Q15 RFFT/RIFFT. + * @param[in] *S points to an instance of the Q15 RFFT/RIFFT structure. + * @param[in] *pSrc points to the input buffer. + * @param[out] *pDst points to the output buffer. + * @return none. + */ + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Initialization function for the Q15 RFFT/RIFFT. + * @param[in, out] *S points to an instance of the Q15 RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of the Q15 CFFT/CIFFT structure. + * @param[in] fftLenReal length of the FFT. + * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. + */ + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + /** + * @brief Processing function for the Q31 RFFT/RIFFT. + * @param[in] *S points to an instance of the Q31 RFFT/RIFFT structure. + * @param[in] *pSrc points to the input buffer. + * @param[out] *pDst points to the output buffer. + * @return none. + */ + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Initialization function for the Q31 RFFT/RIFFT. + * @param[in, out] *S points to an instance of the Q31 RFFT/RIFFT structure. + * @param[in, out] *S_CFFT points to an instance of the Q31 CFFT/CIFFT structure. + * @param[in] fftLenReal length of the FFT. + * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. + */ + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + /** + * @brief Initialization function for the floating-point RFFT/RIFFT. + * @param[in,out] *S points to an instance of the floating-point RFFT/RIFFT structure. + * @param[in,out] *S_CFFT points to an instance of the floating-point CFFT/CIFFT structure. + * @param[in] fftLenReal length of the FFT. + * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. + * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. + */ + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + /** + * @brief Processing function for the floating-point RFFT/RIFFT. + * @param[in] *S points to an instance of the floating-point RFFT/RIFFT structure. + * @param[in] *pSrc points to the input buffer. + * @param[out] *pDst points to the output buffer. + * @return none. + */ + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q31 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q15 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + /** + * @brief Floating-point vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Dot product of floating-point vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + /** + * @brief Dot product of Q7 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + /** + * @brief Dot product of Q15 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Dot product of Q31 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + +/** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_f32; + + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t *pkCoeffs, + float32_t *pvCoeffs, + float32_t *pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t *pkCoeffs, + q31_t *pvCoeffs, + q31_t *pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the Q15 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + * @return none. + */ + + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t *pkCoeffs, + q15_t *pvCoeffs, + q15_t *pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + + } arm_lms_instance_q31; + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t *pCoeffs, + q31_t *pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Correlation of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + /** + * @brief Correlation of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Correlation of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t *pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /* + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cos output. + * @return none. + */ + + void arm_sin_cos_f32( + float32_t theta, + float32_t *pSinVal, + float32_t *pCcosVal); + + /* + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cosine output. + * @return none. + */ + + void arm_sin_cos_q31( + q31_t theta, + q31_t *pSinVal, + q31_t *pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + + + static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + + static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + + static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + + /* Implementation of PID controller */ + + #ifdef ARM_MATH_CM0 + + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0 )* in ; + + #else + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD(S->A0, in); + + #endif + + #ifdef ARM_MATH_CM0 + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0] ; + acc += (q31_t) S->A2 * S->state[1] ; + + #else + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc = __SMLALD(S->A1, (q31_t)__SIMD32(S->state), acc); + + #endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + + /** + * @ingroup groupController + */ + + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + */ + + static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + + } + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + */ + + + static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; + + } + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + + static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * The function implements the forward Park transform. + * + */ + + static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + + } + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + + + static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + */ + + static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + + static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + + static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (x - S->x1) / xSpacing; + + if(i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if(i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues-1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i +1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0)/(x1-x0)); + + } + + /* returns output value */ + return (y); + } + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] *pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q31_t arm_linear_interp_q31(q31_t *pYData, + q31_t x, uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20); + + if(index >= (nValues - 1)) + { + return(pYData[nValues - 1]); + } + else if(index < 0) + { + return(pYData[0]); + } + else + { + + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + + } + + } + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] *pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q15_t arm_linear_interp_q15(q15_t *pYData, q31_t x, uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); + + if(index >= (nValues - 1)) + { + return(pYData[nValues - 1]); + } + else if(index < 0) + { + return(pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (y >> 20); + } + + + } + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] *pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + + + static __INLINE q7_t arm_linear_interp_q7(q7_t *pYData, q31_t x, uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); + + + if(index >= (nValues - 1)) + { + return(pYData[nValues - 1]); + } + else if(index < 0) + { + return(pYData[0]); + } + else + { + + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (y >> 20u); + + } + + } + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + + float32_t arm_sin_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q31_t arm_sin_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q15_t arm_sin_q15( + q15_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + + float32_t arm_cos_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q31_t arm_cos_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + + static __INLINE arm_status arm_sqrt_f32( + float32_t in, float32_t *pOut) + { + if(in > 0) + { + +// #if __FPU_USED + #if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); + #else + *pOut = sqrtf(in); + #endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, q31_t *pOut); + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, q15_t *pOut); + + /** + * @} end of SQRT group + */ + + + + + + + /** + * @brief floating-point Circular write function. + */ + + static __INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + static __INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + /** + * @brief Q15 Circular write function. + */ + + static __INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q15 Circular Read function. + */ + static __INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + + static __INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q7 Circular Read function. + */ + static __INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + /** + * @brief Mean value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Mean value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Floating-point complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + /** + * @brief Q31 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + /** + * @brief Floating-point complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[in] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + * @return none. + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + + + static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows-1) || yIndex < 0 || yIndex > ( S->numCols-1)) + { + return(0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex-1) * S->numCols ; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex-1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + + } + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20u); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20u); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) + { + return(0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return (acc << 2u); + + } + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) + { + return(0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return (acc >> 36); + + } + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) + { + return(0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return (acc >> 40); + + } + + /** + * @} end of BilinearInterpolate group + */ + + + + + + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_MATH_H */ + + +/** + * + * End of file. + */ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/CORE/core_cm0.h b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/CORE/core_cm0.h new file mode 100644 index 0000000..9d7a19f --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/CORE/core_cm0.h @@ -0,0 +1,665 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V2.10 + * @date 19. July 2011 + * + * @note + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + + +/** \mainpage CMSIS Cortex-M0 + + This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. + It consists of: + + - Cortex-M Core Register Definitions + - Cortex-M functions + - Cortex-M instructions + + The CMSIS Cortex-M0 Core Peripheral Access Layer contains C and assembly functions that ease + access to the Cortex-M Core + */ + +/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions + CMSIS violates following MISRA-C2004 Rules: + + - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \defgroup CMSIS_core_definitions CMSIS Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core + - Cortex-M core Revision Number + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + +/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + /* add preprocessor checks */ +#endif + +#include /*!< standard types definitions */ +#include "core_cmInstr.h" /*!< Core Instruction Access */ +#include "core_cmFunc.h" /*!< Core Function Access */ + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000 + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + +/*@} end of group CMSIS_core_definitions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** \defgroup CMSIS_core_register CMSIS Core Register + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE CMSIS Core + Type definitions for the Cortex-M Core Registers + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC CMSIS NVIC + Type definitions for the Cortex-M NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB CMSIS SCB + Type definitions for the Cortex-M System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick CMSIS SysTick + Type definitions for the Cortex-M System Timer Registers + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug CMSIS Core Debug + Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP + and not via processor. Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + This function enables a device specific interrupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to enable + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + This function disables a device specific interrupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to disable + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + This function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Number of the interrupt for get pending + \return 0 Interrupt status is not pending + \return 1 Interrupt status is pending + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + This function sets the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for set pending + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + This function clears the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for clear pending + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + This function sets the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + Note: The priority cannot be set for every core interrupt. + + \param [in] IRQn Number of the interrupt for set priority + \param [in] priority Priority to set + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + This function reads the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + The returned priority value is automatically aligned to the implemented + priority bits of the microcontroller. + + \param [in] IRQn Number of the interrupt for get priority + \return Interrupt Priority + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + This function initiate a system reset request to reset the MCU. + */ +static __INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + This function initialises the system tick timer and its interrupt and start the system tick timer. + Counter is in free running mode to generate periodical interrupts. + + \param [in] ticks Number of ticks between two interrupts + \return 0 Function succeeded + \return 1 Function failed + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/CORE/core_cmFunc.h b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/CORE/core_cmFunc.h new file mode 100644 index 0000000..88819f9 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/CORE/core_cmFunc.h @@ -0,0 +1,609 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V2.10 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +static __INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +static __INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get ISPR Register + + This function returns the content of the ISPR Register. + + \return ISPR Register value + */ +static __INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +static __INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +static __INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +static __INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +static __INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +static __INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +static __INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +static __INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +static __INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +static __INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +static __INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +static __INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +static __INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + + +/** \brief Get ISPR Register + + This function returns the content of the ISPR Register. + + \return ISPR Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) ); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CORE_CMFUNC_H */ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/CORE/core_cmInstr.h b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/CORE/core_cmInstr.h new file mode 100644 index 0000000..78d2ef8 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/CORE/core_cmInstr.h @@ -0,0 +1,585 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V2.10 + * @date 19. July 2011 + * + * @note + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +static __INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +static __INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) static __INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) static __INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) static __INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) static __INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) static __INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) static __INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value) +{ + uint32_t result; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint8_t result; + + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint16_t result; + + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void) +{ + __ASM volatile ("clrex"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value) +{ + uint8_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/CORE/startup_stm32f0xx.s b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/CORE/startup_stm32f0xx.s new file mode 100644 index 0000000..3a31df4 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/CORE/startup_stm32f0xx.s @@ -0,0 +1,256 @@ +;******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** +;* File Name : startup_stm32f0xx.s +;* Author : MCD Application Team +;* Version : V1.0.0 +;* Date : 23-March-2012 +;* Description : STM32F0xx Devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; @attention +; +; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); +; You may not use this file except in compliance with the License. +; You may obtain a copy of the License at: +; +; http://www.st.com/software_license_agreement_liberty_v2 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +;******************************************************************************* +; +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD TS_IRQHandler ; TS + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD CEC_IRQHandler ; CEC + DCD 0 ; Reserved + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT TS_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_5_IRQHandler [WEAK] + EXPORT ADC1_COMP_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +TS_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Channel4_5_IRQHandler +ADC1_COMP_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM6_DAC_IRQHandler +TIM14_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +CEC_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/HARDWARE/Command.c b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/HARDWARE/Command.c new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/HARDWARE/Command.c @@ -0,0 +1 @@ + diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/HARDWARE/Key.c b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/HARDWARE/Key.c new file mode 100644 index 0000000..8c71910 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/HARDWARE/Key.c @@ -0,0 +1,50 @@ +#include "stm32f0xx.h" +#include "delay.h" + +//=================================================================================================== +/* : + : + ע + ӽƼ޹˾ 2008-2020 ȨУؾ + ˾վ www.sun-lcm.com + Ավ https://shop151604432.taobao.com/index.htm?spm=a1z10.5-c.w5002-14603162597.2.4c2619d6w9oYgh + ֧:QQQ:3085638545 + */ +//==================================================================================================== + + +void KeyInit(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* ʹGPIOBʱ */ + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE); + + /* LEDӦPB1*/ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOA, &GPIO_InitStructure); + +} +unsigned char GetKeyVal(void) +{ + unsigned char ucTmp; + + ucTmp = GPIOA->IDR & 0x3f; + if(ucTmp != 0x3f){ + delay_ms(20); + ucTmp = GPIOA->IDR & 0x3f; + if(ucTmp != 0x3f){ + if( ucTmp == 0x00){ return 1;} + if( ucTmp == 0x02){ return 2;} + if( ucTmp == 0x04){ return 3;} + if( ucTmp == 0x08){ return 4;} + if( ucTmp == 0x10){ return 5;} + if( ucTmp == 0x20){ return 6;} + } + } + +} \ No newline at end of file diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/HARDWARE/Key.h b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/HARDWARE/Key.h new file mode 100644 index 0000000..8bb8000 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/HARDWARE/Key.h @@ -0,0 +1 @@ +void KeyInit(void); diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/HARDWARE/STM32F030Demo.map b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/HARDWARE/STM32F030Demo.map new file mode 100644 index 0000000..71fb0c3 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/HARDWARE/STM32F030Demo.map @@ -0,0 +1,1078 @@ +ARM Linker, 5.03 [Build 76] [MDK-ARM Standard] + +============================================================================== + +Section Cross References + + main.o(.text) refers to delay.o(.text) for delay_init + main.o(.text) refers to led.o(.text) for LED_Init + main.o(.text) refers to usart1.o(.text) for USART1_Init + main.o(.text) refers to __2printf.o(.text) for __2printf + system_stm32f0xx.o(.text) refers to aeabi_sdiv.o(.text) for __aeabi_uidivmod + system_stm32f0xx.o(.text) refers to system_stm32f0xx.o(.data) for SystemCoreClock + startup_stm32f0xx.o(STACK) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32f0xx.o(HEAP) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32f0xx.o(RESET) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32f0xx.o(RESET) refers to startup_stm32f0xx.o(STACK) for __initial_sp + startup_stm32f0xx.o(RESET) refers to startup_stm32f0xx.o(.text) for Reset_Handler + startup_stm32f0xx.o(RESET) refers to stm32f0xx_it.o(.text) for NMI_Handler + startup_stm32f0xx.o(RESET) refers to usart1.o(.text) for USART1_IRQHandler + startup_stm32f0xx.o(.text) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32f0xx.o(.text) refers to system_stm32f0xx.o(.text) for SystemInit + startup_stm32f0xx.o(.text) refers to __main.o(!!!main) for __main + startup_stm32f0xx.o(.text) refers to startup_stm32f0xx.o(HEAP) for Heap_Mem + startup_stm32f0xx.o(.text) refers to startup_stm32f0xx.o(STACK) for Stack_Mem + led.o(.text) refers to stm32f0xx_rcc.o(.text) for RCC_AHBPeriphClockCmd + led.o(.text) refers to stm32f0xx_gpio.o(.text) for GPIO_Init + usart1.o(.emb_text) refers (Special) to use_no_semi_2.o(.text) for __use_no_semihosting + usart1.o(.text) refers (Special) to use_no_semi_2.o(.text) for __use_no_semihosting + usart1.o(.text) refers to stm32f0xx_rcc.o(.text) for RCC_AHBPeriphClockCmd + usart1.o(.text) refers to stm32f0xx_gpio.o(.text) for GPIO_PinAFConfig + usart1.o(.text) refers to stm32f0xx_usart.o(.text) for USART_Init + usart1.o(.text) refers to stm32f0xx_misc.o(.text) for NVIC_Init + usart1.o(.data) refers (Special) to use_no_semi_2.o(.text) for __use_no_semihosting + usart1_api.o(.text) refers to printf.o(.text) for printf + usart1_api.o(.text) refers to usart1_api.o(.data) for sKeyPross + delay.o(.text) refers to stm32f0xx_misc.o(.text) for SysTick_CLKSourceConfig + delay.o(.text) refers to aeabi_sdiv.o(.text) for __aeabi_uidivmod + delay.o(.text) refers to system_stm32f0xx.o(.data) for SystemCoreClock + delay.o(.text) refers to delay.o(.data) for fac_us + stm32f0xx_gpio.o(.text) refers to stm32f0xx_rcc.o(.text) for RCC_AHBPeriphResetCmd + stm32f0xx_rcc.o(.text) refers to aeabi_sdiv.o(.text) for __aeabi_uidivmod + stm32f0xx_rcc.o(.text) refers to stm32f0xx_rcc.o(.data) for APBAHBPrescTable + stm32f0xx_usart.o(.text) refers to stm32f0xx_rcc.o(.text) for RCC_APB2PeriphResetCmd + stm32f0xx_usart.o(.text) refers to aeabi_sdiv.o(.text) for __aeabi_uidivmod + use_no_semi_2.o(.text) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi + printf.o(.text) refers (Special) to _printf_a.o(.ARM.Collect$$_printf_percent$$00000006) for _printf_a + printf.o(.text) refers (Special) to _printf_c.o(.ARM.Collect$$_printf_percent$$00000013) for _printf_c + printf.o(.text) refers (Special) to _printf_charcount.o(.text) for _printf_charcount + printf.o(.text) refers (Special) to _printf_d.o(.ARM.Collect$$_printf_percent$$00000009) for _printf_d + printf.o(.text) refers (Special) to _printf_e.o(.ARM.Collect$$_printf_percent$$00000004) for _printf_e + printf.o(.text) refers (Special) to _printf_f.o(.ARM.Collect$$_printf_percent$$00000003) for _printf_f + printf.o(.text) refers (Special) to printf1.o(x$fpl$printf1) for _printf_fp_dec + printf.o(.text) refers (Special) to printf2.o(x$fpl$printf2) for _printf_fp_hex + printf.o(.text) refers (Special) to _printf_g.o(.ARM.Collect$$_printf_percent$$00000005) for _printf_g + printf.o(.text) refers (Special) to _printf_i.o(.ARM.Collect$$_printf_percent$$00000008) for _printf_i + printf.o(.text) refers (Special) to _printf_dec.o(.text) for _printf_int_dec + printf.o(.text) refers (Special) to _printf_l.o(.ARM.Collect$$_printf_percent$$00000012) for _printf_l + printf.o(.text) refers (Special) to _printf_lc.o(.ARM.Collect$$_printf_percent$$00000015) for _printf_lc + printf.o(.text) refers (Special) to _printf_ll.o(.ARM.Collect$$_printf_percent$$00000007) for _printf_ll + printf.o(.text) refers (Special) to _printf_lld.o(.ARM.Collect$$_printf_percent$$0000000E) for _printf_lld + printf.o(.text) refers (Special) to _printf_lli.o(.ARM.Collect$$_printf_percent$$0000000D) for _printf_lli + printf.o(.text) refers (Special) to _printf_llo.o(.ARM.Collect$$_printf_percent$$00000010) for _printf_llo + printf.o(.text) refers (Special) to _printf_llu.o(.ARM.Collect$$_printf_percent$$0000000F) for _printf_llu + printf.o(.text) refers (Special) to _printf_llx.o(.ARM.Collect$$_printf_percent$$00000011) for _printf_llx + printf.o(.text) refers (Special) to _printf_longlong_dec.o(.text) for _printf_longlong_dec + printf.o(.text) refers (Special) to _printf_hex_int_ll_ptr.o(.text) for _printf_longlong_hex + printf.o(.text) refers (Special) to _printf_oct_int_ll.o(.text) for _printf_longlong_oct + printf.o(.text) refers (Special) to _printf_ls.o(.ARM.Collect$$_printf_percent$$00000016) for _printf_ls + printf.o(.text) refers (Special) to _printf_n.o(.ARM.Collect$$_printf_percent$$00000001) for _printf_n + printf.o(.text) refers (Special) to _printf_o.o(.ARM.Collect$$_printf_percent$$0000000B) for _printf_o + printf.o(.text) refers (Special) to _printf_p.o(.ARM.Collect$$_printf_percent$$00000002) for _printf_p + printf.o(.text) refers (Special) to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + printf.o(.text) refers (Special) to _printf_pad.o(.text) for _printf_post_padding + printf.o(.text) refers (Special) to _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) for _printf_s + printf.o(.text) refers (Special) to _printf_str.o(.text) for _printf_str + printf.o(.text) refers (Special) to _printf_truncate.o(.text) for _printf_truncate_signed + printf.o(.text) refers (Special) to _printf_u.o(.ARM.Collect$$_printf_percent$$0000000A) for _printf_u + printf.o(.text) refers (Special) to _printf_wctomb.o(.text) for _printf_wctomb + printf.o(.text) refers (Special) to _printf_x.o(.ARM.Collect$$_printf_percent$$0000000C) for _printf_x + printf.o(.text) refers to _printf_char_file.o(.text) for _printf_char_file + printf.o(.text) refers to usart1.o(.data) for __stdout + __2printf.o(.text) refers to _printf_char_file.o(.text) for _printf_char_file + __2printf.o(.text) refers to usart1.o(.data) for __stdout + noretval__2printf.o(.text) refers to _printf_char_file.o(.text) for _printf_char_file + noretval__2printf.o(.text) refers to usart1.o(.data) for __stdout + __main.o(!!!main) refers to rtentry.o(.ARM.Collect$$rtentry$$00000000) for __rt_entry + rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for __rt_entry_li + rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for __rt_entry_main + rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to rtentry2.o(.ARM.Collect$$rtentry$$0000000C) for __rt_entry_postli_1 + rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to rtentry2.o(.ARM.Collect$$rtentry$$00000009) for __rt_entry_postsh_1 + rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to rtentry2.o(.ARM.Collect$$rtentry$$00000002) for __rt_entry_presh_1 + rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to rtentry4.o(.ARM.Collect$$rtentry$$00000004) for __rt_entry_sh + aeabi_idiv0_sigfpe.o(.text) refers to rt_div0.o(.text) for __rt_div0 + __printf.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + _printf_str.o(.text) refers (Special) to _printf_char.o(.text) for _printf_cs_common + _printf_str.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_str.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_post_padding + _printf_dec.o(.text) refers (Weak) to _printf_truncate.o(.text) for _printf_truncate_signed + _printf_dec.o(.text) refers (Weak) to _printf_truncate.o(.text) for _printf_truncate_unsigned + _printf_dec.o(.text) refers to rtudiv10.o(.text) for __rt_udiv10 + _printf_dec.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_char_file.o(.text) refers to _printf_char_common.o(.text) for _printf_char_common + _printf_char_file.o(.text) refers to ferror.o(.text) for ferror + _printf_char_file.o(.text) refers to usart1.o(.text) for fputc + _printf_wctomb.o(.text) refers (Special) to _printf_wchar.o(.text) for _printf_lcs_common + _printf_wctomb.o(.text) refers to _wcrtomb.o(.text) for _wcrtomb + _printf_wctomb.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_wctomb.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_post_padding + _printf_wctomb.o(.text) refers to _printf_wctomb.o(.constdata) for .constdata + _printf_wctomb.o(.constdata) refers (Special) to _printf_wchar.o(.text) for _printf_lcs_common + _printf_longlong_dec.o(.text) refers to lludiv10.o(.text) for _ll_udiv10 + _printf_longlong_dec.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_oct_ll.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_oct_int.o(.text) refers (Weak) to _printf_truncate.o(.text) for _printf_truncate_unsigned + _printf_oct_int.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_oct_int_ll.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_oct_int_ll.o(.text) refers (Weak) to _printf_truncate.o(.text) for _printf_truncate_unsigned + _printf_hex_ll.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_hex_ll.o(.text) refers to _printf_hex_ll.o(.constdata) for .constdata + _printf_hex_int.o(.text) refers (Weak) to _printf_truncate.o(.text) for _printf_truncate_unsigned + _printf_hex_int.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_hex_int.o(.text) refers to _printf_hex_int.o(.constdata) for .constdata + _printf_hex_int_ll.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_hex_int_ll.o(.text) refers (Weak) to _printf_truncate.o(.text) for _printf_truncate_unsigned + _printf_hex_int_ll.o(.text) refers to _printf_hex_int_ll.o(.constdata) for .constdata + _printf_hex_ptr.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_hex_ptr.o(.text) refers to _printf_hex_ptr.o(.constdata) for .constdata + _printf_hex_int_ptr.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_hex_int_ptr.o(.text) refers (Weak) to _printf_truncate.o(.text) for _printf_truncate_unsigned + _printf_hex_int_ptr.o(.text) refers to _printf_hex_int_ptr.o(.constdata) for .constdata + _printf_hex_ll_ptr.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_hex_ll_ptr.o(.text) refers to _printf_hex_ll_ptr.o(.constdata) for .constdata + _printf_hex_int_ll_ptr.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_hex_int_ll_ptr.o(.text) refers (Weak) to _printf_truncate.o(.text) for _printf_truncate_unsigned + _printf_hex_int_ll_ptr.o(.text) refers to _printf_hex_int_ll_ptr.o(.constdata) for .constdata + __printf_flags.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags.o(.text) refers to __printf_flags.o(.constdata) for .constdata + __printf_ss.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_ss.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_ss.o(.text) refers to __printf_flags_ss.o(.constdata) for .constdata + __printf_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit + __printf_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit + __printf_flags_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_wp.o(.text) refers to __printf_flags_wp.o(.constdata) for .constdata + __printf_ss_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit + __printf_ss_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_ss_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit + __printf_flags_ss_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_ss_wp.o(.text) refers to __printf_flags_ss_wp.o(.constdata) for .constdata + _printf_c.o(.ARM.Collect$$_printf_percent$$00000013) refers (Weak) to _printf_char.o(.text) for _printf_char + _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) refers (Weak) to _printf_char.o(.text) for _printf_string + _printf_n.o(.ARM.Collect$$_printf_percent$$00000001) refers (Weak) to _printf_charcount.o(.text) for _printf_charcount + _printf_x.o(.ARM.Collect$$_printf_percent$$0000000C) refers (Weak) to _printf_hex_int_ll_ptr.o(.text) for _printf_int_hex + _printf_p.o(.ARM.Collect$$_printf_percent$$00000002) refers (Weak) to _printf_hex_int_ll_ptr.o(.text) for _printf_hex_ptr + _printf_o.o(.ARM.Collect$$_printf_percent$$0000000B) refers (Weak) to _printf_oct_int_ll.o(.text) for _printf_int_oct + _printf_i.o(.ARM.Collect$$_printf_percent$$00000008) refers (Weak) to _printf_dec.o(.text) for _printf_int_dec + _printf_d.o(.ARM.Collect$$_printf_percent$$00000009) refers (Weak) to _printf_dec.o(.text) for _printf_int_dec + _printf_u.o(.ARM.Collect$$_printf_percent$$0000000A) refers (Weak) to _printf_dec.o(.text) for _printf_int_dec + _printf_f.o(.ARM.Collect$$_printf_percent$$00000003) refers (Weak) to printf1.o(x$fpl$printf1) for _printf_fp_dec + _printf_e.o(.ARM.Collect$$_printf_percent$$00000004) refers (Weak) to printf1.o(x$fpl$printf1) for _printf_fp_dec + _printf_g.o(.ARM.Collect$$_printf_percent$$00000005) refers (Weak) to printf1.o(x$fpl$printf1) for _printf_fp_dec + _printf_a.o(.ARM.Collect$$_printf_percent$$00000006) refers (Weak) to printf2.o(x$fpl$printf2) for _printf_fp_hex + _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) refers (Special) to _printf_percent_end.o(.ARM.Collect$$_printf_percent$$00000017) for _printf_percent_end + _printf_lli.o(.ARM.Collect$$_printf_percent$$0000000D) refers (Special) to _printf_ll.o(.ARM.Collect$$_printf_percent$$00000007) for _printf_ll + _printf_lli.o(.ARM.Collect$$_printf_percent$$0000000D) refers (Weak) to _printf_longlong_dec.o(.text) for _printf_longlong_dec + _printf_lld.o(.ARM.Collect$$_printf_percent$$0000000E) refers (Special) to _printf_ll.o(.ARM.Collect$$_printf_percent$$00000007) for _printf_ll + _printf_lld.o(.ARM.Collect$$_printf_percent$$0000000E) refers (Weak) to _printf_longlong_dec.o(.text) for _printf_longlong_dec + _printf_llu.o(.ARM.Collect$$_printf_percent$$0000000F) refers (Special) to _printf_ll.o(.ARM.Collect$$_printf_percent$$00000007) for _printf_ll + _printf_llu.o(.ARM.Collect$$_printf_percent$$0000000F) refers (Weak) to _printf_longlong_dec.o(.text) for _printf_longlong_dec + _printf_lc.o(.ARM.Collect$$_printf_percent$$00000015) refers (Special) to _printf_l.o(.ARM.Collect$$_printf_percent$$00000012) for _printf_l + _printf_lc.o(.ARM.Collect$$_printf_percent$$00000015) refers (Weak) to _printf_wchar.o(.text) for _printf_wchar + _printf_ls.o(.ARM.Collect$$_printf_percent$$00000016) refers (Special) to _printf_l.o(.ARM.Collect$$_printf_percent$$00000012) for _printf_l + _printf_ls.o(.ARM.Collect$$_printf_percent$$00000016) refers (Weak) to _printf_wchar.o(.text) for _printf_wstring + _printf_llo.o(.ARM.Collect$$_printf_percent$$00000010) refers (Special) to _printf_ll.o(.ARM.Collect$$_printf_percent$$00000007) for _printf_ll + _printf_llo.o(.ARM.Collect$$_printf_percent$$00000010) refers (Weak) to _printf_oct_int_ll.o(.text) for _printf_ll_oct + _printf_llx.o(.ARM.Collect$$_printf_percent$$00000011) refers (Special) to _printf_ll.o(.ARM.Collect$$_printf_percent$$00000007) for _printf_ll + _printf_llx.o(.ARM.Collect$$_printf_percent$$00000011) refers (Weak) to _printf_hex_int_ll_ptr.o(.text) for _printf_ll_hex + printf1.o(x$fpl$printf1) refers to _printf_fp_dec.o(.text) for _printf_fp_dec_real + printf2.o(x$fpl$printf2) refers to _printf_fp_hex.o(.text) for _printf_fp_hex_real + printf2b.o(x$fpl$printf2) refers to _printf_fp_hex.o(.text) for _printf_fp_hex_real + rtentry2.o(.ARM.Collect$$rtentry$$00000008) refers to boardinit2.o(.text) for _platform_post_stackheap_init + rtentry2.o(.ARM.Collect$$rtentry$$0000000A) refers to libinit.o(.ARM.Collect$$libinit$$00000000) for __rt_lib_init + rtentry2.o(.ARM.Collect$$rtentry$$0000000B) refers to boardinit3.o(.text) for _platform_post_lib_init + rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to main.o(.text) for main + rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to exit.o(.text) for exit + rtentry2.o(.ARM.exidx) refers to rtentry2.o(.ARM.Collect$$rtentry$$00000001) for .ARM.Collect$$rtentry$$00000001 + rtentry2.o(.ARM.exidx) refers to rtentry2.o(.ARM.Collect$$rtentry$$00000008) for .ARM.Collect$$rtentry$$00000008 + rtentry2.o(.ARM.exidx) refers to rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for .ARM.Collect$$rtentry$$0000000A + rtentry2.o(.ARM.exidx) refers to rtentry2.o(.ARM.Collect$$rtentry$$0000000B) for .ARM.Collect$$rtentry$$0000000B + rtentry2.o(.ARM.exidx) refers to rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for .ARM.Collect$$rtentry$$0000000D + rtentry4.o(.ARM.Collect$$rtentry$$00000004) refers to sys_stackheap_outer.o(.text) for __user_setup_stackheap + rtentry4.o(.ARM.exidx) refers to rtentry4.o(.ARM.Collect$$rtentry$$00000004) for .ARM.Collect$$rtentry$$00000004 + rt_div0.o(.text) refers to defsig_fpe_outer.o(.text) for __rt_SIGFPE + _printf_intcommon.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_intcommon.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_intcommon.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_post_padding + _printf_fp_dec.o(.text) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + _printf_fp_dec.o(.text) refers (Special) to lc_numeric_c.o(locale$$code) for _get_lc_numeric + _printf_fp_dec.o(.text) refers to bigflt0.o(.text) for _btod_etento + _printf_fp_dec.o(.text) refers to btod.o(.text) for _btod_d2e + _printf_fp_dec.o(.text) refers to lludiv10.o(.text) for _ll_udiv10 + _printf_fp_dec.o(.text) refers to fpclassify.o(i.__ARM_fpclassify) for __ARM_fpclassify + _printf_fp_dec.o(.text) refers to _printf_fp_infnan.o(.text) for _printf_fp_infnan + _printf_fp_dec.o(.text) refers to rtudiv10.o(.text) for __rt_udiv10 + _printf_fp_dec.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_fp_dec.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_fp_dec.o(.text) refers to rt_locale_intlibspace.o(.text) for __rt_locale + _printf_fp_dec.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_post_padding + _printf_fp_hex.o(.text) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + _printf_fp_hex.o(.text) refers to fpclassify.o(i.__ARM_fpclassify) for __ARM_fpclassify + _printf_fp_hex.o(.text) refers to _printf_fp_infnan.o(.text) for _printf_fp_infnan + _printf_fp_hex.o(.text) refers to aeabi_sdiv.o(.text) for __aeabi_idivmod + _printf_fp_hex.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_fp_hex.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_fp_hex.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_post_padding + _printf_fp_hex.o(.text) refers to _printf_fp_hex.o(.constdata) for .constdata + _printf_fp_hex.o(.constdata) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + _printf_char_common.o(.text) refers to __printf_flags_ss_wp.o(.text) for __printf + _printf_char.o(.text) refers (Weak) to _printf_str.o(.text) for _printf_str + _printf_wchar.o(.text) refers (Weak) to _printf_wctomb.o(.text) for _printf_wctomb + _wcrtomb.o(.text) refers to rt_ctype_table.o(.text) for __rt_ctype_table + sys_stackheap_outer.o(.text) refers to libspace.o(.text) for __user_perproc_libspace + sys_stackheap_outer.o(.text) refers to startup_stm32f0xx.o(.text) for __user_initial_stackheap + sys_stackheap_outer.o(__vectab_stack_and_reset_area) refers to tempstk.o(.text) for __temporary_stack_top + sys_stackheap_outer.o(__vectab_stack_and_reset_area) refers to __main.o(!!!main) for __main + rt_ctype_table.o(.text) refers to rt_locale_intlibspace.o(.text) for __rt_locale + rt_ctype_table.o(.text) refers to lc_ctype_c.o(locale$$code) for _get_lc_ctype + rt_locale.o(.text) refers to rt_locale.o(.bss) for __rt_locale_data + rt_locale_intlibspace.o(.text) refers to libspace.o(.bss) for __libspace_start + _printf_fp_infnan.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_fp_infnan.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_post_padding + bigflt0.o(.text) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + bigflt0.o(.text) refers to aeabi_sdiv.o(.text) for __aeabi_idivmod + bigflt0.o(.text) refers to btod.o(.text) for _btod_emul + bigflt0.o(.text) refers to bigflt0.o(.constdata) for .constdata + bigflt0.o(.constdata) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + btod.o(.text) refers to btod.o(i.__ARM_common_ll_muluu) for __ARM_common_ll_muluu + lc_numeric_c.o(locale$$data) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000014) for __rt_lib_init_lc_numeric_2 + lc_numeric_c.o(locale$$code) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000014) for __rt_lib_init_lc_numeric_2 + lc_numeric_c.o(locale$$code) refers to strcmp.o(.text) for strcmp + lc_numeric_c.o(locale$$code) refers to lc_numeric_c.o(locale$$data) for __lcnum_c_name + exit.o(.text) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for __rt_exit + defsig_fpe_outer.o(.text) refers to defsig_fpe_inner.o(.text) for __rt_SIGFPE_inner + defsig_fpe_outer.o(.text) refers to defsig_exit.o(.text) for __sig_exit + defsig_fpe_formal.o(.text) refers to rt_raise.o(.text) for __rt_raise + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002C) for __rt_lib_init_alloca_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002A) for __rt_lib_init_argv_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000019) for __rt_lib_init_atexit_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001F) for __rt_lib_init_clock_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000030) for __rt_lib_init_cpp_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002E) for __rt_lib_init_exceptions_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000001) for __rt_lib_init_fp_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001D) for __rt_lib_init_fp_trap_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000021) for __rt_lib_init_getenv_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000008) for __rt_lib_init_heap_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000F) for __rt_lib_init_lc_collate_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000011) for __rt_lib_init_lc_ctype_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000013) for __rt_lib_init_lc_monetary_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000015) for __rt_lib_init_lc_numeric_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000017) for __rt_lib_init_lc_time_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000C) for __rt_lib_init_rand_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000031) for __rt_lib_init_return + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001B) for __rt_lib_init_signal_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000023) for __rt_lib_init_stdio_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000A) for __rt_lib_init_user_alloc_1 + ieee_status.o(.text) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + fpclassify.o(i.__ARM_fpclassify) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + libspace.o(.text) refers to libspace.o(.bss) for __libspace_start + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1 + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1 + rtexit.o(.ARM.exidx) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for .ARM.Collect$$rtexit$$00000000 + rt_raise.o(.text) refers to __raise.o(.text) for __raise + rt_raise.o(.text) refers to usart1.o(.text) for _sys_exit + lc_ctype_c.o(locale$$data) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000010) for __rt_lib_init_lc_ctype_2 + lc_ctype_c.o(locale$$code) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000010) for __rt_lib_init_lc_ctype_2 + lc_ctype_c.o(locale$$code) refers to strcmp.o(.text) for strcmp + lc_ctype_c.o(locale$$code) refers to lc_ctype_c.o(locale$$data) for __lcctype_c_name + defsig_exit.o(.text) refers to usart1.o(.text) for _sys_exit + defsig_fpe_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + libinit2.o(.ARM.Collect$$libinit$$0000000D) refers (Weak) to rt_locale_intlibspace.o(.text) for __rt_locale + libinit2.o(.ARM.Collect$$libinit$$0000000E) refers to libinit2.o(.ARM.Collect$$libinit$$0000000D) for .ARM.Collect$$libinit$$0000000D + libinit2.o(.ARM.Collect$$libinit$$00000010) refers to libinit2.o(.ARM.Collect$$libinit$$0000000D) for .ARM.Collect$$libinit$$0000000D + libinit2.o(.ARM.Collect$$libinit$$00000010) refers (Weak) to lc_ctype_c.o(locale$$code) for _get_lc_ctype + libinit2.o(.ARM.Collect$$libinit$$00000012) refers to libinit2.o(.ARM.Collect$$libinit$$0000000D) for .ARM.Collect$$libinit$$0000000D + libinit2.o(.ARM.Collect$$libinit$$00000014) refers to libinit2.o(.ARM.Collect$$libinit$$0000000D) for .ARM.Collect$$libinit$$0000000D + libinit2.o(.ARM.Collect$$libinit$$00000014) refers (Weak) to lc_numeric_c.o(locale$$code) for _get_lc_numeric + libinit2.o(.ARM.Collect$$libinit$$00000016) refers to libinit2.o(.ARM.Collect$$libinit$$0000000D) for .ARM.Collect$$libinit$$0000000D + libinit2.o(.ARM.Collect$$libinit$$00000024) refers to argv_veneer.o(.text) for __ARM_argv_veneer + libinit2.o(.ARM.Collect$$libinit$$00000025) refers to argv_veneer.o(.text) for __ARM_argv_veneer + rtexit2.o(.ARM.Collect$$rtexit$$00000003) refers to libshutdown.o(.ARM.Collect$$libshutdown$$00000000) for __rt_lib_shutdown + rtexit2.o(.ARM.Collect$$rtexit$$00000004) refers to usart1.o(.text) for _sys_exit + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000001) for .ARM.Collect$$rtexit$$00000001 + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for .ARM.Collect$$rtexit$$00000003 + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for .ARM.Collect$$rtexit$$00000004 + __raise.o(.text) refers to defsig.o(CL$$defsig) for __default_signal_handler + defsig_general.o(.text) refers to sys_wrch.o(.text) for _ttywrch + sys_wrch.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_wrch.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + defsig.o(CL$$defsig) refers to defsig_fpe_inner.o(.text) for __rt_SIGFPE_inner + defsig.o(CL$$defsig) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner + _get_argv_nomalloc.o(.text) refers (Special) to hrguard.o(.text) for __heap_region$guard + _get_argv_nomalloc.o(.text) refers to defsig_rtmem_outer.o(.text) for __rt_SIGRTMEM + _get_argv_nomalloc.o(.text) refers to sys_command.o(.text) for _sys_command_string + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000006) for __rt_lib_shutdown_fp_trap_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000E) for __rt_lib_shutdown_heap_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F) for __rt_lib_shutdown_return + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000009) for __rt_lib_shutdown_signal_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000003) for __rt_lib_shutdown_stdio_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000B) for __rt_lib_shutdown_user_alloc_1 + sys_command.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_command.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + defsig_abrt_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_rtred_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_rtmem_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_rtmem_outer.o(.text) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner + defsig_rtmem_outer.o(.text) refers to defsig_exit.o(.text) for __sig_exit + defsig_rtmem_formal.o(.text) refers to rt_raise.o(.text) for __rt_raise + defsig_stak_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_pvfn_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_cppl_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_segv_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_other.o(.text) refers to defsig_general.o(.text) for __default_signal_display + + +============================================================================== + +Removing Unused input sections from the image. + + Removing main.o(.emb_text), (8 bytes). + Removing stm32f0xx_it.o(.emb_text), (8 bytes). + Removing system_stm32f0xx.o(.emb_text), (8 bytes). + Removing led.o(.emb_text), (8 bytes). + Removing usart1.o(.emb_text), (8 bytes). + Removing usart1_api.o(.emb_text), (8 bytes). + Removing usart1_api.o(.text), (32 bytes). + Removing usart1_api.o(.constdata), (71 bytes). + Removing usart1_api.o(.data), (8 bytes). + Removing delay.o(.emb_text), (8 bytes). + Removing stm32f0xx_gpio.o(.emb_text), (8 bytes). + Removing stm32f0xx_rcc.o(.emb_text), (8 bytes). + Removing stm32f0xx_misc.o(.emb_text), (8 bytes). + Removing stm32f0xx_usart.o(.emb_text), (8 bytes). + +14 unused section(s) (total 199 bytes) removed from the image. + +============================================================================== + +Image Symbol Table + + Local Symbols + + Symbol Name Value Ov Type Size Object(Section) + + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit3.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit2.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit1.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardshut.o ABSOLUTE + ../clib/angel/handlers.s 0x00000000 Number 0 __scatter_zi.o ABSOLUTE + ../clib/angel/handlers.s 0x00000000 Number 0 __scatter_copy.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 rtentry2.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 rtentry4.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 rtexit2.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 rtentry.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 rtexit.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 aeabi_idiv0.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 rt_locale.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 rt_div0.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 rt_locale_intlibspace.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 rt_ctype_table.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 rt_raise.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 aeabi_idiv0_sigfpe.o ABSOLUTE + ../clib/angel/scatterp.s 0x00000000 Number 0 __scatter.o ABSOLUTE + ../clib/angel/startup.s 0x00000000 Number 0 __main.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 indicate_semi.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 libspace.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 sys_stackheap_outer.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 use_no_semi.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 tempstk.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 use_no_semi_2.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_command.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_wrch.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 no_argv.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 argv_veneer.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 _get_argv_nomalloc.o ABSOLUTE + ../clib/bigflt.c 0x00000000 Number 0 bigflt0.o ABSOLUTE + ../clib/btod.c 0x00000000 Number 0 btod.o ABSOLUTE + ../clib/division.c 0x00000000 Number 0 lludiv10.o ABSOLUTE + ../clib/division.c 0x00000000 Number 0 rtudiv10.o ABSOLUTE + ../clib/division.s 0x00000000 Number 0 aeabi_sdiv_div0.o ABSOLUTE + ../clib/division.s 0x00000000 Number 0 aeabi_sdiv.o ABSOLUTE + ../clib/heapalloc.c 0x00000000 Number 0 hrguard.o ABSOLUTE + ../clib/heapaux.c 0x00000000 Number 0 heapauxi.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libshutdown.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libinit2.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libinit.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libshutdown2.o ABSOLUTE + ../clib/locale.c 0x00000000 Number 0 _wcrtomb.o ABSOLUTE + ../clib/locale.s 0x00000000 Number 0 lc_ctype_c.o ABSOLUTE + ../clib/locale.s 0x00000000 Number 0 lc_numeric_c.o ABSOLUTE + ../clib/misc.s 0x00000000 Number 0 printf_stubs.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_intcommon.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_wp.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_hex_ll.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_flags_ss.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_ss.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_flags.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_hex_int_ll_ptr.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_hex_ll_ptr.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_flags_wp.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_hex_int_ptr.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_hex_ptr.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_hex_int_ll.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_ss_wp.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_nopercent.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_fp_infnan.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_flags_ss_wp.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 printf.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __2printf.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_hex_int.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_char_common.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_char.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_pad.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_truncate.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_str.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_dec.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_charcount.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_char_file.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_fp_dec.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_wctomb.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_longlong_dec.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_oct_ll.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_oct_int.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_oct_int_ll.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_fp_hex.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_wchar.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 noretval__2printf.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_s.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_n.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_x.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_p.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_o.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_i.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_d.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_u.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_f.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_e.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_g.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_percent.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_lli.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_lld.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_ll.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_l.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_lc.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_ls.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_llo.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_llx.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_llu.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_percent_end.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_c.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_a.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtred_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtmem_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtmem_outer.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_cppl_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtmem_formal.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_stak_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_other.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_pvfn_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_fpe_outer.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_fpe_formal.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_exit.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_fpe_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_segv_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 __raise.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_general.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_abrt_inner.o ABSOLUTE + ../clib/signal.s 0x00000000 Number 0 defsig.o ABSOLUTE + ../clib/stdio.c 0x00000000 Number 0 ferror_locked.o ABSOLUTE + ../clib/stdio.c 0x00000000 Number 0 ferror.o ABSOLUTE + ../clib/stdlib.c 0x00000000 Number 0 exit.o ABSOLUTE + ../clib/string.c 0x00000000 Number 0 strcmp.o ABSOLUTE + ../fplib/cfplib/fpinit.c 0x00000000 Number 0 fpinit.o ABSOLUTE + ../fplib/cfplib/ieee_status.c 0x00000000 Number 0 ieee_status.o ABSOLUTE + ../fplib/printf1.s 0x00000000 Number 0 printf1.o ABSOLUTE + ../fplib/printf2.s 0x00000000 Number 0 printf2.o ABSOLUTE + ../fplib/printf2a.s 0x00000000 Number 0 printf2a.o ABSOLUTE + ../fplib/printf2b.s 0x00000000 Number 0 printf2b.o ABSOLUTE + ../fplib/usenofp.s 0x00000000 Number 0 usenofp.o ABSOLUTE + ../mathlib/fpclassify.c 0x00000000 Number 0 fpclassify.o ABSOLUTE + ..\CORE\startup_stm32f0xx.s 0x00000000 Number 0 startup_stm32f0xx.o ABSOLUTE + ..\HARDWARE\USART1.c 0x00000000 Number 0 usart1.o ABSOLUTE + ..\HARDWARE\USART1_API.c 0x00000000 Number 0 usart1_api.o ABSOLUTE + ..\HARDWARE\led.c 0x00000000 Number 0 led.o ABSOLUTE + ..\STM32F03x_FWLib\src\stm32f0xx_gpio.c 0x00000000 Number 0 stm32f0xx_gpio.o ABSOLUTE + ..\STM32F03x_FWLib\src\stm32f0xx_misc.c 0x00000000 Number 0 stm32f0xx_misc.o ABSOLUTE + ..\STM32F03x_FWLib\src\stm32f0xx_rcc.c 0x00000000 Number 0 stm32f0xx_rcc.o ABSOLUTE + ..\STM32F03x_FWLib\src\stm32f0xx_usart.c 0x00000000 Number 0 stm32f0xx_usart.o ABSOLUTE + ..\SYSTEM\delay.c 0x00000000 Number 0 delay.o ABSOLUTE + ..\\HARDWARE\\USART1.c 0x00000000 Number 0 usart1.o ABSOLUTE + ..\\HARDWARE\\USART1_API.c 0x00000000 Number 0 usart1_api.o ABSOLUTE + ..\\HARDWARE\\led.c 0x00000000 Number 0 led.o ABSOLUTE + ..\\STM32F03x_FWLib\\src\\stm32f0xx_gpio.c 0x00000000 Number 0 stm32f0xx_gpio.o ABSOLUTE + ..\\STM32F03x_FWLib\\src\\stm32f0xx_misc.c 0x00000000 Number 0 stm32f0xx_misc.o ABSOLUTE + ..\\STM32F03x_FWLib\\src\\stm32f0xx_rcc.c 0x00000000 Number 0 stm32f0xx_rcc.o ABSOLUTE + ..\\STM32F03x_FWLib\\src\\stm32f0xx_usart.c 0x00000000 Number 0 stm32f0xx_usart.o ABSOLUTE + ..\\SYSTEM\\delay.c 0x00000000 Number 0 delay.o ABSOLUTE + dc.s 0x00000000 Number 0 dc.o ABSOLUTE + main.c 0x00000000 Number 0 main.o ABSOLUTE + main.c 0x00000000 Number 0 main.o ABSOLUTE + stm32f0xx_it.c 0x00000000 Number 0 stm32f0xx_it.o ABSOLUTE + stm32f0xx_it.c 0x00000000 Number 0 stm32f0xx_it.o ABSOLUTE + system_stm32f0xx.c 0x00000000 Number 0 system_stm32f0xx.o ABSOLUTE + system_stm32f0xx.c 0x00000000 Number 0 system_stm32f0xx.o ABSOLUTE + RESET 0x08000000 Section 192 startup_stm32f0xx.o(RESET) + !!!main 0x080000c0 Section 8 __main.o(!!!main) + !!!scatter 0x080000c8 Section 60 __scatter.o(!!!scatter) + !!handler_copy 0x08000104 Section 26 __scatter_copy.o(!!handler_copy) + !!handler_zi 0x08000120 Section 28 __scatter_zi.o(!!handler_zi) + .ARM.Collect$$_printf_percent$$00000000 0x0800013c Section 2 _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) + .ARM.Collect$$_printf_percent$$00000017 0x0800013e Section 4 _printf_percent_end.o(.ARM.Collect$$_printf_percent$$00000017) + .ARM.Collect$$libinit$$00000000 0x08000142 Section 2 libinit.o(.ARM.Collect$$libinit$$00000000) + .ARM.Collect$$libinit$$00000001 0x08000144 Section 4 libinit2.o(.ARM.Collect$$libinit$$00000001) + .ARM.Collect$$libinit$$00000008 0x08000148 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000008) + .ARM.Collect$$libinit$$0000000A 0x08000148 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000000A) + .ARM.Collect$$libinit$$0000000C 0x08000148 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000000C) + .ARM.Collect$$libinit$$0000000F 0x08000148 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000000F) + .ARM.Collect$$libinit$$00000011 0x08000148 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000011) + .ARM.Collect$$libinit$$00000013 0x08000148 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000013) + .ARM.Collect$$libinit$$00000015 0x08000148 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000015) + .ARM.Collect$$libinit$$00000017 0x08000148 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000017) + .ARM.Collect$$libinit$$00000019 0x08000148 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000019) + .ARM.Collect$$libinit$$0000001B 0x08000148 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000001B) + .ARM.Collect$$libinit$$0000001D 0x08000148 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000001D) + .ARM.Collect$$libinit$$0000001F 0x08000148 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000001F) + .ARM.Collect$$libinit$$00000021 0x08000148 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000021) + .ARM.Collect$$libinit$$00000023 0x08000148 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000023) + .ARM.Collect$$libinit$$0000002A 0x08000148 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000002A) + .ARM.Collect$$libinit$$0000002C 0x08000148 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000002C) + .ARM.Collect$$libinit$$0000002E 0x08000148 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000002E) + .ARM.Collect$$libinit$$00000030 0x08000148 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000030) + .ARM.Collect$$libinit$$00000031 0x08000148 Section 2 libinit2.o(.ARM.Collect$$libinit$$00000031) + .ARM.Collect$$libshutdown$$00000000 0x0800014a Section 2 libshutdown.o(.ARM.Collect$$libshutdown$$00000000) + .ARM.Collect$$libshutdown$$00000003 0x0800014c Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000003) + .ARM.Collect$$libshutdown$$00000006 0x0800014c Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000006) + .ARM.Collect$$libshutdown$$00000009 0x0800014c Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000009) + .ARM.Collect$$libshutdown$$0000000B 0x0800014c Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000B) + .ARM.Collect$$libshutdown$$0000000E 0x0800014c Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000E) + .ARM.Collect$$libshutdown$$0000000F 0x0800014c Section 2 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F) + .ARM.Collect$$rtentry$$00000000 0x0800014e Section 0 rtentry.o(.ARM.Collect$$rtentry$$00000000) + .ARM.Collect$$rtentry$$00000002 0x0800014e Section 0 rtentry2.o(.ARM.Collect$$rtentry$$00000002) + .ARM.Collect$$rtentry$$00000004 0x0800014e Section 6 rtentry4.o(.ARM.Collect$$rtentry$$00000004) + .ARM.Collect$$rtentry$$00000009 0x08000154 Section 0 rtentry2.o(.ARM.Collect$$rtentry$$00000009) + .ARM.Collect$$rtentry$$0000000A 0x08000154 Section 4 rtentry2.o(.ARM.Collect$$rtentry$$0000000A) + .ARM.Collect$$rtentry$$0000000C 0x08000158 Section 0 rtentry2.o(.ARM.Collect$$rtentry$$0000000C) + .ARM.Collect$$rtentry$$0000000D 0x08000158 Section 8 rtentry2.o(.ARM.Collect$$rtentry$$0000000D) + .ARM.Collect$$rtexit$$00000000 0x08000160 Section 2 rtexit.o(.ARM.Collect$$rtexit$$00000000) + .ARM.Collect$$rtexit$$00000002 0x08000162 Section 0 rtexit2.o(.ARM.Collect$$rtexit$$00000002) + .ARM.Collect$$rtexit$$00000003 0x08000162 Section 4 rtexit2.o(.ARM.Collect$$rtexit$$00000003) + .ARM.Collect$$rtexit$$00000004 0x08000166 Section 6 rtexit2.o(.ARM.Collect$$rtexit$$00000004) + .text 0x0800016c Section 0 main.o(.text) + .text 0x080001bc Section 0 stm32f0xx_it.o(.text) + .text 0x080001c8 Section 0 system_stm32f0xx.o(.text) + SetSysClock 0x080001c9 Thumb Code 202 system_stm32f0xx.o(.text) + .text 0x080003bc Section 56 startup_stm32f0xx.o(.text) + .text 0x080003f4 Section 0 led.o(.text) + .text 0x08000420 Section 0 usart1.o(.text) + .text 0x08000500 Section 0 delay.o(.text) + .text 0x080005cc Section 0 stm32f0xx_gpio.o(.text) + .text 0x080007b8 Section 0 stm32f0xx_rcc.o(.text) + .text 0x08000dac Section 0 stm32f0xx_misc.o(.text) + .text 0x08000e60 Section 0 stm32f0xx_usart.o(.text) + .text 0x080013ce Section 2 use_no_semi_2.o(.text) + .text 0x080013d0 Section 0 __2printf.o(.text) + .text 0x080013ec Section 346 aeabi_sdiv.o(.text) + .text 0x08001546 Section 0 heapauxi.o(.text) + .text 0x0800154c Section 2 use_no_semi.o(.text) + .text 0x08001550 Section 0 _printf_char_file.o(.text) + .text 0x08001578 Section 0 __printf_flags_ss_wp.o(.text) + .text 0x08001700 Section 0 _printf_char_common.o(.text) + _printf_input_char 0x08001701 Thumb Code 10 _printf_char_common.o(.text) + .text 0x08001730 Section 0 ferror.o(.text) + .text 0x08001738 Section 62 sys_stackheap_outer.o(.text) + .text 0x08001776 Section 0 exit.o(.text) + .text 0x08001784 Section 8 libspace.o(.text) + i._is_digit 0x0800178c Section 0 __printf_wp.o(i._is_digit) + .constdata 0x0800179a Section 17 __printf_flags_ss_wp.o(.constdata) + maptable 0x0800179a Data 17 __printf_flags_ss_wp.o(.constdata) + .data 0x20000000 Section 20 system_stm32f0xx.o(.data) + .data 0x20000014 Section 4 usart1.o(.data) + .data 0x20000018 Section 4 delay.o(.data) + fac_us 0x20000018 Data 1 delay.o(.data) + fac_ms 0x2000001a Data 2 delay.o(.data) + .data 0x2000001c Section 16 stm32f0xx_rcc.o(.data) + APBAHBPrescTable 0x2000001c Data 16 stm32f0xx_rcc.o(.data) + .bss 0x2000002c Section 96 libspace.o(.bss) + HEAP 0x20000090 Section 512 startup_stm32f0xx.o(HEAP) + Heap_Mem 0x20000090 Data 512 startup_stm32f0xx.o(HEAP) + STACK 0x20000290 Section 1024 startup_stm32f0xx.o(STACK) + Stack_Mem 0x20000290 Data 1024 startup_stm32f0xx.o(STACK) + __initial_sp 0x20000690 Data 0 startup_stm32f0xx.o(STACK) + + Global Symbols + + Symbol Name Value Ov Type Size Object(Section) + + BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OTIME$ROPI$IEEEJ$EBA8$UX$STANDARDLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE + __ARM_use_no_argv 0x00000000 Number 0 main.o ABSOLUTE + _printf_flags 0x00000000 Number 0 printf_stubs.o ABSOLUTE + _printf_return_value 0x00000000 Number 0 printf_stubs.o ABSOLUTE + _printf_sizespec 0x00000000 Number 0 printf_stubs.o ABSOLUTE + _printf_widthprec 0x00000000 Number 0 printf_stubs.o ABSOLUTE + __ARM_exceptions_init - Undefined Weak Reference + __alloca_initialize - Undefined Weak Reference + __cpp_initialize__aeabi_ - Undefined Weak Reference + __cxa_finalize - Undefined Weak Reference + __sigvec_lookup - Undefined Weak Reference + _atexit_init - Undefined Weak Reference + _call_atexit_fns - Undefined Weak Reference + _clock_init - Undefined Weak Reference + _fp_trap_init - Undefined Weak Reference + _fp_trap_shutdown - Undefined Weak Reference + _get_lc_collate - Undefined Weak Reference + _get_lc_monetary - Undefined Weak Reference + _get_lc_time - Undefined Weak Reference + _getenv_init - Undefined Weak Reference + _handle_redirection - Undefined Weak Reference + _init_alloc - Undefined Weak Reference + _init_user_alloc - Undefined Weak Reference + _initio - Undefined Weak Reference + _mutex_acquire - Undefined Weak Reference + _mutex_release - Undefined Weak Reference + _printf_mbtowc - Undefined Weak Reference + _printf_wc - Undefined Weak Reference + _rand_init - Undefined Weak Reference + _signal_finish - Undefined Weak Reference + _signal_init - Undefined Weak Reference + _terminate_alloc - Undefined Weak Reference + _terminate_user_alloc - Undefined Weak Reference + _terminateio - Undefined Weak Reference + __Vectors_Size 0x000000c0 Number 0 startup_stm32f0xx.o ABSOLUTE + __Vectors 0x08000000 Data 4 startup_stm32f0xx.o(RESET) + __Vectors_End 0x080000c0 Data 0 startup_stm32f0xx.o(RESET) + __main 0x080000c1 Thumb Code 8 __main.o(!!!main) + __scatterload 0x080000c9 Thumb Code 0 __scatter.o(!!!scatter) + __scatterload_rt2 0x080000c9 Thumb Code 52 __scatter.o(!!!scatter) + __scatterload_rt2_thumb_only 0x080000c9 Thumb Code 0 __scatter.o(!!!scatter) + __scatterload_null 0x080000d9 Thumb Code 0 __scatter.o(!!!scatter) + __scatterload_copy 0x08000105 Thumb Code 26 __scatter_copy.o(!!handler_copy) + __scatterload_zeroinit 0x08000121 Thumb Code 28 __scatter_zi.o(!!handler_zi) + _printf_percent 0x0800013d Thumb Code 0 _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) + _printf_percent_end 0x0800013f Thumb Code 0 _printf_percent_end.o(.ARM.Collect$$_printf_percent$$00000017) + __rt_lib_init 0x08000143 Thumb Code 0 libinit.o(.ARM.Collect$$libinit$$00000000) + __rt_lib_init_fp_1 0x08000145 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000001) + __rt_lib_init_alloca_1 0x08000149 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000002C) + __rt_lib_init_argv_1 0x08000149 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000002A) + __rt_lib_init_atexit_1 0x08000149 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000019) + __rt_lib_init_clock_1 0x08000149 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000001F) + __rt_lib_init_cpp_1 0x08000149 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000030) + __rt_lib_init_exceptions_1 0x08000149 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000002E) + __rt_lib_init_fp_trap_1 0x08000149 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000001D) + __rt_lib_init_getenv_1 0x08000149 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000021) + __rt_lib_init_heap_1 0x08000149 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000008) + __rt_lib_init_lc_collate_1 0x08000149 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000000F) + __rt_lib_init_lc_ctype_1 0x08000149 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000011) + __rt_lib_init_lc_monetary_1 0x08000149 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000013) + __rt_lib_init_lc_numeric_1 0x08000149 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000015) + __rt_lib_init_lc_time_1 0x08000149 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000017) + __rt_lib_init_rand_1 0x08000149 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000000C) + __rt_lib_init_return 0x08000149 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000031) + __rt_lib_init_signal_1 0x08000149 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000001B) + __rt_lib_init_stdio_1 0x08000149 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000023) + __rt_lib_init_user_alloc_1 0x08000149 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000000A) + __rt_lib_shutdown 0x0800014b Thumb Code 0 libshutdown.o(.ARM.Collect$$libshutdown$$00000000) + __rt_lib_shutdown_fp_trap_1 0x0800014d Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000006) + __rt_lib_shutdown_heap_1 0x0800014d Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000E) + __rt_lib_shutdown_return 0x0800014d Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F) + __rt_lib_shutdown_signal_1 0x0800014d Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000009) + __rt_lib_shutdown_stdio_1 0x0800014d Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000003) + __rt_lib_shutdown_user_alloc_1 0x0800014d Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000B) + __rt_entry 0x0800014f Thumb Code 0 rtentry.o(.ARM.Collect$$rtentry$$00000000) + __rt_entry_presh_1 0x0800014f Thumb Code 0 rtentry2.o(.ARM.Collect$$rtentry$$00000002) + __rt_entry_sh 0x0800014f Thumb Code 0 rtentry4.o(.ARM.Collect$$rtentry$$00000004) + __rt_entry_li 0x08000155 Thumb Code 0 rtentry2.o(.ARM.Collect$$rtentry$$0000000A) + __rt_entry_postsh_1 0x08000155 Thumb Code 0 rtentry2.o(.ARM.Collect$$rtentry$$00000009) + __rt_entry_main 0x08000159 Thumb Code 0 rtentry2.o(.ARM.Collect$$rtentry$$0000000D) + __rt_entry_postli_1 0x08000159 Thumb Code 0 rtentry2.o(.ARM.Collect$$rtentry$$0000000C) + __rt_exit 0x08000161 Thumb Code 0 rtexit.o(.ARM.Collect$$rtexit$$00000000) + __rt_exit_ls 0x08000163 Thumb Code 0 rtexit2.o(.ARM.Collect$$rtexit$$00000003) + __rt_exit_prels_1 0x08000163 Thumb Code 0 rtexit2.o(.ARM.Collect$$rtexit$$00000002) + __rt_exit_exit 0x08000167 Thumb Code 0 rtexit2.o(.ARM.Collect$$rtexit$$00000004) + main 0x0800016d Thumb Code 46 main.o(.text) + NMI_Handler 0x080001bd Thumb Code 2 stm32f0xx_it.o(.text) + HardFault_Handler 0x080001bf Thumb Code 4 stm32f0xx_it.o(.text) + SVC_Handler 0x080001c3 Thumb Code 2 stm32f0xx_it.o(.text) + PendSV_Handler 0x080001c5 Thumb Code 2 stm32f0xx_it.o(.text) + SysTick_Handler 0x080001c7 Thumb Code 2 stm32f0xx_it.o(.text) + SystemInit 0x08000293 Thumb Code 110 system_stm32f0xx.o(.text) + SystemCoreClockUpdate 0x08000301 Thumb Code 154 system_stm32f0xx.o(.text) + Reset_Handler 0x080003bd Thumb Code 8 startup_stm32f0xx.o(.text) + ADC1_COMP_IRQHandler 0x080003cf Thumb Code 0 startup_stm32f0xx.o(.text) + CEC_IRQHandler 0x080003cf Thumb Code 0 startup_stm32f0xx.o(.text) + DMA1_Channel1_IRQHandler 0x080003cf Thumb Code 0 startup_stm32f0xx.o(.text) + DMA1_Channel2_3_IRQHandler 0x080003cf Thumb Code 0 startup_stm32f0xx.o(.text) + DMA1_Channel4_5_IRQHandler 0x080003cf Thumb Code 0 startup_stm32f0xx.o(.text) + EXTI0_1_IRQHandler 0x080003cf Thumb Code 0 startup_stm32f0xx.o(.text) + EXTI2_3_IRQHandler 0x080003cf Thumb Code 0 startup_stm32f0xx.o(.text) + EXTI4_15_IRQHandler 0x080003cf Thumb Code 0 startup_stm32f0xx.o(.text) + FLASH_IRQHandler 0x080003cf Thumb Code 0 startup_stm32f0xx.o(.text) + I2C1_IRQHandler 0x080003cf Thumb Code 0 startup_stm32f0xx.o(.text) + I2C2_IRQHandler 0x080003cf Thumb Code 0 startup_stm32f0xx.o(.text) + PVD_IRQHandler 0x080003cf Thumb Code 0 startup_stm32f0xx.o(.text) + RCC_IRQHandler 0x080003cf Thumb Code 0 startup_stm32f0xx.o(.text) + RTC_IRQHandler 0x080003cf Thumb Code 0 startup_stm32f0xx.o(.text) + SPI1_IRQHandler 0x080003cf Thumb Code 0 startup_stm32f0xx.o(.text) + SPI2_IRQHandler 0x080003cf Thumb Code 0 startup_stm32f0xx.o(.text) + TIM14_IRQHandler 0x080003cf Thumb Code 0 startup_stm32f0xx.o(.text) + TIM15_IRQHandler 0x080003cf Thumb Code 0 startup_stm32f0xx.o(.text) + TIM16_IRQHandler 0x080003cf Thumb Code 0 startup_stm32f0xx.o(.text) + TIM17_IRQHandler 0x080003cf Thumb Code 0 startup_stm32f0xx.o(.text) + TIM1_BRK_UP_TRG_COM_IRQHandler 0x080003cf Thumb Code 0 startup_stm32f0xx.o(.text) + TIM1_CC_IRQHandler 0x080003cf Thumb Code 0 startup_stm32f0xx.o(.text) + TIM2_IRQHandler 0x080003cf Thumb Code 0 startup_stm32f0xx.o(.text) + TIM3_IRQHandler 0x080003cf Thumb Code 0 startup_stm32f0xx.o(.text) + TIM6_DAC_IRQHandler 0x080003cf Thumb Code 0 startup_stm32f0xx.o(.text) + TS_IRQHandler 0x080003cf Thumb Code 0 startup_stm32f0xx.o(.text) + USART2_IRQHandler 0x080003cf Thumb Code 0 startup_stm32f0xx.o(.text) + WWDG_IRQHandler 0x080003cf Thumb Code 0 startup_stm32f0xx.o(.text) + __user_initial_stackheap 0x080003d1 Thumb Code 0 startup_stm32f0xx.o(.text) + LED_Init 0x080003f5 Thumb Code 42 led.o(.text) + _sys_exit 0x08000421 Thumb Code 4 usart1.o(.text) + fputc 0x08000425 Thumb Code 20 usart1.o(.text) + USART1_Init 0x08000439 Thumb Code 144 usart1.o(.text) + USART1_IRQHandler 0x080004c9 Thumb Code 46 usart1.o(.text) + delay_init 0x08000501 Thumb Code 44 delay.o(.text) + delay_us 0x0800052d Thumb Code 70 delay.o(.text) + delay_ms 0x08000573 Thumb Code 70 delay.o(.text) + GPIO_DeInit 0x080005cd Thumb Code 132 stm32f0xx_gpio.o(.text) + GPIO_Init 0x08000651 Thumb Code 144 stm32f0xx_gpio.o(.text) + GPIO_StructInit 0x080006e1 Thumb Code 20 stm32f0xx_gpio.o(.text) + GPIO_PinLockConfig 0x080006f5 Thumb Code 34 stm32f0xx_gpio.o(.text) + GPIO_ReadInputDataBit 0x08000717 Thumb Code 18 stm32f0xx_gpio.o(.text) + GPIO_ReadInputData 0x08000729 Thumb Code 6 stm32f0xx_gpio.o(.text) + GPIO_ReadOutputDataBit 0x0800072f Thumb Code 18 stm32f0xx_gpio.o(.text) + GPIO_ReadOutputData 0x08000741 Thumb Code 6 stm32f0xx_gpio.o(.text) + GPIO_SetBits 0x08000747 Thumb Code 4 stm32f0xx_gpio.o(.text) + GPIO_ResetBits 0x0800074b Thumb Code 4 stm32f0xx_gpio.o(.text) + GPIO_WriteBit 0x0800074f Thumb Code 12 stm32f0xx_gpio.o(.text) + GPIO_Write 0x0800075b Thumb Code 4 stm32f0xx_gpio.o(.text) + GPIO_PinAFConfig 0x0800075f Thumb Code 68 stm32f0xx_gpio.o(.text) + RCC_DeInit 0x080007b9 Thumb Code 104 stm32f0xx_rcc.o(.text) + RCC_HSEConfig 0x08000821 Thumb Code 12 stm32f0xx_rcc.o(.text) + RCC_GetFlagStatus 0x0800082d Thumb Code 66 stm32f0xx_rcc.o(.text) + RCC_WaitForHSEStartUp 0x0800086f Thumb Code 60 stm32f0xx_rcc.o(.text) + RCC_AdjustHSICalibrationValue 0x080008ab Thumb Code 26 stm32f0xx_rcc.o(.text) + RCC_HSICmd 0x080008c5 Thumb Code 32 stm32f0xx_rcc.o(.text) + RCC_AdjustHSI14CalibrationValue 0x080008e5 Thumb Code 26 stm32f0xx_rcc.o(.text) + RCC_HSI14Cmd 0x080008ff Thumb Code 32 stm32f0xx_rcc.o(.text) + RCC_HSI14ADCRequestCmd 0x0800091f Thumb Code 32 stm32f0xx_rcc.o(.text) + RCC_LSEConfig 0x0800093f Thumb Code 34 stm32f0xx_rcc.o(.text) + RCC_LSEDriveConfig 0x08000961 Thumb Code 22 stm32f0xx_rcc.o(.text) + RCC_LSICmd 0x08000977 Thumb Code 32 stm32f0xx_rcc.o(.text) + RCC_PLLConfig 0x08000997 Thumb Code 30 stm32f0xx_rcc.o(.text) + RCC_PLLCmd 0x080009b5 Thumb Code 36 stm32f0xx_rcc.o(.text) + RCC_PREDIV1Config 0x080009d9 Thumb Code 24 stm32f0xx_rcc.o(.text) + RCC_ClockSecuritySystemCmd 0x080009f1 Thumb Code 36 stm32f0xx_rcc.o(.text) + RCC_MCOConfig 0x08000a15 Thumb Code 6 stm32f0xx_rcc.o(.text) + RCC_SYSCLKConfig 0x08000a1b Thumb Code 24 stm32f0xx_rcc.o(.text) + RCC_GetSYSCLKSource 0x08000a33 Thumb Code 10 stm32f0xx_rcc.o(.text) + RCC_HCLKConfig 0x08000a3d Thumb Code 28 stm32f0xx_rcc.o(.text) + RCC_PCLKConfig 0x08000a59 Thumb Code 30 stm32f0xx_rcc.o(.text) + RCC_ADCCLKConfig 0x08000a77 Thumb Code 52 stm32f0xx_rcc.o(.text) + RCC_CECCLKConfig 0x08000aab Thumb Code 22 stm32f0xx_rcc.o(.text) + RCC_I2CCLKConfig 0x08000ac1 Thumb Code 22 stm32f0xx_rcc.o(.text) + RCC_USARTCLKConfig 0x08000ad7 Thumb Code 22 stm32f0xx_rcc.o(.text) + RCC_GetClocksFreq 0x08000aed Thumb Code 368 stm32f0xx_rcc.o(.text) + RCC_RTCCLKConfig 0x08000c5d Thumb Code 12 stm32f0xx_rcc.o(.text) + RCC_RTCCLKCmd 0x08000c69 Thumb Code 36 stm32f0xx_rcc.o(.text) + RCC_BackupResetCmd 0x08000c8d Thumb Code 36 stm32f0xx_rcc.o(.text) + RCC_AHBPeriphClockCmd 0x08000cb1 Thumb Code 28 stm32f0xx_rcc.o(.text) + RCC_APB2PeriphClockCmd 0x08000ccd Thumb Code 28 stm32f0xx_rcc.o(.text) + RCC_APB1PeriphClockCmd 0x08000ce9 Thumb Code 28 stm32f0xx_rcc.o(.text) + RCC_AHBPeriphResetCmd 0x08000d05 Thumb Code 28 stm32f0xx_rcc.o(.text) + RCC_APB2PeriphResetCmd 0x08000d21 Thumb Code 28 stm32f0xx_rcc.o(.text) + RCC_APB1PeriphResetCmd 0x08000d3d Thumb Code 28 stm32f0xx_rcc.o(.text) + RCC_ITConfig 0x08000d59 Thumb Code 28 stm32f0xx_rcc.o(.text) + RCC_ClearFlag 0x08000d75 Thumb Code 16 stm32f0xx_rcc.o(.text) + RCC_GetITStatus 0x08000d85 Thumb Code 20 stm32f0xx_rcc.o(.text) + RCC_ClearITPendingBit 0x08000d99 Thumb Code 6 stm32f0xx_rcc.o(.text) + NVIC_Init 0x08000dad Thumb Code 106 stm32f0xx_misc.o(.text) + NVIC_SystemLPConfig 0x08000e17 Thumb Code 28 stm32f0xx_misc.o(.text) + SysTick_CLKSourceConfig 0x08000e33 Thumb Code 32 stm32f0xx_misc.o(.text) + USART_DeInit 0x08000e61 Thumb Code 56 stm32f0xx_usart.o(.text) + USART_Init 0x08000e99 Thumb Code 230 stm32f0xx_usart.o(.text) + USART_StructInit 0x08000f7f Thumb Code 24 stm32f0xx_usart.o(.text) + USART_ClockInit 0x08000f97 Thumb Code 36 stm32f0xx_usart.o(.text) + USART_ClockStructInit 0x08000fbb Thumb Code 12 stm32f0xx_usart.o(.text) + USART_Cmd 0x08000fc7 Thumb Code 24 stm32f0xx_usart.o(.text) + USART_DirectionModeCmd 0x08000fdf Thumb Code 20 stm32f0xx_usart.o(.text) + USART_OverSampling8Cmd 0x08000ff3 Thumb Code 28 stm32f0xx_usart.o(.text) + USART_OneBitMethodCmd 0x0800100f Thumb Code 28 stm32f0xx_usart.o(.text) + USART_MSBFirstCmd 0x0800102b Thumb Code 28 stm32f0xx_usart.o(.text) + USART_DataInvCmd 0x08001047 Thumb Code 28 stm32f0xx_usart.o(.text) + USART_InvPinCmd 0x08001063 Thumb Code 20 stm32f0xx_usart.o(.text) + USART_SWAPPinCmd 0x08001077 Thumb Code 28 stm32f0xx_usart.o(.text) + USART_ReceiverTimeOutCmd 0x08001093 Thumb Code 28 stm32f0xx_usart.o(.text) + USART_SetReceiverTimeOut 0x080010af Thumb Code 16 stm32f0xx_usart.o(.text) + USART_SetPrescaler 0x080010bf Thumb Code 18 stm32f0xx_usart.o(.text) + USART_STOPModeCmd 0x080010d1 Thumb Code 24 stm32f0xx_usart.o(.text) + USART_StopModeWakeUpSourceConfig 0x080010e9 Thumb Code 18 stm32f0xx_usart.o(.text) + USART_AutoBaudRateCmd 0x080010fb Thumb Code 28 stm32f0xx_usart.o(.text) + USART_AutoBaudRateConfig 0x08001117 Thumb Code 18 stm32f0xx_usart.o(.text) + USART_AutoBaudRateNewRequest 0x08001129 Thumb Code 12 stm32f0xx_usart.o(.text) + USART_SendData 0x08001135 Thumb Code 8 stm32f0xx_usart.o(.text) + USART_ReceiveData 0x0800113d Thumb Code 10 stm32f0xx_usart.o(.text) + USART_SetAddress 0x08001147 Thumb Code 18 stm32f0xx_usart.o(.text) + USART_MuteModeCmd 0x08001159 Thumb Code 28 stm32f0xx_usart.o(.text) + USART_MuteModeWakeUpConfig 0x08001175 Thumb Code 18 stm32f0xx_usart.o(.text) + USART_AddressDetectionConfig 0x08001187 Thumb Code 16 stm32f0xx_usart.o(.text) + USART_LINBreakDetectLengthConfig 0x08001197 Thumb Code 16 stm32f0xx_usart.o(.text) + USART_LINCmd 0x080011a7 Thumb Code 28 stm32f0xx_usart.o(.text) + USART_HalfDuplexCmd 0x080011c3 Thumb Code 24 stm32f0xx_usart.o(.text) + USART_SetGuardTime 0x080011db Thumb Code 16 stm32f0xx_usart.o(.text) + USART_SmartCardCmd 0x080011eb Thumb Code 24 stm32f0xx_usart.o(.text) + USART_SmartCardNACKCmd 0x08001203 Thumb Code 24 stm32f0xx_usart.o(.text) + USART_SetAutoRetryCount 0x0800121b Thumb Code 20 stm32f0xx_usart.o(.text) + USART_SetBlockLength 0x0800122f Thumb Code 30 stm32f0xx_usart.o(.text) + USART_IrDAConfig 0x0800124d Thumb Code 16 stm32f0xx_usart.o(.text) + USART_IrDACmd 0x0800125d Thumb Code 24 stm32f0xx_usart.o(.text) + USART_DECmd 0x08001275 Thumb Code 28 stm32f0xx_usart.o(.text) + USART_DEPolarityConfig 0x08001291 Thumb Code 18 stm32f0xx_usart.o(.text) + USART_SetDEAssertionTime 0x080012a3 Thumb Code 20 stm32f0xx_usart.o(.text) + USART_SetDEDeassertionTime 0x080012b7 Thumb Code 20 stm32f0xx_usart.o(.text) + USART_DMACmd 0x080012cb Thumb Code 20 stm32f0xx_usart.o(.text) + USART_DMAReceptionErrorConfig 0x080012df Thumb Code 18 stm32f0xx_usart.o(.text) + USART_ITConfig 0x080012f1 Thumb Code 66 stm32f0xx_usart.o(.text) + USART_RequestCmd 0x08001333 Thumb Code 20 stm32f0xx_usart.o(.text) + USART_OverrunDetectionConfig 0x08001347 Thumb Code 18 stm32f0xx_usart.o(.text) + USART_GetFlagStatus 0x08001359 Thumb Code 18 stm32f0xx_usart.o(.text) + USART_ClearFlag 0x0800136b Thumb Code 4 stm32f0xx_usart.o(.text) + USART_GetITStatus 0x0800136f Thumb Code 78 stm32f0xx_usart.o(.text) + USART_ClearITPendingBit 0x080013bd Thumb Code 18 stm32f0xx_usart.o(.text) + __use_no_semihosting 0x080013cf Thumb Code 2 use_no_semi_2.o(.text) + __2printf 0x080013d1 Thumb Code 22 __2printf.o(.text) + __aeabi_uidiv 0x080013ed Thumb Code 0 aeabi_sdiv.o(.text) + __aeabi_uidivmod 0x080013ed Thumb Code 20 aeabi_sdiv.o(.text) + __aeabi_idiv 0x08001401 Thumb Code 0 aeabi_sdiv.o(.text) + __aeabi_idivmod 0x08001401 Thumb Code 326 aeabi_sdiv.o(.text) + __use_two_region_memory 0x08001547 Thumb Code 2 heapauxi.o(.text) + __rt_heap_escrow$2region 0x08001549 Thumb Code 2 heapauxi.o(.text) + __rt_heap_expand$2region 0x0800154b Thumb Code 2 heapauxi.o(.text) + __I$use$semihosting 0x0800154d Thumb Code 0 use_no_semi.o(.text) + __use_no_semihosting_swi 0x0800154d Thumb Code 2 use_no_semi.o(.text) + _printf_char_file 0x08001551 Thumb Code 34 _printf_char_file.o(.text) + __printf 0x08001579 Thumb Code 386 __printf_flags_ss_wp.o(.text) + _printf_char_common 0x0800170b Thumb Code 32 _printf_char_common.o(.text) + ferror 0x08001731 Thumb Code 8 ferror.o(.text) + __user_setup_stackheap 0x08001739 Thumb Code 62 sys_stackheap_outer.o(.text) + exit 0x08001777 Thumb Code 12 exit.o(.text) + __user_libspace 0x08001785 Thumb Code 8 libspace.o(.text) + __user_perproc_libspace 0x08001785 Thumb Code 0 libspace.o(.text) + __user_perthread_libspace 0x08001785 Thumb Code 0 libspace.o(.text) + _is_digit 0x0800178d Thumb Code 14 __printf_wp.o(i._is_digit) + Region$$Table$$Base 0x080017ac Number 0 anon$$obj.o(Region$$Table) + Region$$Table$$Limit 0x080017cc Number 0 anon$$obj.o(Region$$Table) + SystemCoreClock 0x20000000 Data 4 system_stm32f0xx.o(.data) + AHBPrescTable 0x20000004 Data 16 system_stm32f0xx.o(.data) + __stdout 0x20000014 Data 4 usart1.o(.data) + __libspace_start 0x2000002c Data 96 libspace.o(.bss) + __temporary_stack_top$libspace 0x2000008c Data 0 libspace.o(.bss) + + + +============================================================================== + +Memory Map of the image + + Image Entry point : 0x080003bd + + Load Region LR_1 (Base: 0x08000000, Size: 0x000017f8, Max: 0xffffffff, ABSOLUTE) + + Execution Region ER_RO (Base: 0x08000000, Size: 0x000017cc, Max: 0xffffffff, ABSOLUTE) + + Base Addr Size Type Attr Idx E Section Name Object + + 0x08000000 0x000000c0 Data RO 110 RESET startup_stm32f0xx.o + 0x080000c0 0x00000008 Code RO 314 * !!!main c_p.l(__main.o) + 0x080000c8 0x0000003c Code RO 630 !!!scatter c_p.l(__scatter.o) + 0x08000104 0x0000001a Code RO 632 !!handler_copy c_p.l(__scatter_copy.o) + 0x0800011e 0x00000002 PAD + 0x08000120 0x0000001c Code RO 634 !!handler_zi c_p.l(__scatter_zi.o) + 0x0800013c 0x00000002 Code RO 402 .ARM.Collect$$_printf_percent$$00000000 c_p.l(_printf_percent.o) + 0x0800013e 0x00000004 Code RO 452 .ARM.Collect$$_printf_percent$$00000017 c_p.l(_printf_percent_end.o) + 0x08000142 0x00000002 Code RO 496 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0x08000148 0x00000000 Code RO 544 .ARM.Collect$$libinit$$0000001D c_p.l(libinit2.o) + 0x08000148 0x00000000 Code RO 546 .ARM.Collect$$libinit$$0000001F c_p.l(libinit2.o) + 0x08000148 0x00000000 Code RO 548 .ARM.Collect$$libinit$$00000021 c_p.l(libinit2.o) + 0x08000148 0x00000000 Code RO 550 .ARM.Collect$$libinit$$00000023 c_p.l(libinit2.o) + 0x08000148 0x00000000 Code RO 554 .ARM.Collect$$libinit$$0000002A c_p.l(libinit2.o) + 0x08000148 0x00000000 Code RO 556 .ARM.Collect$$libinit$$0000002C c_p.l(libinit2.o) + 0x08000148 0x00000000 Code RO 558 .ARM.Collect$$libinit$$0000002E c_p.l(libinit2.o) + 0x08000148 0x00000000 Code RO 560 .ARM.Collect$$libinit$$00000030 c_p.l(libinit2.o) + 0x08000148 0x00000002 Code RO 561 .ARM.Collect$$libinit$$00000031 c_p.l(libinit2.o) + 0x0800014a 0x00000002 Code RO 587 .ARM.Collect$$libshutdown$$00000000 c_p.l(libshutdown.o) + 0x0800014c 0x00000000 Code RO 615 .ARM.Collect$$libshutdown$$00000003 c_p.l(libshutdown2.o) + 0x0800014c 0x00000000 Code RO 618 .ARM.Collect$$libshutdown$$00000006 c_p.l(libshutdown2.o) + 0x0800014c 0x00000000 Code RO 621 .ARM.Collect$$libshutdown$$00000009 c_p.l(libshutdown2.o) + 0x0800014c 0x00000000 Code RO 623 .ARM.Collect$$libshutdown$$0000000B c_p.l(libshutdown2.o) + 0x0800014c 0x00000000 Code RO 626 .ARM.Collect$$libshutdown$$0000000E c_p.l(libshutdown2.o) + 0x0800014c 0x00000002 Code RO 627 .ARM.Collect$$libshutdown$$0000000F c_p.l(libshutdown2.o) + 0x0800014e 0x00000000 Code RO 318 .ARM.Collect$$rtentry$$00000000 c_p.l(rtentry.o) + 0x0800014e 0x00000000 Code RO 421 .ARM.Collect$$rtentry$$00000002 c_p.l(rtentry2.o) + 0x0800014e 0x00000006 Code RO 433 .ARM.Collect$$rtentry$$00000004 c_p.l(rtentry4.o) + 0x08000154 0x00000000 Code RO 423 .ARM.Collect$$rtentry$$00000009 c_p.l(rtentry2.o) + 0x08000154 0x00000004 Code RO 424 .ARM.Collect$$rtentry$$0000000A c_p.l(rtentry2.o) + 0x08000158 0x00000000 Code RO 426 .ARM.Collect$$rtentry$$0000000C c_p.l(rtentry2.o) + 0x08000158 0x00000008 Code RO 427 .ARM.Collect$$rtentry$$0000000D c_p.l(rtentry2.o) + 0x08000160 0x00000002 Code RO 506 .ARM.Collect$$rtexit$$00000000 c_p.l(rtexit.o) + 0x08000162 0x00000000 Code RO 563 .ARM.Collect$$rtexit$$00000002 c_p.l(rtexit2.o) + 0x08000162 0x00000004 Code RO 564 .ARM.Collect$$rtexit$$00000003 c_p.l(rtexit2.o) + 0x08000166 0x00000006 Code RO 565 .ARM.Collect$$rtexit$$00000004 c_p.l(rtexit2.o) + 0x0800016c 0x00000050 Code RO 2 .text main.o + 0x080001bc 0x0000000c Code RO 68 .text stm32f0xx_it.o + 0x080001c8 0x000001f4 Code RO 87 .text system_stm32f0xx.o + 0x080003bc 0x00000038 Code RO 111 * .text startup_stm32f0xx.o + 0x080003f4 0x0000002a Code RO 116 .text led.o + 0x0800041e 0x00000002 PAD + 0x08000420 0x000000e0 Code RO 166 .text usart1.o + 0x08000500 0x000000cc Code RO 212 .text delay.o + 0x080005cc 0x000001ec Code RO 233 .text stm32f0xx_gpio.o + 0x080007b8 0x000005f4 Code RO 249 .text stm32f0xx_rcc.o + 0x08000dac 0x000000b4 Code RO 267 .text stm32f0xx_misc.o + 0x08000e60 0x0000056e Code RO 283 .text stm32f0xx_usart.o + 0x080013ce 0x00000002 Code RO 300 .text c_p.l(use_no_semi_2.o) + 0x080013d0 0x0000001c Code RO 304 .text c_p.l(__2printf.o) + 0x080013ec 0x0000015a Code RO 308 .text c_p.l(aeabi_sdiv.o) + 0x08001546 0x00000006 Code RO 312 .text c_p.l(heapauxi.o) + 0x0800154c 0x00000002 Code RO 316 .text c_p.l(use_no_semi.o) + 0x0800154e 0x00000002 PAD + 0x08001550 0x00000028 Code RO 335 .text c_p.l(_printf_char_file.o) + 0x08001578 0x00000188 Code RO 386 .text c_p.l(__printf_flags_ss_wp.o) + 0x08001700 0x00000030 Code RO 446 .text c_p.l(_printf_char_common.o) + 0x08001730 0x00000008 Code RO 453 .text c_p.l(ferror.o) + 0x08001738 0x0000003e Code RO 461 .text c_p.l(sys_stackheap_outer.o) + 0x08001776 0x0000000c Code RO 485 .text c_p.l(exit.o) + 0x08001782 0x00000002 PAD + 0x08001784 0x00000008 Code RO 502 .text c_p.l(libspace.o) + 0x0800178c 0x0000000e Code RO 379 i._is_digit c_p.l(__printf_wp.o) + 0x0800179a 0x00000011 Data RO 387 .constdata c_p.l(__printf_flags_ss_wp.o) + 0x080017ab 0x00000001 PAD + 0x080017ac 0x00000020 Data RO 628 Region$$Table anon$$obj.o + + + Execution Region ER_RW (Base: 0x20000000, Size: 0x0000002c, Max: 0xffffffff, ABSOLUTE) + + Base Addr Size Type Attr Idx E Section Name Object + + 0x20000000 0x00000014 Data RW 88 .data system_stm32f0xx.o + 0x20000014 0x00000004 Data RW 167 .data usart1.o + 0x20000018 0x00000004 Data RW 213 .data delay.o + 0x2000001c 0x00000010 Data RW 250 .data stm32f0xx_rcc.o + + + Execution Region ER_ZI (Base: 0x2000002c, Size: 0x00000664, Max: 0xffffffff, ABSOLUTE) + + Base Addr Size Type Attr Idx E Section Name Object + + 0x2000002c 0x00000060 Zero RW 503 .bss c_p.l(libspace.o) + 0x2000008c 0x00000004 PAD + 0x20000090 0x00000200 Zero RW 109 HEAP startup_stm32f0xx.o + 0x20000290 0x00000400 Zero RW 108 STACK startup_stm32f0xx.o + + +============================================================================== + +Image component sizes + + + Code (inc. data) RO Data RW Data ZI Data Debug Object Name + + 204 20 0 4 0 1115 delay.o + 42 0 0 0 0 109183 led.o + 80 34 0 0 0 4731 main.o + 56 26 192 0 1536 636 startup_stm32f0xx.o + 492 22 0 0 0 3765 stm32f0xx_gpio.o + 12 0 0 0 0 831 stm32f0xx_it.o + 180 14 0 0 0 1448 stm32f0xx_misc.o + 1524 44 0 16 0 8642 stm32f0xx_rcc.o + 1390 12 0 0 0 12127 stm32f0xx_usart.o + 500 34 0 20 0 1763 system_stm32f0xx.o + 224 10 0 4 0 3018 usart1.o + + ---------------------------------------------------------------------- + 4706 216 224 44 1536 147259 Object Totals + 0 0 32 0 0 0 (incl. Generated) + 2 0 0 0 0 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name + + 28 6 0 0 0 84 __2printf.o + 8 0 0 0 0 68 __main.o + 392 6 17 0 0 76 __printf_flags_ss_wp.o + 14 0 0 0 0 60 __printf_wp.o + 60 8 0 0 0 0 __scatter.o + 26 0 0 0 0 0 __scatter_copy.o + 28 0 0 0 0 0 __scatter_zi.o + 48 6 0 0 0 88 _printf_char_common.o + 40 6 0 0 0 72 _printf_char_file.o + 2 0 0 0 0 0 _printf_percent.o + 4 0 0 0 0 0 _printf_percent_end.o + 346 0 0 0 0 92 aeabi_sdiv.o + 12 0 0 0 0 64 exit.o + 8 0 0 0 0 60 ferror.o + 6 0 0 0 0 136 heapauxi.o + 2 0 0 0 0 0 libinit.o + 6 0 0 0 0 0 libinit2.o + 2 0 0 0 0 0 libshutdown.o + 2 0 0 0 0 0 libshutdown2.o + 8 4 0 0 96 68 libspace.o + 0 0 0 0 0 0 rtentry.o + 12 0 0 0 0 0 rtentry2.o + 6 0 0 0 0 0 rtentry4.o + 2 0 0 0 0 0 rtexit.o + 10 0 0 0 0 0 rtexit2.o + 62 0 0 0 0 80 sys_stackheap_outer.o + 2 0 0 0 0 68 use_no_semi.o + 2 0 0 0 0 68 use_no_semi_2.o + + ---------------------------------------------------------------------- + 1144 36 18 0 100 1084 Library Totals + 6 0 1 0 4 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Name + + 1138 36 17 0 96 1084 c_p.l + + ---------------------------------------------------------------------- + 1144 36 18 0 100 1084 Library Totals + + ---------------------------------------------------------------------- + +============================================================================== + + + Code (inc. data) RO Data RW Data ZI Data Debug + + 5850 252 242 44 1636 147107 Grand Totals + 5850 252 242 44 1636 147107 ELF Image Totals + 5850 252 242 44 0 0 ROM Totals + +============================================================================== + + Total RO Size (Code + RO Data) 6092 ( 5.95kB) + Total RW Size (RW Data + ZI Data) 1680 ( 1.64kB) + Total ROM Size (Code + RO Data + RW Data) 6136 ( 5.99kB) + +============================================================================== + diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/HARDWARE/USART1.c b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/HARDWARE/USART1.c new file mode 100644 index 0000000..8d88f6e --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/HARDWARE/USART1.c @@ -0,0 +1,427 @@ +#include "USART1.h" +typedef unsigned long uint32; + + +/////////////////////////////////////////////////////////////////////////////////////////////////////// +//ڼ֤/ӽJCϵмɴģ +//STM32F030 +//ӽƼ@̲ +//˾վ:www.sun-lcm.com +//Ա꣺https://shop151604432.taobao.com +//ҵ꣺https://sundisplay2008.1688.com +//ҵ֧֣ mobile:13509671256 QQ:3167153224 +//֧֣ QQ:3085638545 +//޸:2015/09/18 +//汾V1.0 +//ȨУؾ +//Copyright(C) ӽƼ޹˾ 2015-2021 +//All rights reserved +//****************************************************************************************************** +//V1.0޸˵ +// +///////////////////////////////////////////////////////////////////////////////////////////////////////// + + + +//´,֧printf,Ҫѡuse MicroLIB +#if 1 +#pragma import(__use_no_semihosting) +//׼Ҫֺ֧ +struct __FILE +{ + int handle; + /* Whatever you require here. If the only file you are using is */ + /* standard output using printf() for debugging, no file handling */ + /* is required. */ +}; +/* FILE is typedef d in stdio.h. */ +FILE __stdout; +//_sys_exit()Աʹðģʽ +void _sys_exit(int x) +{ + x = x; +} +//ضfputc +int fputc(int ch, FILE *f) +{ + while(!((USART1->ISR)&(1<<7))){} + USART1->TDR=ch; + return (ch); +} + + + + +#endif + +#define u8 unsigned char + +///////////////////////////////////////////////////////////////////////////////////// +//STM32ڳʼ +//1.߷ʽ TX-->TX RX->RX +//2.ڳʼ ģĬΪ 115200 8λλ 1ʼλ 1ֹͣλ żУ +//3.baudʹõIJ +///////////////////////////////////////////////////////////////////////////////////// + +/* USARTʼ */ +void USART1_Init(uint32_t baud) +{ + GPIO_InitTypeDef GPIO_InitStructure; + USART_InitTypeDef USART_InitStructure; + NVIC_InitTypeDef NVIC_InitStruct; + + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE); //ʹGPIOAʱ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);//ʹUSARTʱ + /* USART1Ķ˿ */ + GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_1);//PA9ɵڶ TX + GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_1);//PA10ɵڶ RX + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9 | GPIO_Pin_10; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + + /* USART1Ļ */ + USART_InitStructure.USART_BaudRate = baud; // + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + + USART_Init(USART1, &USART_InitStructure); + USART_ITConfig(USART1,USART_IT_RXNE,ENABLE); //ʹܽж + USART_Cmd(USART1, ENABLE); //ʹUSART1 + + /* USART1NVICж */ + NVIC_InitStruct.NVIC_IRQChannel = USART1_IRQn; + NVIC_InitStruct.NVIC_IRQChannelPriority = 0x02; + NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStruct); + + //_KEY_STEP PA2 + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + + +} + +///////////////////////////////////////////////////////////////////////////////////// +//ȡַ +//1.߷ʽ TX-->TX RX->RX +//2.ڳʼ ģĬΪ 115200 8λλ 1ʼλ 1ֹͣλ żУ +//3.յַظһ㺯 +////////////////////////////////////////////////////////////////////////////////////// + +int UartGet (void) { + + while (!(USART1->ISR & USART_FLAG_RXNE)); + + return ((int)(USART1->TDR & 0x1FF)); +} + +extern u8 rx_flag_finished; +extern u8 RX_BUF[]; +extern u8 rx_count; +extern u8 ok; + +///////////////////////////////////////////////////////////////////////////////////// +//ȡ״̬ +//1.߷ʽ TX-->TX RX->RX +//2.ڳʼ ģĬΪ 115200 8λλ 1ʼλ 1ֹͣλ żУ +//3.жϷʽ"OK\r\n" +//4.λokȫֱֱokΪ0x0fȡ"OK\r\n"˳ѭ +////////////////////////////////////////////////////////////////////////////////////// +void CheckBusy(void) +{ + while(1) + { + if(ok==0x0f) + break; + } + + ok=0; +} + + void get_var(unsigned char *val) + { + for(;;) + { + if((RX_BUF[0]=='V')&&(RX_BUF[1]=='A')&&(RX_BUF[2]=='R')) + { + RX_BUF[0]=0; + RX_BUF[1]=0; + RX_BUF[2]=0; + val[0]=RX_BUF[3]; + val[1]=RX_BUF[4]; + val[2]=RX_BUF[5]; + val[3]=RX_BUF[6]; + rx_flag_finished=0; + rx_count=0; + break; + } + } + + } + + + +char rch[5][3]; //xxx:xxx,xxx,xxx,xxx +u8 i=0; +u8 p=0;// +u8 cmd=0; //==1 +u8 cmdok=0; //==1 +u8 ok=0x00; + +///////////////////////////////////////////////////////////////////////////////////// +//ģ鷢ͻַ +//1.߷ʽ TX-->TX RX->RX +//2.ڳʼ ģĬΪ 115200 8λλ 1ʼλ 1ֹͣλ żУ +//3.λokȫֱͳȡVARASCII ַ +////////////////////////////////////////////////////////////////////////////////////// + +void getch(u8 c) +{ + if (c=='{') + { i=0; + cmd=1; + p=0; + } + else if(c=='}') + { cmd=0; + cmdok=1; + } + else if((c==':')||(c==',')) + { + p++; + i=0; + } + else if (cmd==1) + { + if (i<3) rch[p][i]=c; + i++; + } + else if(c=='O') + { + ok=(ok&0x00)|(0x01); + } + else if(c=='K') + { + ok=(ok&0x0d)|(0x02); + } + else if(c=='\r') + { + ok=(ok&0x0b)|(0x04); + } + else if(c=='\n') + { + ok=(ok&0x07)|(0x08); + } + +} + +unsigned char val[4]; + +///////////////////////////////////////////////////////////////////////////////////// +//VARν +//1.߷ʽ TX-->TX RX->RX +//2.ڳʼ ģĬΪ 115200 8λλ 1ʼλ 1ֹͣλ żУ +//3.VARASCII ַתΪvalֵظһ㺯 +////////////////////////////////////////////////////////////////////////////////////// +unsigned char GetValue(void) +{ + unsigned char m,n; + while(1) + { + if(cmdok==1) + { + if ((rch[0][0]=='V')&&(rch[0][1]=='A')&&(rch[0][2]=='R')) + { + /*һֽ*/ + if ((rch[1][2]>=0x30) && (rch[1][2]<=0x39))//100ϵ + { + val[0]=(rch[1][0]-0x30)*100+(rch[1][1]-0x30)*10+(rch[1][2]-0x30); + + } + else if((rch[1][1]>=0x30) && (rch[1][1]<=0x39)) //10ϵ + { + val[0]=(rch[1][0]-0x30)*10+(rch[1][1]-0x30); + } + else if((rch[1][0]>=0x30) && (rch[1][0]<=0x39)) + { + val[0]=(rch[1][0]-0x30); + } + /*ڶֽ*/ + if ((rch[2][2]>=0x30) && (rch[2][2]<=0x39))//100ϵ + { + val[1]=(rch[2][0]-0x30)*100+(rch[2][1]-0x30)*10+(rch[2][2]-0x30); + } + else if((rch[2][1]>=0x30) && (rch[2][1]<=0x39)) //10ϵ + { + val[1]=(rch[2][0]-0x30)*10+(rch[2][1]-0x30); + } + else if((rch[2][0]>=0x30) && (rch[2][0]<=0x39)) + { + val[1]=(rch[2][0]-0x30); + } + + /*ֽ*/ + if ((rch[3][2]>=0x30) && (rch[3][2]<=0x39))//100ϵ + { + val[2]=(rch[3][0]-0x30)*100+(rch[3][1]-0x30)*10+(rch[3][2]-0x30); + + } + + else if((rch[3][1]>=0x30) && (rch[3][1]<=0x39)) //10ϵ + { + val[2]=(rch[3][0]-0x30)*10+(rch[3][1]-0x30); + } + else if((rch[3][0]>=0x30) && (rch[3][0]<=0x39)) + { + val[2]=(rch[3][0]-0x30); + } + /*ĸֽ*/ + if ((rch[4][2]>=0x30) && (rch[4][2]<=0x39))//100ϵ + { + val[3]=(rch[4][0]-0x30)*100+(rch[4][1]-0x30)*10+(rch[4][2]-0x30); + + } + + else if((rch[4][1]>=0x30) && (rch[4][1]<=0x39)) //10ϵ + { + val[3]=(rch[4][0]-0x30)*10+(rch[4][1]-0x30); + } + else if((rch[4][0]>=0x30) && (rch[4][0]<=0x39)) + { + val[3]=(rch[4][0]-0x30); + } + + for(n=0;n<5;n++) + for(m=0;m<3;m++) + rch[n][m]=0; + cmdok=0; + break; + + + } + // cmdok=0; + + + + } + +} +} + +///////////////////////////////////////////////////////////////////////////////////// +//ڷݺ +//1.߷ʽ TX-->TX RX->RX +//2.ڳʼ ģĬΪ 115200 8λλ 1ʼλ 1ֹͣλ żУ +//3.ֱַַ +//4. databuf ΪҪַĵַ +////////////////////////////////////////////////////////////////////////////////////// + +void UartSend(char * databuf) +{ + u8 i=0; + while (1) + { + if ((*databuf)!=0)//ֱݶ + { + USART_SendData(USART1, *databuf); //һֽ + while(USART_GetFlagStatus(USART1, USART_FLAG_TXE) == RESET){}; // + databuf++;//i++; + } + else return; + } +} + +///////////////////////////////////////////////////////////////////////////////////// +//ڽжϺ +//1.߷ʽ TX-->TX RX->RX +//2.ڳʼ ģĬΪ 115200 8λλ 1ʼλ 1ֹͣλ żУ +//3.ȡÿһַн +////////////////////////////////////////////////////////////////////////////////////// + +u8 RX_BUF[4]; +u8 rx_flag_finished=0; +u8 rx_count=0; +void USART1_IRQHandler(void) //??1?????? +{ + u8 Res=1; + if(USART_GetITStatus(USART1, USART_IT_RXNE) != RESET) //????(?????????0x0d 0x0a??) + { + Res =USART_ReceiveData(USART1);//(USART1->DR); //???????? + getch(Res); +// if(rx_flag_finished!=0xc0)//????? +// { +// if(rx_flag_finished&0x40)//????0x0d +// { +// if(Res==0x0a) +// { +// rx_flag_finished|=0x80; //????? rx_flag_finished=0xc0 +// RX_BUF[rx_count]='\0'; //?????????????? +// } +// else +// { +// rx_flag_finished=0;//????,???? +// rx_count=0; +// } +// } +// else //????0X0D +// { +// if(Res!=0x0d) +// { +// RX_BUF[rx_count++]=Res ; +// } +// else +// { +// rx_flag_finished|=0x40; +// } +// } +// } + + + +// if(Res=='O') +// busy_flag=0; +// else +// busy_flag=1; + } +} + + + + + + + + +#if 0 + + + + +//============================================================================= +//ļƣ +//ܸҪUSART1жϺ +//˵ +//أ +//============================================================================= +void USART1_IRQHandler(void) +{ + if(USART_GetITStatus(USART1, USART_IT_RXNE) != RESET) + { + USART_SendData(USART1,USART_ReceiveData(USART1)); + while (USART_GetFlagStatus(USART1,USART_FLAG_TXE) == RESET); + } + +} + +#endif diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/HARDWARE/USART1.h b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/HARDWARE/USART1.h new file mode 100644 index 0000000..dfe58f8 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/HARDWARE/USART1.h @@ -0,0 +1,11 @@ + +#ifndef _USART1_H +#define _USART1_H + +#include "stm32f0xx.h" +#include + + +void USART1_Init(uint32_t baud); + +#endif diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/HARDWARE/USART1_API.c b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/HARDWARE/USART1_API.c new file mode 100644 index 0000000..d11fff2 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/HARDWARE/USART1_API.c @@ -0,0 +1,41 @@ +#include "USART1.h" + +#define KEY1_COMM1 {0xEB,0x4B,0x07,0xF8,0xC0,0x88,0x22,0x88,0x66,0x2A,0x2D,0x41} + +const unsigned char Key1Com1[] = {0xEB,0x4B,0x07,0xF8,0xC0,0x88,0x22,0x88,0x66,0x2A,0x2D,0x41}; +const unsigned char Key1Com2[] = {0xEB,0x4B,0x07,0xF8,0xB9,0x3B,0x48,0x33,0x65,0xDD,0x4B,0x6E,0x3A,0x7F,0x71,0x10,0x31,0x87,0x4A}; + +const unsigned char KeyComm[2][20] = { + {0xEB,0x4B,0x07,0xF8,0xC0,0x88,0x22,0x88,0x66,0x2A,0x2D,0x41} +}; + +typedef struct Command{ + unsigned char KeyCom1; + unsigned char KeyCom2; +}sKeyCommand_t; + + +//sKeyCommand_t sKeyCommand[] = { + //(0xEB,0x4B,0x07,0xF8,0xC0,0x88,0x22,0x88,0x66,0x2A,0x2D,0x41,} +//}; + +typedef struct keyPross{ + unsigned char KeyTime; + unsigned char KeyVal; + void (*UartPrintf)(unsigned char*); +}sKeyPross_t; + +sKeyPross_t sKeyPross; + +void OutputCommand(unsigned char KeyVal, unsigned char KeyTime) +{ + +} +void Init_API(void) +{ + sKeyPross.UartPrintf = printf; +} +void OutputCommand_Uart1(sKeyPross_t sKeyPross) +{ + sKeyPross.UartPrintf("123"); +} diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/HARDWARE/led.c b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/HARDWARE/led.c new file mode 100644 index 0000000..ad41960 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/HARDWARE/led.c @@ -0,0 +1,39 @@ +#include "LED.h" + +#if 0 + +void LED_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + RCC_AHBPeriphClockCmd(LED_GPIO_CLK, ENABLE); + + GPIO_InitStructure.GPIO_Pin = LED_PIN; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_Init(LED_PORT, &GPIO_InitStructure); +} + +/**************************************************** +ܣLED + + + עô˺ǰҪLED.h޸ĺ궨LED +****************************************************/ +void LED_ON(void) +{ + GPIO_ResetBits(LED_PORT, LED_PIN); +} + +/**************************************************** +ܣLED + + + עô˺ǰҪLED.h޸ĺ궨LED +****************************************************/ +void LED_OFF(void) +{ + GPIO_SetBits(LED_PORT, LED_PIN); +} +#endif \ No newline at end of file diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/HARDWARE/led.h b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/HARDWARE/led.h new file mode 100644 index 0000000..477c9b7 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/HARDWARE/led.h @@ -0,0 +1,29 @@ +#ifndef __LED_H +#define __LED_H + +//=================================================================================================== +/* : + : + ע + ӽƼ޹˾ 2008-2020 ȨУؾ + ˾վ www.sun-lcm.com + Ավ https://shop151604432.taobao.com/index.htm?spm=a1z10.5-c.w5002-14603162597.2.4c2619d6w9oYgh + ֧:QQQ:3085638545 + */ +//==================================================================================================== + + + + +#include "stm32f0xx.h" + + +#define LED_GPIO_CLK RCC_AHBPeriph_GPIOA +#define LED_PORT GPIOA +#define LED_PIN GPIO_Pin_4 + +void LED_Init(void); +void LED_ON(void); +void LED_OFF(void); + +#endif diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/HARDWARE/startup_stm32f0xx.lst b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/HARDWARE/startup_stm32f0xx.lst new file mode 100644 index 0000000..7f25e94 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/HARDWARE/startup_stm32f0xx.lst @@ -0,0 +1,936 @@ + + + +ARM Macro Assembler Page 1 + + + 1 00000000 ;******************** (C) COPYRIGHT 2012 STMicroelectron + ics ******************** + 2 00000000 ;* File Name : startup_stm32f0xx.s + 3 00000000 ;* Author : MCD Application Team + 4 00000000 ;* Version : V1.0.0 + 5 00000000 ;* Date : 23-March-2012 + 6 00000000 ;* Description : STM32F0xx Devices vector table f + or MDK-ARM toolchain. + 7 00000000 ;* This module performs: + 8 00000000 ;* - Set the initial SP + 9 00000000 ;* - Set the initial PC == Reset_Ha + ndler + 10 00000000 ;* - Set the vector table entries w + ith the exceptions ISR address + 11 00000000 ;* - Branches to __main in the C li + brary (which eventually + 12 00000000 ;* calls main()). + 13 00000000 ;* After Reset the CortexM0 process + or is in Thread mode, + 14 00000000 ;* priority is Privileged, and the + Stack is set to Main. + 15 00000000 ;* <<< Use Configuration Wizard in Context Menu >>> + 16 00000000 ;******************************************************* + ************************ + 17 00000000 ; @attention + 18 00000000 ; + 19 00000000 ; Licensed under MCD-ST Liberty SW License Agreement V2 + , (the "License"); + 20 00000000 ; You may not use this file except in compliance with t + he License. + 21 00000000 ; You may obtain a copy of the License at: + 22 00000000 ; + 23 00000000 ; http://www.st.com/software_license_agreement_l + iberty_v2 + 24 00000000 ; + 25 00000000 ; Unless required by applicable law or agreed to in wri + ting, software + 26 00000000 ; distributed under the License is distributed on an "A + S IS" BASIS, + 27 00000000 ; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + express or implied. + 28 00000000 ; See the License for the specific language governing p + ermissions and + 29 00000000 ; limitations under the License. + 30 00000000 ; + 31 00000000 ;******************************************************* + ************************ + 32 00000000 ; + 33 00000000 ; Amount of memory (in bytes) allocated for Stack + 34 00000000 ; Tailor this value to your application needs + 35 00000000 ; Stack Configuration + 36 00000000 ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + 37 00000000 ; + 38 00000000 + 39 00000000 00000400 + Stack_Size + EQU 0x00000400 + 40 00000000 + 41 00000000 AREA STACK, NOINIT, READWRITE, ALIGN + + + +ARM Macro Assembler Page 2 + + +=3 + 42 00000000 Stack_Mem + SPACE Stack_Size + 43 00000400 __initial_sp + 44 00000400 + 45 00000400 + 46 00000400 ; Heap Configuration + 47 00000400 ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + 48 00000400 ; + 49 00000400 + 50 00000400 00000200 + Heap_Size + EQU 0x00000200 + 51 00000400 + 52 00000400 AREA HEAP, NOINIT, READWRITE, ALIGN= +3 + 53 00000000 __heap_base + 54 00000000 Heap_Mem + SPACE Heap_Size + 55 00000200 __heap_limit + 56 00000200 + 57 00000200 PRESERVE8 + 58 00000200 THUMB + 59 00000200 + 60 00000200 + 61 00000200 ; Vector Table Mapped to Address 0 at Reset + 62 00000200 AREA RESET, DATA, READONLY + 63 00000000 EXPORT __Vectors + 64 00000000 EXPORT __Vectors_End + 65 00000000 EXPORT __Vectors_Size + 66 00000000 + 67 00000000 00000000 + __Vectors + DCD __initial_sp ; Top of Stack + 68 00000004 00000000 DCD Reset_Handler ; Reset Handler + 69 00000008 00000000 DCD NMI_Handler ; NMI Handler + 70 0000000C 00000000 DCD HardFault_Handler ; Hard Fault + Handler + 71 00000010 00000000 DCD 0 ; Reserved + 72 00000014 00000000 DCD 0 ; Reserved + 73 00000018 00000000 DCD 0 ; Reserved + 74 0000001C 00000000 DCD 0 ; Reserved + 75 00000020 00000000 DCD 0 ; Reserved + 76 00000024 00000000 DCD 0 ; Reserved + 77 00000028 00000000 DCD 0 ; Reserved + 78 0000002C 00000000 DCD SVC_Handler ; SVCall Handler + 79 00000030 00000000 DCD 0 ; Reserved + 80 00000034 00000000 DCD 0 ; Reserved + 81 00000038 00000000 DCD PendSV_Handler ; PendSV Handler + + 82 0000003C 00000000 DCD SysTick_Handler + ; SysTick Handler + 83 00000040 + 84 00000040 ; External Interrupts + 85 00000040 00000000 DCD WWDG_IRQHandler + ; Window Watchdog + 86 00000044 00000000 DCD PVD_IRQHandler ; PVD through EX + TI Line detect + 87 00000048 00000000 DCD RTC_IRQHandler ; RTC through EX + + + +ARM Macro Assembler Page 3 + + + TI Line + 88 0000004C 00000000 DCD FLASH_IRQHandler ; FLASH + 89 00000050 00000000 DCD RCC_IRQHandler ; RCC + 90 00000054 00000000 DCD EXTI0_1_IRQHandler + ; EXTI Line 0 and 1 + + 91 00000058 00000000 DCD EXTI2_3_IRQHandler + ; EXTI Line 2 and 3 + + 92 0000005C 00000000 DCD EXTI4_15_IRQHandler + ; EXTI Line 4 to 15 + + 93 00000060 00000000 DCD TS_IRQHandler ; TS + 94 00000064 00000000 DCD DMA1_Channel1_IRQHandler + ; DMA1 Channel 1 + 95 00000068 00000000 DCD DMA1_Channel2_3_IRQHandler ; DM + A1 Channel 2 and Ch + annel 3 + 96 0000006C 00000000 DCD DMA1_Channel4_5_IRQHandler ; DM + A1 Channel 4 and Ch + annel 5 + 97 00000070 00000000 DCD ADC1_COMP_IRQHandler ; ADC1, CO + MP1 and COMP2 + 98 00000074 00000000 DCD TIM1_BRK_UP_TRG_COM_IRQHandler + ; TIM1 Break, Updat + e, Trigger and Comm + utation + 99 00000078 00000000 DCD TIM1_CC_IRQHandler ; TIM1 Captu + re Compare + 100 0000007C 00000000 DCD TIM2_IRQHandler ; TIM2 + 101 00000080 00000000 DCD TIM3_IRQHandler ; TIM3 + 102 00000084 00000000 DCD TIM6_DAC_IRQHandler + ; TIM6 and DAC + 103 00000088 00000000 DCD 0 ; Reserved + 104 0000008C 00000000 DCD TIM14_IRQHandler ; TIM14 + 105 00000090 00000000 DCD TIM15_IRQHandler ; TIM15 + 106 00000094 00000000 DCD TIM16_IRQHandler ; TIM16 + 107 00000098 00000000 DCD TIM17_IRQHandler ; TIM17 + 108 0000009C 00000000 DCD I2C1_IRQHandler ; I2C1 + 109 000000A0 00000000 DCD I2C2_IRQHandler ; I2C2 + 110 000000A4 00000000 DCD SPI1_IRQHandler ; SPI1 + 111 000000A8 00000000 DCD SPI2_IRQHandler ; SPI2 + 112 000000AC 00000000 DCD USART1_IRQHandler ; USART1 + 113 000000B0 00000000 DCD USART2_IRQHandler ; USART2 + 114 000000B4 00000000 DCD 0 ; Reserved + 115 000000B8 00000000 DCD CEC_IRQHandler ; CEC + 116 000000BC 00000000 DCD 0 ; Reserved + 117 000000C0 + 118 000000C0 __Vectors_End + 119 000000C0 + 120 000000C0 000000C0 + __Vectors_Size + EQU __Vectors_End - __Vectors + 121 000000C0 + 122 000000C0 AREA |.text|, CODE, READONLY + 123 00000000 + 124 00000000 ; Reset handler routine + 125 00000000 Reset_Handler + PROC + + + +ARM Macro Assembler Page 4 + + + 126 00000000 EXPORT Reset_Handler [ +WEAK] + 127 00000000 IMPORT __main + 128 00000000 IMPORT SystemInit + 129 00000000 4807 LDR R0, =SystemInit + 130 00000002 4780 BLX R0 + 131 00000004 4807 LDR R0, =__main + 132 00000006 4700 BX R0 + 133 00000008 ENDP + 134 00000008 + 135 00000008 ; Dummy Exception Handlers (infinite loops which can be + modified) + 136 00000008 + 137 00000008 NMI_Handler + PROC + 138 00000008 EXPORT NMI_Handler +[WEAK] + 139 00000008 E7FE B . + 140 0000000A ENDP + 142 0000000A HardFault_Handler + PROC + 143 0000000A EXPORT HardFault_Handler +[WEAK] + 144 0000000A E7FE B . + 145 0000000C ENDP + 146 0000000C SVC_Handler + PROC + 147 0000000C EXPORT SVC_Handler +[WEAK] + 148 0000000C E7FE B . + 149 0000000E ENDP + 150 0000000E PendSV_Handler + PROC + 151 0000000E EXPORT PendSV_Handler +[WEAK] + 152 0000000E E7FE B . + 153 00000010 ENDP + 154 00000010 SysTick_Handler + PROC + 155 00000010 EXPORT SysTick_Handler +[WEAK] + 156 00000010 E7FE B . + 157 00000012 ENDP + 158 00000012 + 159 00000012 Default_Handler + PROC + 160 00000012 + 161 00000012 EXPORT WWDG_IRQHandler +[WEAK] + 162 00000012 EXPORT PVD_IRQHandler +[WEAK] + 163 00000012 EXPORT RTC_IRQHandler +[WEAK] + 164 00000012 EXPORT FLASH_IRQHandler +[WEAK] + 165 00000012 EXPORT RCC_IRQHandler +[WEAK] + 166 00000012 EXPORT EXTI0_1_IRQHandler +[WEAK] + + + +ARM Macro Assembler Page 5 + + + 167 00000012 EXPORT EXTI2_3_IRQHandler +[WEAK] + 168 00000012 EXPORT EXTI4_15_IRQHandler +[WEAK] + 169 00000012 EXPORT TS_IRQHandler +[WEAK] + 170 00000012 EXPORT DMA1_Channel1_IRQHandler +[WEAK] + 171 00000012 EXPORT DMA1_Channel2_3_IRQHandler +[WEAK] + 172 00000012 EXPORT DMA1_Channel4_5_IRQHandler +[WEAK] + 173 00000012 EXPORT ADC1_COMP_IRQHandler +[WEAK] + 174 00000012 EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler +[WEAK] + 175 00000012 EXPORT TIM1_CC_IRQHandler +[WEAK] + 176 00000012 EXPORT TIM2_IRQHandler +[WEAK] + 177 00000012 EXPORT TIM3_IRQHandler +[WEAK] + 178 00000012 EXPORT TIM6_DAC_IRQHandler +[WEAK] + 179 00000012 EXPORT TIM14_IRQHandler +[WEAK] + 180 00000012 EXPORT TIM15_IRQHandler +[WEAK] + 181 00000012 EXPORT TIM16_IRQHandler +[WEAK] + 182 00000012 EXPORT TIM17_IRQHandler +[WEAK] + 183 00000012 EXPORT I2C1_IRQHandler +[WEAK] + 184 00000012 EXPORT I2C2_IRQHandler +[WEAK] + 185 00000012 EXPORT SPI1_IRQHandler +[WEAK] + 186 00000012 EXPORT SPI2_IRQHandler +[WEAK] + 187 00000012 EXPORT USART1_IRQHandler +[WEAK] + 188 00000012 EXPORT USART2_IRQHandler +[WEAK] + 189 00000012 EXPORT CEC_IRQHandler +[WEAK] + 190 00000012 + 191 00000012 + 192 00000012 WWDG_IRQHandler + 193 00000012 PVD_IRQHandler + 194 00000012 RTC_IRQHandler + 195 00000012 FLASH_IRQHandler + 196 00000012 RCC_IRQHandler + 197 00000012 EXTI0_1_IRQHandler + 198 00000012 EXTI2_3_IRQHandler + 199 00000012 EXTI4_15_IRQHandler + 200 00000012 TS_IRQHandler + 201 00000012 DMA1_Channel1_IRQHandler + 202 00000012 DMA1_Channel2_3_IRQHandler + + + +ARM Macro Assembler Page 6 + + + 203 00000012 DMA1_Channel4_5_IRQHandler + 204 00000012 ADC1_COMP_IRQHandler + 205 00000012 TIM1_BRK_UP_TRG_COM_IRQHandler + 206 00000012 TIM1_CC_IRQHandler + 207 00000012 TIM2_IRQHandler + 208 00000012 TIM3_IRQHandler + 209 00000012 TIM6_DAC_IRQHandler + 210 00000012 TIM14_IRQHandler + 211 00000012 TIM15_IRQHandler + 212 00000012 TIM16_IRQHandler + 213 00000012 TIM17_IRQHandler + 214 00000012 I2C1_IRQHandler + 215 00000012 I2C2_IRQHandler + 216 00000012 SPI1_IRQHandler + 217 00000012 SPI2_IRQHandler + 218 00000012 USART1_IRQHandler + 219 00000012 USART2_IRQHandler + 220 00000012 CEC_IRQHandler + 221 00000012 + 222 00000012 E7FE B . + 223 00000014 + 224 00000014 ENDP + 225 00000014 + 226 00000014 ALIGN + 227 00000014 + 228 00000014 ;******************************************************* + ************************ + 229 00000014 ; User Stack and Heap initialization + 230 00000014 ;******************************************************* + ************************ + 231 00000014 IF :DEF:__MICROLIB + 238 00000014 + 239 00000014 IMPORT __use_two_region_memory + 240 00000014 EXPORT __user_initial_stackheap + 241 00000014 + 242 00000014 __user_initial_stackheap + 243 00000014 + 244 00000014 4804 LDR R0, = Heap_Mem + 245 00000016 4905 LDR R1, =(Stack_Mem + Stack_Size) + 246 00000018 4A05 LDR R2, = (Heap_Mem + Heap_Size) + 247 0000001A 4B06 LDR R3, = Stack_Mem + 248 0000001C 4770 BX LR + 249 0000001E + 250 0000001E 00 00 ALIGN + 251 00000020 + 252 00000020 ENDIF + 253 00000020 + 254 00000020 END + 00000000 + 00000000 + 00000000 + 00000400 + 00000200 + 00000000 +Command Line: --debug --xref --cpu=Cortex-M0 --apcs=interwork --depend=..\obj\s +tartup_stm32f0xx.d -o..\obj\startup_stm32f0xx.o -IC:\Keil\ARM\RV31\INC -IC:\Kei +l\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -IC:\Keil\ARM\PACK\Keil\STM32F0xx_DFP +\1.0.0\Device\Include --list=.\startup_stm32f0xx.lst ..\CORE\startup_stm32f0xx. +s + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +STACK 00000000 + +Symbol: STACK + Definitions + At line 41 in file ..\CORE\startup_stm32f0xx.s + Uses + None +Comment: STACK unused +Stack_Mem 00000000 + +Symbol: Stack_Mem + Definitions + At line 42 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 245 in file ..\CORE\startup_stm32f0xx.s + At line 247 in file ..\CORE\startup_stm32f0xx.s + +__initial_sp 00000400 + +Symbol: __initial_sp + Definitions + At line 43 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 67 in file ..\CORE\startup_stm32f0xx.s +Comment: __initial_sp used once +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +HEAP 00000000 + +Symbol: HEAP + Definitions + At line 52 in file ..\CORE\startup_stm32f0xx.s + Uses + None +Comment: HEAP unused +Heap_Mem 00000000 + +Symbol: Heap_Mem + Definitions + At line 54 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 244 in file ..\CORE\startup_stm32f0xx.s + At line 246 in file ..\CORE\startup_stm32f0xx.s + +__heap_base 00000000 + +Symbol: __heap_base + Definitions + At line 53 in file ..\CORE\startup_stm32f0xx.s + Uses + None +Comment: __heap_base unused +__heap_limit 00000200 + +Symbol: __heap_limit + Definitions + At line 55 in file ..\CORE\startup_stm32f0xx.s + Uses + None +Comment: __heap_limit unused +4 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +RESET 00000000 + +Symbol: RESET + Definitions + At line 62 in file ..\CORE\startup_stm32f0xx.s + Uses + None +Comment: RESET unused +__Vectors 00000000 + +Symbol: __Vectors + Definitions + At line 67 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 63 in file ..\CORE\startup_stm32f0xx.s + At line 120 in file ..\CORE\startup_stm32f0xx.s + +__Vectors_End 000000C0 + +Symbol: __Vectors_End + Definitions + At line 118 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 64 in file ..\CORE\startup_stm32f0xx.s + At line 120 in file ..\CORE\startup_stm32f0xx.s + +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +.text 00000000 + +Symbol: .text + Definitions + At line 122 in file ..\CORE\startup_stm32f0xx.s + Uses + None +Comment: .text unused +ADC1_COMP_IRQHandler 00000012 + +Symbol: ADC1_COMP_IRQHandler + Definitions + At line 204 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 97 in file ..\CORE\startup_stm32f0xx.s + At line 173 in file ..\CORE\startup_stm32f0xx.s + +CEC_IRQHandler 00000012 + +Symbol: CEC_IRQHandler + Definitions + At line 220 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 115 in file ..\CORE\startup_stm32f0xx.s + At line 189 in file ..\CORE\startup_stm32f0xx.s + +DMA1_Channel1_IRQHandler 00000012 + +Symbol: DMA1_Channel1_IRQHandler + Definitions + At line 201 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 94 in file ..\CORE\startup_stm32f0xx.s + At line 170 in file ..\CORE\startup_stm32f0xx.s + +DMA1_Channel2_3_IRQHandler 00000012 + +Symbol: DMA1_Channel2_3_IRQHandler + Definitions + At line 202 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 95 in file ..\CORE\startup_stm32f0xx.s + At line 171 in file ..\CORE\startup_stm32f0xx.s + +DMA1_Channel4_5_IRQHandler 00000012 + +Symbol: DMA1_Channel4_5_IRQHandler + Definitions + At line 203 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 96 in file ..\CORE\startup_stm32f0xx.s + At line 172 in file ..\CORE\startup_stm32f0xx.s + +Default_Handler 00000012 + +Symbol: Default_Handler + Definitions + At line 159 in file ..\CORE\startup_stm32f0xx.s + Uses + + + +ARM Macro Assembler Page 2 Alphabetic symbol ordering +Relocatable symbols + + None +Comment: Default_Handler unused +EXTI0_1_IRQHandler 00000012 + +Symbol: EXTI0_1_IRQHandler + Definitions + At line 197 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 90 in file ..\CORE\startup_stm32f0xx.s + At line 166 in file ..\CORE\startup_stm32f0xx.s + +EXTI2_3_IRQHandler 00000012 + +Symbol: EXTI2_3_IRQHandler + Definitions + At line 198 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 91 in file ..\CORE\startup_stm32f0xx.s + At line 167 in file ..\CORE\startup_stm32f0xx.s + +EXTI4_15_IRQHandler 00000012 + +Symbol: EXTI4_15_IRQHandler + Definitions + At line 199 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 92 in file ..\CORE\startup_stm32f0xx.s + At line 168 in file ..\CORE\startup_stm32f0xx.s + +FLASH_IRQHandler 00000012 + +Symbol: FLASH_IRQHandler + Definitions + At line 195 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 88 in file ..\CORE\startup_stm32f0xx.s + At line 164 in file ..\CORE\startup_stm32f0xx.s + +HardFault_Handler 0000000A + +Symbol: HardFault_Handler + Definitions + At line 142 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 70 in file ..\CORE\startup_stm32f0xx.s + At line 143 in file ..\CORE\startup_stm32f0xx.s + +I2C1_IRQHandler 00000012 + +Symbol: I2C1_IRQHandler + Definitions + At line 214 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 108 in file ..\CORE\startup_stm32f0xx.s + At line 183 in file ..\CORE\startup_stm32f0xx.s + +I2C2_IRQHandler 00000012 + +Symbol: I2C2_IRQHandler + + + +ARM Macro Assembler Page 3 Alphabetic symbol ordering +Relocatable symbols + + Definitions + At line 215 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 109 in file ..\CORE\startup_stm32f0xx.s + At line 184 in file ..\CORE\startup_stm32f0xx.s + +NMI_Handler 00000008 + +Symbol: NMI_Handler + Definitions + At line 137 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 69 in file ..\CORE\startup_stm32f0xx.s + At line 138 in file ..\CORE\startup_stm32f0xx.s + +PVD_IRQHandler 00000012 + +Symbol: PVD_IRQHandler + Definitions + At line 193 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 86 in file ..\CORE\startup_stm32f0xx.s + At line 162 in file ..\CORE\startup_stm32f0xx.s + +PendSV_Handler 0000000E + +Symbol: PendSV_Handler + Definitions + At line 150 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 81 in file ..\CORE\startup_stm32f0xx.s + At line 151 in file ..\CORE\startup_stm32f0xx.s + +RCC_IRQHandler 00000012 + +Symbol: RCC_IRQHandler + Definitions + At line 196 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 89 in file ..\CORE\startup_stm32f0xx.s + At line 165 in file ..\CORE\startup_stm32f0xx.s + +RTC_IRQHandler 00000012 + +Symbol: RTC_IRQHandler + Definitions + At line 194 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 87 in file ..\CORE\startup_stm32f0xx.s + At line 163 in file ..\CORE\startup_stm32f0xx.s + +Reset_Handler 00000000 + +Symbol: Reset_Handler + Definitions + At line 125 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 68 in file ..\CORE\startup_stm32f0xx.s + At line 126 in file ..\CORE\startup_stm32f0xx.s + + + +ARM Macro Assembler Page 4 Alphabetic symbol ordering +Relocatable symbols + + +SPI1_IRQHandler 00000012 + +Symbol: SPI1_IRQHandler + Definitions + At line 216 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 110 in file ..\CORE\startup_stm32f0xx.s + At line 185 in file ..\CORE\startup_stm32f0xx.s + +SPI2_IRQHandler 00000012 + +Symbol: SPI2_IRQHandler + Definitions + At line 217 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 111 in file ..\CORE\startup_stm32f0xx.s + At line 186 in file ..\CORE\startup_stm32f0xx.s + +SVC_Handler 0000000C + +Symbol: SVC_Handler + Definitions + At line 146 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 78 in file ..\CORE\startup_stm32f0xx.s + At line 147 in file ..\CORE\startup_stm32f0xx.s + +SysTick_Handler 00000010 + +Symbol: SysTick_Handler + Definitions + At line 154 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 82 in file ..\CORE\startup_stm32f0xx.s + At line 155 in file ..\CORE\startup_stm32f0xx.s + +TIM14_IRQHandler 00000012 + +Symbol: TIM14_IRQHandler + Definitions + At line 210 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 104 in file ..\CORE\startup_stm32f0xx.s + At line 179 in file ..\CORE\startup_stm32f0xx.s + +TIM15_IRQHandler 00000012 + +Symbol: TIM15_IRQHandler + Definitions + At line 211 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 105 in file ..\CORE\startup_stm32f0xx.s + At line 180 in file ..\CORE\startup_stm32f0xx.s + +TIM16_IRQHandler 00000012 + +Symbol: TIM16_IRQHandler + Definitions + + + +ARM Macro Assembler Page 5 Alphabetic symbol ordering +Relocatable symbols + + At line 212 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 106 in file ..\CORE\startup_stm32f0xx.s + At line 181 in file ..\CORE\startup_stm32f0xx.s + +TIM17_IRQHandler 00000012 + +Symbol: TIM17_IRQHandler + Definitions + At line 213 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 107 in file ..\CORE\startup_stm32f0xx.s + At line 182 in file ..\CORE\startup_stm32f0xx.s + +TIM1_BRK_UP_TRG_COM_IRQHandler 00000012 + +Symbol: TIM1_BRK_UP_TRG_COM_IRQHandler + Definitions + At line 205 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 98 in file ..\CORE\startup_stm32f0xx.s + At line 174 in file ..\CORE\startup_stm32f0xx.s + +TIM1_CC_IRQHandler 00000012 + +Symbol: TIM1_CC_IRQHandler + Definitions + At line 206 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 99 in file ..\CORE\startup_stm32f0xx.s + At line 175 in file ..\CORE\startup_stm32f0xx.s + +TIM2_IRQHandler 00000012 + +Symbol: TIM2_IRQHandler + Definitions + At line 207 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 100 in file ..\CORE\startup_stm32f0xx.s + At line 176 in file ..\CORE\startup_stm32f0xx.s + +TIM3_IRQHandler 00000012 + +Symbol: TIM3_IRQHandler + Definitions + At line 208 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 101 in file ..\CORE\startup_stm32f0xx.s + At line 177 in file ..\CORE\startup_stm32f0xx.s + +TIM6_DAC_IRQHandler 00000012 + +Symbol: TIM6_DAC_IRQHandler + Definitions + At line 209 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 102 in file ..\CORE\startup_stm32f0xx.s + At line 178 in file ..\CORE\startup_stm32f0xx.s + + + + +ARM Macro Assembler Page 6 Alphabetic symbol ordering +Relocatable symbols + +TS_IRQHandler 00000012 + +Symbol: TS_IRQHandler + Definitions + At line 200 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 93 in file ..\CORE\startup_stm32f0xx.s + At line 169 in file ..\CORE\startup_stm32f0xx.s + +USART1_IRQHandler 00000012 + +Symbol: USART1_IRQHandler + Definitions + At line 218 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 112 in file ..\CORE\startup_stm32f0xx.s + At line 187 in file ..\CORE\startup_stm32f0xx.s + +USART2_IRQHandler 00000012 + +Symbol: USART2_IRQHandler + Definitions + At line 219 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 113 in file ..\CORE\startup_stm32f0xx.s + At line 188 in file ..\CORE\startup_stm32f0xx.s + +WWDG_IRQHandler 00000012 + +Symbol: WWDG_IRQHandler + Definitions + At line 192 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 85 in file ..\CORE\startup_stm32f0xx.s + At line 161 in file ..\CORE\startup_stm32f0xx.s + +__user_initial_stackheap 00000014 + +Symbol: __user_initial_stackheap + Definitions + At line 242 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 240 in file ..\CORE\startup_stm32f0xx.s +Comment: __user_initial_stackheap used once +38 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Absolute symbols + +Heap_Size 00000200 + +Symbol: Heap_Size + Definitions + At line 50 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 54 in file ..\CORE\startup_stm32f0xx.s + At line 246 in file ..\CORE\startup_stm32f0xx.s + +Stack_Size 00000400 + +Symbol: Stack_Size + Definitions + At line 39 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 42 in file ..\CORE\startup_stm32f0xx.s + At line 245 in file ..\CORE\startup_stm32f0xx.s + +__Vectors_Size 000000C0 + +Symbol: __Vectors_Size + Definitions + At line 120 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 65 in file ..\CORE\startup_stm32f0xx.s +Comment: __Vectors_Size used once +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +External symbols + +SystemInit 00000000 + +Symbol: SystemInit + Definitions + At line 128 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 129 in file ..\CORE\startup_stm32f0xx.s +Comment: SystemInit used once +__main 00000000 + +Symbol: __main + Definitions + At line 127 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 131 in file ..\CORE\startup_stm32f0xx.s +Comment: __main used once +__use_two_region_memory 00000000 + +Symbol: __use_two_region_memory + Definitions + At line 239 in file ..\CORE\startup_stm32f0xx.s + Uses + None +Comment: __use_two_region_memory unused +3 symbols +388 symbols in table diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/STM32F030Demo.build_log.htm b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/STM32F030Demo.build_log.htm new file mode 100644 index 0000000..e6d1421 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/STM32F030Demo.build_log.htm @@ -0,0 +1,26 @@ + + +
+
Vision Build Log

+
Project:

+E:\SSJ Ŀ\SSJ Ŀ\ʾģ Ŀ\\ģԳ\2.4\CN2048 оƬԴ\STM32F030\User\STM32F030Demo.uvproj
+Project File Date:  11/14/2018
+
+
Output:

+Build target 'Stm32f030demo'
+linking...
+..\OBJ\STM32F030Demo.axf: Error: L6218E: Undefined symbol GetKeyVal (referred from main.o).
+..\OBJ\STM32F030Demo.axf: Error: L6218E: Undefined symbol KeyInit (referred from main.o).
+Not enough information to list image symbols.
+Finished: 1 information, 0 warning and 2 error messages.
+"..\OBJ\STM32F030Demo.axf" - 2 Error(s), 0 Warning(s).
+Target not created
+
+ + +ain.o). +..\OBJ\STM32F030Demo.axf: Error: L6218E: Undefined symbol KeyInit (referred from main.o). +Not enough information to list image symbols. +Finished: 1 information, 0 warning and 2 error messages. +"..\OBJ\STM32F030Demo.axf" - 2 Error(s), 0 Warning(s). +Target not created diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/STM32F030Demo.htm b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/STM32F030Demo.htm new file mode 100644 index 0000000..9a4fd7a --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/STM32F030Demo.htm @@ -0,0 +1,803 @@ + + +Static Call Graph - [..\OBJ\STM32F030Demo.axf] +
+

Static Call Graph for image ..\OBJ\STM32F030Demo.axf

+

#<CALLGRAPH># ARM Linker, 5040049: Last Updated: Wed Nov 14 16:32:57 2018 +

+

Maximum Stack Usage = 136 bytes + Unknown(Functions without stacksize, Cycles, Untraceable Function Pointers)

+Call chain for Maximum Stack Depth:

+__rt_entry_main ⇒ main ⇒ __2printf ⇒ _printf_char_file ⇒ _printf_char_common ⇒ __printf +

+

+Functions with no stack information +

+ +

+

+Mutually Recursive functions +

  • ADC1_COMP_IRQHandler   ⇒   ADC1_COMP_IRQHandler
    + +

    +

    +Function Pointers +

      +
    • ADC1_COMP_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • CEC_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • DMA1_Channel1_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • DMA1_Channel2_3_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • DMA1_Channel4_5_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • EXTI0_1_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • EXTI2_3_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • EXTI4_15_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • FLASH_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • HardFault_Handler from stm32f0xx_it.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • I2C1_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • I2C2_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • NMI_Handler from stm32f0xx_it.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • PVD_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • PendSV_Handler from stm32f0xx_it.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • RCC_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • RTC_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • Reset_Handler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • SPI1_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • SPI2_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • SVC_Handler from stm32f0xx_it.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • SysTick_Handler from stm32f0xx_it.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • SystemInit from system_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(.text) +
    • TIM14_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • TIM15_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • TIM16_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • TIM17_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • TIM1_BRK_UP_TRG_COM_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • TIM1_CC_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • TIM2_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • TIM3_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • TIM6_DAC_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • TS_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • USART1_IRQHandler from usart1.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • USART2_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • WWDG_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • __main from __main.o(!!!main) referenced from startup_stm32f0xx.o(.text) +
    • _printf_input_char from _printf_char_common.o(.text) referenced from _printf_char_common.o(.text) +
    • fputc from usart1.o(.text) referenced from _printf_char_file.o(.text) +
    +

    +

    +Global Symbols +

    +

    __main (Thumb, 8 bytes, Stack size 0 bytes, __main.o(!!!main)) +

    [Calls]

    • >>   __rt_entry +
    • >>   __scatterload +
    + +

    __scatterload (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter)) +

    [Called By]

    • >>   __main +
    + +

    __scatterload_rt2 (Thumb, 52 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED) +

    [Calls]

    • >>   __rt_entry +
    + +

    __scatterload_rt2_thumb_only (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED) + +

    __scatterload_null (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED) + +

    __scatterload_copy (Thumb, 26 bytes, Stack size unknown bytes, __scatter_copy.o(!!handler_copy), UNUSED) +

    [Calls]

    • >>   __scatterload_copy +
    +
    [Called By]
    • >>   __scatterload_copy +
    + +

    __scatterload_zeroinit (Thumb, 28 bytes, Stack size unknown bytes, __scatter_zi.o(!!handler_zi), UNUSED) + +

    _printf_percent (Thumb, 0 bytes, Stack size unknown bytes, _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000)) +

    [Called By]

    • >>   __printf +
    + +

    _printf_percent_end (Thumb, 0 bytes, Stack size unknown bytes, _printf_percent_end.o(.ARM.Collect$$_printf_percent$$00000017)) + +

    __rt_lib_init (Thumb, 0 bytes, Stack size unknown bytes, libinit.o(.ARM.Collect$$libinit$$00000000)) +

    [Called By]

    • >>   __rt_entry_li +
    + +

    __rt_lib_init_fp_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000001)) + +

    __rt_lib_init_alloca_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000002C)) + +

    __rt_lib_init_argv_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000002A)) + +

    __rt_lib_init_atexit_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000019)) + +

    __rt_lib_init_clock_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001F)) + +

    __rt_lib_init_cpp_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000030)) + +

    __rt_lib_init_exceptions_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000002E)) + +

    __rt_lib_init_fp_trap_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001D)) + +

    __rt_lib_init_getenv_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000021)) + +

    __rt_lib_init_heap_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000008)) + +

    __rt_lib_init_lc_collate_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000F)) + +

    __rt_lib_init_lc_ctype_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000011)) + +

    __rt_lib_init_lc_monetary_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000013)) + +

    __rt_lib_init_lc_numeric_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000015)) + +

    __rt_lib_init_lc_time_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000017)) + +

    __rt_lib_init_rand_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000C)) + +

    __rt_lib_init_return (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000031)) + +

    __rt_lib_init_signal_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001B)) + +

    __rt_lib_init_stdio_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000023)) + +

    __rt_lib_init_user_alloc_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000A)) + +

    __rt_lib_shutdown (Thumb, 0 bytes, Stack size unknown bytes, libshutdown.o(.ARM.Collect$$libshutdown$$00000000)) +

    [Called By]

    • >>   __rt_exit_ls +
    + +

    __rt_lib_shutdown_fp_trap_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000006)) + +

    __rt_lib_shutdown_heap_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000E)) + +

    __rt_lib_shutdown_return (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F)) + +

    __rt_lib_shutdown_signal_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000009)) + +

    __rt_lib_shutdown_stdio_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000003)) + +

    __rt_lib_shutdown_user_alloc_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000B)) + +

    __rt_entry (Thumb, 0 bytes, Stack size unknown bytes, rtentry.o(.ARM.Collect$$rtentry$$00000000)) +

    [Called By]

    • >>   __main +
    • >>   __scatterload_rt2 +
    + +

    __rt_entry_presh_1 (Thumb, 0 bytes, Stack size unknown bytes, rtentry2.o(.ARM.Collect$$rtentry$$00000002)) + +

    __rt_entry_sh (Thumb, 0 bytes, Stack size unknown bytes, rtentry4.o(.ARM.Collect$$rtentry$$00000004)) +

    [Stack]

    • Max Depth = 8 + Unknown Stack Size +
    • Call Chain = __rt_entry_sh ⇒ __user_setup_stackheap +
    +
    [Calls]
    • >>   __user_setup_stackheap +
    + +

    __rt_entry_li (Thumb, 0 bytes, Stack size unknown bytes, rtentry2.o(.ARM.Collect$$rtentry$$0000000A)) +

    [Calls]

    • >>   __rt_lib_init +
    + +

    __rt_entry_postsh_1 (Thumb, 0 bytes, Stack size unknown bytes, rtentry2.o(.ARM.Collect$$rtentry$$00000009)) + +

    __rt_entry_main (Thumb, 0 bytes, Stack size unknown bytes, rtentry2.o(.ARM.Collect$$rtentry$$0000000D)) +

    [Stack]

    • Max Depth = 136 + Unknown Stack Size +
    • Call Chain = __rt_entry_main ⇒ main ⇒ __2printf ⇒ _printf_char_file ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   main +
    • >>   exit +
    + +

    __rt_entry_postli_1 (Thumb, 0 bytes, Stack size unknown bytes, rtentry2.o(.ARM.Collect$$rtentry$$0000000C)) + +

    __rt_exit (Thumb, 0 bytes, Stack size unknown bytes, rtexit.o(.ARM.Collect$$rtexit$$00000000)) +

    [Called By]

    • >>   exit +
    + +

    __rt_exit_ls (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000003)) +

    [Calls]

    • >>   __rt_lib_shutdown +
    + +

    __rt_exit_prels_1 (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000002)) + +

    __rt_exit_exit (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000004)) +

    [Calls]

    • >>   _sys_exit +
    + +

    main (Thumb, 328 bytes, Stack size 0 bytes, main.o(.text)) +

    [Stack]

    • Max Depth = 136 + Unknown Stack Size +
    • Call Chain = main ⇒ __2printf ⇒ _printf_char_file ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   __2printf +
    • >>   delay_ms +
    • >>   delay_init +
    • >>   USART1_Init +
    • >>   LED_Init +
    • >>   KeyInit +
    • >>   GetKeyVal +
    +
    [Called By]
    • >>   __rt_entry_main +
    + +

    NMI_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f0xx_it.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    HardFault_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32f0xx_it.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    SVC_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f0xx_it.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    PendSV_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f0xx_it.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    SysTick_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f0xx_it.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    SystemInit (Thumb, 110 bytes, Stack size 8 bytes, system_stm32f0xx.o(.text)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = SystemInit ⇒ SetSysClock +
    +
    [Calls]
    • >>   SetSysClock +
    +
    [Address Reference Count : 1]
    • startup_stm32f0xx.o(.text) +
    +

    SystemCoreClockUpdate (Thumb, 154 bytes, Stack size 24 bytes, system_stm32f0xx.o(.text), UNUSED) +

    [Calls]

    • >>   __aeabi_uidivmod +
    + +

    Reset_Handler (Thumb, 8 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) + +

    ADC1_COMP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +

    [Calls]

    • >>   ADC1_COMP_IRQHandler +
    +
    [Called By]
    • >>   ADC1_COMP_IRQHandler +
    +
    [Address Reference Count : 1]
    • startup_stm32f0xx.o(RESET) +
    +

    CEC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    DMA1_Channel1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    DMA1_Channel2_3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    DMA1_Channel4_5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    EXTI0_1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    EXTI2_3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    EXTI4_15_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    FLASH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    I2C1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    I2C2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    PVD_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    RCC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    RTC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    SPI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    SPI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    TIM14_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    TIM15_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    TIM16_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    TIM17_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    TIM1_BRK_UP_TRG_COM_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    TIM1_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    TIM2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    TIM3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    TIM6_DAC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    TS_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    USART2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    WWDG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    __user_initial_stackheap (Thumb, 0 bytes, Stack size unknown bytes, startup_stm32f0xx.o(.text)) +

    [Called By]

    • >>   __user_setup_stackheap +
    + +

    LED_Init (Thumb, 42 bytes, Stack size 16 bytes, led.o(.text)) +

    [Stack]

    • Max Depth = 36
    • Call Chain = LED_Init ⇒ GPIO_Init +
    +
    [Calls]
    • >>   RCC_AHBPeriphClockCmd +
    • >>   GPIO_Init +
    +
    [Called By]
    • >>   main +
    + +

    _sys_exit (Thumb, 4 bytes, Stack size 0 bytes, usart1.o(.text)) +

    [Called By]

    • >>   __rt_exit_exit +
    + +

    fputc (Thumb, 22 bytes, Stack size 0 bytes, usart1.o(.text)) +
    [Address Reference Count : 1]

    • _printf_char_file.o(.text) +
    +

    USART1_Init (Thumb, 144 bytes, Stack size 48 bytes, usart1.o(.text)) +

    [Stack]

    • Max Depth = 136
    • Call Chain = USART1_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   USART_Init +
    • >>   USART_ITConfig +
    • >>   USART_Cmd +
    • >>   RCC_APB2PeriphClockCmd +
    • >>   NVIC_Init +
    • >>   GPIO_PinAFConfig +
    • >>   RCC_AHBPeriphClockCmd +
    • >>   GPIO_Init +
    +
    [Called By]
    • >>   main +
    + +

    USART1_IRQHandler (Thumb, 46 bytes, Stack size 8 bytes, usart1.o(.text)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = USART1_IRQHandler ⇒ USART_GetITStatus +
    +
    [Calls]
    • >>   USART_SendData +
    • >>   USART_ReceiveData +
    • >>   USART_GetITStatus +
    • >>   USART_GetFlagStatus +
    +
    [Address Reference Count : 1]
    • startup_stm32f0xx.o(RESET) +
    +

    KeyInit (Thumb, 40 bytes, Stack size 16 bytes, key.o(.text)) +

    [Stack]

    • Max Depth = 36
    • Call Chain = KeyInit ⇒ GPIO_Init +
    +
    [Calls]
    • >>   RCC_AHBPeriphClockCmd +
    • >>   GPIO_Init +
    +
    [Called By]
    • >>   main +
    + +

    GetKeyVal (Thumb, 92 bytes, Stack size 8 bytes, key.o(.text)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = GetKeyVal +
    +
    [Calls]
    • >>   delay_ms +
    +
    [Called By]
    • >>   main +
    + +

    delay_init (Thumb, 44 bytes, Stack size 8 bytes, delay.o(.text)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = delay_init +
    +
    [Calls]
    • >>   __aeabi_uidivmod +
    • >>   SysTick_CLKSourceConfig +
    +
    [Called By]
    • >>   main +
    + +

    delay_us (Thumb, 74 bytes, Stack size 0 bytes, delay.o(.text), UNUSED) + +

    delay_ms (Thumb, 74 bytes, Stack size 0 bytes, delay.o(.text)) +

    [Called By]

    • >>   GetKeyVal +
    • >>   main +
    + +

    GPIO_DeInit (Thumb, 132 bytes, Stack size 8 bytes, stm32f0xx_gpio.o(.text), UNUSED) +

    [Calls]

    • >>   RCC_AHBPeriphResetCmd +
    + +

    GPIO_Init (Thumb, 144 bytes, Stack size 20 bytes, stm32f0xx_gpio.o(.text)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = GPIO_Init +
    +
    [Called By]
    • >>   USART1_Init +
    • >>   LED_Init +
    • >>   KeyInit +
    + +

    GPIO_StructInit (Thumb, 20 bytes, Stack size 0 bytes, stm32f0xx_gpio.o(.text), UNUSED) + +

    GPIO_PinLockConfig (Thumb, 34 bytes, Stack size 8 bytes, stm32f0xx_gpio.o(.text), UNUSED) + +

    GPIO_ReadInputDataBit (Thumb, 20 bytes, Stack size 0 bytes, stm32f0xx_gpio.o(.text), UNUSED) + +

    GPIO_ReadInputData (Thumb, 6 bytes, Stack size 0 bytes, stm32f0xx_gpio.o(.text), UNUSED) + +

    GPIO_ReadOutputDataBit (Thumb, 20 bytes, Stack size 0 bytes, stm32f0xx_gpio.o(.text), UNUSED) + +

    GPIO_ReadOutputData (Thumb, 6 bytes, Stack size 0 bytes, stm32f0xx_gpio.o(.text), UNUSED) + +

    GPIO_SetBits (Thumb, 4 bytes, Stack size 0 bytes, stm32f0xx_gpio.o(.text), UNUSED) + +

    GPIO_ResetBits (Thumb, 4 bytes, Stack size 0 bytes, stm32f0xx_gpio.o(.text), UNUSED) + +

    GPIO_WriteBit (Thumb, 12 bytes, Stack size 0 bytes, stm32f0xx_gpio.o(.text), UNUSED) + +

    GPIO_Write (Thumb, 4 bytes, Stack size 0 bytes, stm32f0xx_gpio.o(.text), UNUSED) + +

    GPIO_PinAFConfig (Thumb, 68 bytes, Stack size 20 bytes, stm32f0xx_gpio.o(.text)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = GPIO_PinAFConfig +
    +
    [Called By]
    • >>   USART1_Init +
    + +

    RCC_DeInit (Thumb, 104 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_HSEConfig (Thumb, 12 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_GetFlagStatus (Thumb, 68 bytes, Stack size 8 bytes, stm32f0xx_rcc.o(.text), UNUSED) +

    [Called By]

    • >>   RCC_WaitForHSEStartUp +
    + +

    RCC_WaitForHSEStartUp (Thumb, 60 bytes, Stack size 16 bytes, stm32f0xx_rcc.o(.text), UNUSED) +

    [Calls]

    • >>   RCC_GetFlagStatus +
    + +

    RCC_AdjustHSICalibrationValue (Thumb, 26 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_HSICmd (Thumb, 32 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_AdjustHSI14CalibrationValue (Thumb, 26 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_HSI14Cmd (Thumb, 32 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_HSI14ADCRequestCmd (Thumb, 32 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_LSEConfig (Thumb, 34 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_LSEDriveConfig (Thumb, 22 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_LSICmd (Thumb, 32 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_PLLConfig (Thumb, 30 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_PLLCmd (Thumb, 36 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_PREDIV1Config (Thumb, 24 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_ClockSecuritySystemCmd (Thumb, 36 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_MCOConfig (Thumb, 6 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_SYSCLKConfig (Thumb, 24 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_GetSYSCLKSource (Thumb, 10 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_HCLKConfig (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_PCLKConfig (Thumb, 30 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_ADCCLKConfig (Thumb, 52 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_CECCLKConfig (Thumb, 22 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_I2CCLKConfig (Thumb, 22 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_USARTCLKConfig (Thumb, 22 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_GetClocksFreq (Thumb, 368 bytes, Stack size 32 bytes, stm32f0xx_rcc.o(.text)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = RCC_GetClocksFreq +
    +
    [Calls]
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   USART_Init +
    + +

    RCC_RTCCLKConfig (Thumb, 12 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_RTCCLKCmd (Thumb, 36 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_BackupResetCmd (Thumb, 36 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_AHBPeriphClockCmd (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text)) +

    [Called By]

    • >>   USART1_Init +
    • >>   LED_Init +
    • >>   KeyInit +
    + +

    RCC_APB2PeriphClockCmd (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text)) +

    [Called By]

    • >>   USART1_Init +
    + +

    RCC_APB1PeriphClockCmd (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_AHBPeriphResetCmd (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) +

    [Called By]

    • >>   GPIO_DeInit +
    + +

    RCC_APB2PeriphResetCmd (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) +

    [Called By]

    • >>   USART_DeInit +
    + +

    RCC_APB1PeriphResetCmd (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) +

    [Called By]

    • >>   USART_DeInit +
    + +

    RCC_ITConfig (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_ClearFlag (Thumb, 16 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_GetITStatus (Thumb, 22 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_ClearITPendingBit (Thumb, 6 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    NVIC_Init (Thumb, 106 bytes, Stack size 0 bytes, stm32f0xx_misc.o(.text)) +

    [Called By]

    • >>   USART1_Init +
    + +

    NVIC_SystemLPConfig (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_misc.o(.text), UNUSED) + +

    SysTick_CLKSourceConfig (Thumb, 32 bytes, Stack size 0 bytes, stm32f0xx_misc.o(.text)) +

    [Called By]

    • >>   delay_init +
    + +

    USART_DeInit (Thumb, 56 bytes, Stack size 8 bytes, stm32f0xx_usart.o(.text), UNUSED) +

    [Calls]

    • >>   RCC_APB1PeriphResetCmd +
    • >>   RCC_APB2PeriphResetCmd +
    + +

    USART_Init (Thumb, 234 bytes, Stack size 56 bytes, stm32f0xx_usart.o(.text)) +

    [Stack]

    • Max Depth = 88
    • Call Chain = USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   __aeabi_uidivmod +
    • >>   RCC_GetClocksFreq +
    +
    [Called By]
    • >>   USART1_Init +
    + +

    USART_StructInit (Thumb, 24 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_ClockInit (Thumb, 36 bytes, Stack size 8 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_ClockStructInit (Thumb, 12 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_Cmd (Thumb, 24 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text)) +

    [Called By]

    • >>   USART1_Init +
    + +

    USART_DirectionModeCmd (Thumb, 20 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_OverSampling8Cmd (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_OneBitMethodCmd (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_MSBFirstCmd (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_DataInvCmd (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_InvPinCmd (Thumb, 20 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_SWAPPinCmd (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_ReceiverTimeOutCmd (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_SetReceiverTimeOut (Thumb, 16 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_SetPrescaler (Thumb, 18 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_STOPModeCmd (Thumb, 24 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_StopModeWakeUpSourceConfig (Thumb, 18 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_AutoBaudRateCmd (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_AutoBaudRateConfig (Thumb, 18 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_AutoBaudRateNewRequest (Thumb, 12 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_SendData (Thumb, 8 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text)) +

    [Called By]

    • >>   USART1_IRQHandler +
    + +

    USART_ReceiveData (Thumb, 10 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text)) +

    [Called By]

    • >>   USART1_IRQHandler +
    + +

    USART_SetAddress (Thumb, 18 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_MuteModeCmd (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_MuteModeWakeUpConfig (Thumb, 18 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_AddressDetectionConfig (Thumb, 16 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_LINBreakDetectLengthConfig (Thumb, 16 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_LINCmd (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_HalfDuplexCmd (Thumb, 24 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_SetGuardTime (Thumb, 16 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_SmartCardCmd (Thumb, 24 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_SmartCardNACKCmd (Thumb, 24 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_SetAutoRetryCount (Thumb, 20 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_SetBlockLength (Thumb, 30 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_IrDAConfig (Thumb, 16 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_IrDACmd (Thumb, 24 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_DECmd (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_DEPolarityConfig (Thumb, 18 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_SetDEAssertionTime (Thumb, 20 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_SetDEDeassertionTime (Thumb, 20 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_DMACmd (Thumb, 20 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_DMAReceptionErrorConfig (Thumb, 18 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_ITConfig (Thumb, 66 bytes, Stack size 24 bytes, stm32f0xx_usart.o(.text)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = USART_ITConfig +
    +
    [Called By]
    • >>   USART1_Init +
    + +

    USART_RequestCmd (Thumb, 20 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_OverrunDetectionConfig (Thumb, 18 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_GetFlagStatus (Thumb, 20 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text)) +

    [Called By]

    • >>   USART1_IRQHandler +
    + +

    USART_ClearFlag (Thumb, 4 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_GetITStatus (Thumb, 78 bytes, Stack size 16 bytes, stm32f0xx_usart.o(.text)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = USART_GetITStatus +
    +
    [Called By]
    • >>   USART1_IRQHandler +
    + +

    USART_ClearITPendingBit (Thumb, 18 bytes, Stack size 8 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    __use_no_semihosting (Thumb, 2 bytes, Stack size 0 bytes, use_no_semi_2.o(.text), UNUSED) + +

    __2printf (Thumb, 22 bytes, Stack size 24 bytes, __2printf.o(.text)) +

    [Stack]

    • Max Depth = 136 + Unknown Stack Size +
    • Call Chain = __2printf ⇒ _printf_char_file ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   _printf_char_file +
    +
    [Called By]
    • >>   main +
    + +

    __aeabi_uidiv (Thumb, 0 bytes, Stack size 0 bytes, aeabi_sdiv.o(.text), UNUSED) + +

    __aeabi_uidivmod (Thumb, 20 bytes, Stack size 0 bytes, aeabi_sdiv.o(.text)) +

    [Called By]

    • >>   RCC_GetClocksFreq +
    • >>   USART_Init +
    • >>   SystemCoreClockUpdate +
    • >>   delay_init +
    + +

    __aeabi_idiv (Thumb, 0 bytes, Stack size 8 bytes, aeabi_sdiv.o(.text), UNUSED) + +

    __aeabi_idivmod (Thumb, 326 bytes, Stack size 8 bytes, aeabi_sdiv.o(.text), UNUSED) + +

    __use_two_region_memory (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED) + +

    __rt_heap_escrow$2region (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED) + +

    __rt_heap_expand$2region (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED) + +

    __I$use$semihosting (Thumb, 0 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED) + +

    __use_no_semihosting_swi (Thumb, 2 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED) + +

    _printf_char_file (Thumb, 34 bytes, Stack size 16 bytes, _printf_char_file.o(.text)) +

    [Stack]

    • Max Depth = 112 + Unknown Stack Size +
    • Call Chain = _printf_char_file ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   ferror +
    • >>   _printf_char_common +
    +
    [Called By]
    • >>   __2printf +
    + +

    __printf (Thumb, 386 bytes, Stack size 32 bytes, __printf_flags_ss_wp.o(.text)) +

    [Stack]

    • Max Depth = 32 + Unknown Stack Size +
    • Call Chain = __printf +
    +
    [Calls]
    • >>   _printf_percent +
    • >>   _is_digit +
    +
    [Called By]
    • >>   _printf_char_common +
    + +

    _printf_char_common (Thumb, 32 bytes, Stack size 64 bytes, _printf_char_common.o(.text)) +

    [Stack]

    • Max Depth = 96 + Unknown Stack Size +
    • Call Chain = _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   __printf +
    +
    [Called By]
    • >>   _printf_char_file +
    + +

    ferror (Thumb, 8 bytes, Stack size 0 bytes, ferror.o(.text)) +

    [Called By]

    • >>   _printf_char_file +
    + +

    __user_setup_stackheap (Thumb, 62 bytes, Stack size 8 bytes, sys_stackheap_outer.o(.text)) +

    [Stack]

    • Max Depth = 8 + Unknown Stack Size +
    • Call Chain = __user_setup_stackheap +
    +
    [Calls]
    • >>   __user_initial_stackheap +
    • >>   __user_perproc_libspace +
    +
    [Called By]
    • >>   __rt_entry_sh +
    + +

    exit (Thumb, 12 bytes, Stack size 0 bytes, exit.o(.text)) +

    [Calls]

    • >>   __rt_exit +
    • >>   _call_atexit_fns (Weak Reference) +
    +
    [Called By]
    • >>   __rt_entry_main +
    + +

    __user_libspace (Thumb, 8 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED) + +

    __user_perproc_libspace (Thumb, 0 bytes, Stack size 0 bytes, libspace.o(.text)) +

    [Called By]

    • >>   __user_setup_stackheap +
    + +

    __user_perthread_libspace (Thumb, 0 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED) + +

    _is_digit (Thumb, 14 bytes, Stack size 0 bytes, __printf_wp.o(i._is_digit)) +

    [Called By]

    • >>   __printf +
    +

    +

    +Local Symbols +

    +

    SetSysClock (Thumb, 206 bytes, Stack size 12 bytes, system_stm32f0xx.o(.text)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = SetSysClock +
    +
    [Called By]
    • >>   SystemInit +
    + +

    _printf_input_char (Thumb, 10 bytes, Stack size 0 bytes, _printf_char_common.o(.text)) +
    [Address Reference Count : 1]

    • _printf_char_common.o(.text) +

    +

    +Undefined Global Symbols +

    +

    _call_atexit_fns (ARM, 0 bytes, Stack size 0 bytes, UNDEFINED) +

    [Called By]

    • >>   exit +
    +
    diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/STM32F030Demo.lnp b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/STM32F030Demo.lnp new file mode 100644 index 0000000..050288b --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/STM32F030Demo.lnp @@ -0,0 +1,15 @@ +--cpu Cortex-M0 +"..\obj\main.o" +"..\obj\stm32f0xx_it.o" +"..\obj\system_stm32f0xx.o" +"..\obj\startup_stm32f0xx.o" +"..\obj\led.o" +"..\obj\usart1.o" +"..\obj\delay.o" +"..\obj\stm32f0xx_gpio.o" +"..\obj\stm32f0xx_rcc.o" +"..\obj\stm32f0xx_misc.o" +"..\obj\stm32f0xx_usart.o" +--ro-base 0x08000000 --entry 0x08000000 --rw-base 0x20000000 --entry Reset_Handler --first __Vectors --strict --summary_stderr --info summarysizes --map --xref --callgraph --symbols +--info sizes --info totals --info unused --info veneers +--list ".\STM32F030Demo.map" -o ..\OBJ\STM32F030Demo.axf \ No newline at end of file diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/STM32F030Demo_Stm32f030demo.dep b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/STM32F030Demo_Stm32f030demo.dep new file mode 100644 index 0000000..e41de32 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/STM32F030Demo_Stm32f030demo.dep @@ -0,0 +1,122 @@ +Dependencies for Project 'STM32F030Demo', Target 'Stm32f030demo': (DO NOT MODIFY !) +F (.\main.c)(0x5F8D96A2)(-c --cpu Cortex-M0 -g -W -O0 --apcs=interwork -I ..\CORE -I ..\HARDWARE -I ..\STM32F03x_FWLib\inc -I ..\STM32F03x_FWLib\src -I ..\User -I ..\SYSTEM -I.\RTE\_Stm32f030demo -IF:\tool_setup\ARM\CMSIS\5.3.0\CMSIS\Include -IF:\tool_setup\Keil\STM32F0xx_DFP\2.0.0\Drivers\CMSIS\Device\ST\STM32F0xx\Include -D__UVISION_VERSION="525" -D_RTE_ -DSTM32F030x6 -DUSE_STDPERIPH_DRIVER -DSTM32F0XX -o ..\obj\main.o --omf_browse ..\obj\main.crf --depend ..\obj\main.d) +I (stm32f0xx.h)(0x5C0F2083) +I (..\CORE\core_cm0.h)(0x574D3404) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E) +I (..\CORE\core_cmInstr.h)(0x574D3404) +I (..\CORE\core_cmFunc.h)(0x574D3404) +I (system_stm32f0xx.h)(0x574D3404) +I (stm32f0xx_conf.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_gpio.h)(0x574D3404) +I (..\User\stm32f0xx.h)(0x5C0F2083) +I (..\STM32F03x_FWLib\inc\stm32f0xx_rcc.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_usart.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_misc.h)(0x574D3404) +I (..\SYSTEM\delay.h)(0x574D3404) +I (..\HARDWARE\led.h)(0x5D15B711) +I (..\HARDWARE\USART1.h)(0x574D3404) +I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x599ECD2C) +I (..\HARDWARE\Key.h)(0x574D3404) +F (.\stm32f0xx_it.c)(0x574D3404)(-c --cpu Cortex-M0 -g -W -O0 --apcs=interwork -I ..\CORE -I ..\HARDWARE -I ..\STM32F03x_FWLib\inc -I ..\STM32F03x_FWLib\src -I ..\User -I ..\SYSTEM -I.\RTE\_Stm32f030demo -IF:\tool_setup\ARM\CMSIS\5.3.0\CMSIS\Include -IF:\tool_setup\Keil\STM32F0xx_DFP\2.0.0\Drivers\CMSIS\Device\ST\STM32F0xx\Include -D__UVISION_VERSION="525" -D_RTE_ -DSTM32F030x6 -DUSE_STDPERIPH_DRIVER -DSTM32F0XX -o ..\obj\stm32f0xx_it.o --omf_browse ..\obj\stm32f0xx_it.crf --depend ..\obj\stm32f0xx_it.d) +I (stm32f0xx_it.h)(0x574D3404) +I (stm32f0xx.h)(0x5C0F2083) +I (..\CORE\core_cm0.h)(0x574D3404) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E) +I (..\CORE\core_cmInstr.h)(0x574D3404) +I (..\CORE\core_cmFunc.h)(0x574D3404) +I (system_stm32f0xx.h)(0x574D3404) +I (stm32f0xx_conf.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_gpio.h)(0x574D3404) +I (..\User\stm32f0xx.h)(0x5C0F2083) +I (..\STM32F03x_FWLib\inc\stm32f0xx_rcc.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_usart.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_misc.h)(0x574D3404) +F (.\system_stm32f0xx.c)(0x574D3404)(-c --cpu Cortex-M0 -g -W -O0 --apcs=interwork -I ..\CORE -I ..\HARDWARE -I ..\STM32F03x_FWLib\inc -I ..\STM32F03x_FWLib\src -I ..\User -I ..\SYSTEM -I.\RTE\_Stm32f030demo -IF:\tool_setup\ARM\CMSIS\5.3.0\CMSIS\Include -IF:\tool_setup\Keil\STM32F0xx_DFP\2.0.0\Drivers\CMSIS\Device\ST\STM32F0xx\Include -D__UVISION_VERSION="525" -D_RTE_ -DSTM32F030x6 -DUSE_STDPERIPH_DRIVER -DSTM32F0XX -o ..\obj\system_stm32f0xx.o --omf_browse ..\obj\system_stm32f0xx.crf --depend ..\obj\system_stm32f0xx.d) +I (stm32f0xx.h)(0x5C0F2083) +I (..\CORE\core_cm0.h)(0x574D3404) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E) +I (..\CORE\core_cmInstr.h)(0x574D3404) +I (..\CORE\core_cmFunc.h)(0x574D3404) +I (system_stm32f0xx.h)(0x574D3404) +I (stm32f0xx_conf.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_gpio.h)(0x574D3404) +I (..\User\stm32f0xx.h)(0x5C0F2083) +I (..\STM32F03x_FWLib\inc\stm32f0xx_rcc.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_usart.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_misc.h)(0x574D3404) +F (..\CORE\startup_stm32f0xx.s)(0x574D3404)(--cpu Cortex-M0 -g --apcs=interwork -I.\RTE\_Stm32f030demo -IF:\tool_setup\ARM\CMSIS\5.3.0\CMSIS\Include -IF:\tool_setup\Keil\STM32F0xx_DFP\2.0.0\Drivers\CMSIS\Device\ST\STM32F0xx\Include --pd "__UVISION_VERSION SETA 525" --pd "_RTE_ SETA 1" --pd "STM32F030x6 SETA 1" --list .\startup_stm32f0xx.lst --xref -o ..\obj\startup_stm32f0xx.o --depend ..\obj\startup_stm32f0xx.d) +F (..\HARDWARE\USART1.c)(0x5F8ABBB7)(-c --cpu Cortex-M0 -g -W -O0 --apcs=interwork -I ..\CORE -I ..\HARDWARE -I ..\STM32F03x_FWLib\inc -I ..\STM32F03x_FWLib\src -I ..\User -I ..\SYSTEM -I.\RTE\_Stm32f030demo -IF:\tool_setup\ARM\CMSIS\5.3.0\CMSIS\Include -IF:\tool_setup\Keil\STM32F0xx_DFP\2.0.0\Drivers\CMSIS\Device\ST\STM32F0xx\Include -D__UVISION_VERSION="525" -D_RTE_ -DSTM32F030x6 -DUSE_STDPERIPH_DRIVER -DSTM32F0XX -o ..\obj\usart1.o --omf_browse ..\obj\usart1.crf --depend ..\obj\usart1.d) +I (..\HARDWARE\USART1.h)(0x574D3404) +I (..\User\stm32f0xx.h)(0x5C0F2083) +I (..\CORE\core_cm0.h)(0x574D3404) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E) +I (..\CORE\core_cmInstr.h)(0x574D3404) +I (..\CORE\core_cmFunc.h)(0x574D3404) +I (..\User\system_stm32f0xx.h)(0x574D3404) +I (..\User\stm32f0xx_conf.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_gpio.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_rcc.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_usart.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_misc.h)(0x574D3404) +I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x599ECD2C) +F (..\SYSTEM\delay.c)(0x5F72DB3A)(-c --cpu Cortex-M0 -g -W -O0 --apcs=interwork -I ..\CORE -I ..\HARDWARE -I ..\STM32F03x_FWLib\inc -I ..\STM32F03x_FWLib\src -I ..\User -I ..\SYSTEM -I.\RTE\_Stm32f030demo -IF:\tool_setup\ARM\CMSIS\5.3.0\CMSIS\Include -IF:\tool_setup\Keil\STM32F0xx_DFP\2.0.0\Drivers\CMSIS\Device\ST\STM32F0xx\Include -D__UVISION_VERSION="525" -D_RTE_ -DSTM32F030x6 -DUSE_STDPERIPH_DRIVER -DSTM32F0XX -o ..\obj\delay.o --omf_browse ..\obj\delay.crf --depend ..\obj\delay.d) +I (..\SYSTEM\delay.h)(0x574D3404) +I (..\User\stm32f0xx.h)(0x5C0F2083) +I (..\CORE\core_cm0.h)(0x574D3404) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E) +I (..\CORE\core_cmInstr.h)(0x574D3404) +I (..\CORE\core_cmFunc.h)(0x574D3404) +I (..\User\system_stm32f0xx.h)(0x574D3404) +I (..\User\stm32f0xx_conf.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_gpio.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_rcc.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_usart.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_misc.h)(0x574D3404) +F (..\STM32F03x_FWLib\src\stm32f0xx_gpio.c)(0x574D3404)(-c --cpu Cortex-M0 -g -W -O0 --apcs=interwork -I ..\CORE -I ..\HARDWARE -I ..\STM32F03x_FWLib\inc -I ..\STM32F03x_FWLib\src -I ..\User -I ..\SYSTEM -I.\RTE\_Stm32f030demo -IF:\tool_setup\ARM\CMSIS\5.3.0\CMSIS\Include -IF:\tool_setup\Keil\STM32F0xx_DFP\2.0.0\Drivers\CMSIS\Device\ST\STM32F0xx\Include -D__UVISION_VERSION="525" -D_RTE_ -DSTM32F030x6 -DUSE_STDPERIPH_DRIVER -DSTM32F0XX -o ..\obj\stm32f0xx_gpio.o --omf_browse ..\obj\stm32f0xx_gpio.crf --depend ..\obj\stm32f0xx_gpio.d) +I (..\STM32F03x_FWLib\inc\stm32f0xx_gpio.h)(0x574D3404) +I (..\User\stm32f0xx.h)(0x5C0F2083) +I (..\CORE\core_cm0.h)(0x574D3404) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E) +I (..\CORE\core_cmInstr.h)(0x574D3404) +I (..\CORE\core_cmFunc.h)(0x574D3404) +I (..\User\system_stm32f0xx.h)(0x574D3404) +I (..\User\stm32f0xx_conf.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_rcc.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_usart.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_misc.h)(0x574D3404) +F (..\STM32F03x_FWLib\src\stm32f0xx_rcc.c)(0x574D3404)(-c --cpu Cortex-M0 -g -W -O0 --apcs=interwork -I ..\CORE -I ..\HARDWARE -I ..\STM32F03x_FWLib\inc -I ..\STM32F03x_FWLib\src -I ..\User -I ..\SYSTEM -I.\RTE\_Stm32f030demo -IF:\tool_setup\ARM\CMSIS\5.3.0\CMSIS\Include -IF:\tool_setup\Keil\STM32F0xx_DFP\2.0.0\Drivers\CMSIS\Device\ST\STM32F0xx\Include -D__UVISION_VERSION="525" -D_RTE_ -DSTM32F030x6 -DUSE_STDPERIPH_DRIVER -DSTM32F0XX -o ..\obj\stm32f0xx_rcc.o --omf_browse ..\obj\stm32f0xx_rcc.crf --depend ..\obj\stm32f0xx_rcc.d) +I (..\STM32F03x_FWLib\inc\stm32f0xx_rcc.h)(0x574D3404) +I (..\User\stm32f0xx.h)(0x5C0F2083) +I (..\CORE\core_cm0.h)(0x574D3404) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E) +I (..\CORE\core_cmInstr.h)(0x574D3404) +I (..\CORE\core_cmFunc.h)(0x574D3404) +I (..\User\system_stm32f0xx.h)(0x574D3404) +I (..\User\stm32f0xx_conf.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_gpio.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_usart.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_misc.h)(0x574D3404) +F (..\STM32F03x_FWLib\src\stm32f0xx_misc.c)(0x574D3404)(-c --cpu Cortex-M0 -g -W -O0 --apcs=interwork -I ..\CORE -I ..\HARDWARE -I ..\STM32F03x_FWLib\inc -I ..\STM32F03x_FWLib\src -I ..\User -I ..\SYSTEM -I.\RTE\_Stm32f030demo -IF:\tool_setup\ARM\CMSIS\5.3.0\CMSIS\Include -IF:\tool_setup\Keil\STM32F0xx_DFP\2.0.0\Drivers\CMSIS\Device\ST\STM32F0xx\Include -D__UVISION_VERSION="525" -D_RTE_ -DSTM32F030x6 -DUSE_STDPERIPH_DRIVER -DSTM32F0XX -o ..\obj\stm32f0xx_misc.o --omf_browse ..\obj\stm32f0xx_misc.crf --depend ..\obj\stm32f0xx_misc.d) +I (..\STM32F03x_FWLib\inc\stm32f0xx_misc.h)(0x574D3404) +I (..\User\stm32f0xx.h)(0x5C0F2083) +I (..\CORE\core_cm0.h)(0x574D3404) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E) +I (..\CORE\core_cmInstr.h)(0x574D3404) +I (..\CORE\core_cmFunc.h)(0x574D3404) +I (..\User\system_stm32f0xx.h)(0x574D3404) +I (..\User\stm32f0xx_conf.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_gpio.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_rcc.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_usart.h)(0x574D3404) +F (..\STM32F03x_FWLib\src\stm32f0xx_usart.c)(0x574D3404)(-c --cpu Cortex-M0 -g -W -O0 --apcs=interwork -I ..\CORE -I ..\HARDWARE -I ..\STM32F03x_FWLib\inc -I ..\STM32F03x_FWLib\src -I ..\User -I ..\SYSTEM -I.\RTE\_Stm32f030demo -IF:\tool_setup\ARM\CMSIS\5.3.0\CMSIS\Include -IF:\tool_setup\Keil\STM32F0xx_DFP\2.0.0\Drivers\CMSIS\Device\ST\STM32F0xx\Include -D__UVISION_VERSION="525" -D_RTE_ -DSTM32F030x6 -DUSE_STDPERIPH_DRIVER -DSTM32F0XX -o ..\obj\stm32f0xx_usart.o --omf_browse ..\obj\stm32f0xx_usart.crf --depend ..\obj\stm32f0xx_usart.d) +I (..\STM32F03x_FWLib\inc\stm32f0xx_usart.h)(0x574D3404) +I (..\User\stm32f0xx.h)(0x5C0F2083) +I (..\CORE\core_cm0.h)(0x574D3404) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E) +I (..\CORE\core_cmInstr.h)(0x574D3404) +I (..\CORE\core_cmFunc.h)(0x574D3404) +I (..\User\system_stm32f0xx.h)(0x574D3404) +I (..\User\stm32f0xx_conf.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_gpio.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_rcc.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_misc.h)(0x574D3404) diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/TEST.axf b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/TEST.axf new file mode 100644 index 0000000..57e1c0e Binary files /dev/null and b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/TEST.axf differ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/TEST.build_log.htm b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/TEST.build_log.htm new file mode 100644 index 0000000..f84ce63 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/TEST.build_log.htm @@ -0,0 +1,60 @@ + + +
    +
    Vision Build Log
    
+
    Tool Versions:
    
+IDE-Version: Vision V5.25.2.0
+Copyright (C) 2018 ARM Ltd and ARM Germany GmbH. All rights reserved.
+License Information: 111 Microsoft, Microsoft, LIC=WHY45-G5GRW-G78R6-DUJKC-EYBSC-67VJZ
+ 
+Tool Versions:
+Toolchain:       MDK-ARM Plus  Version: 5.25.2.0
+Toolchain Path:  C:\Keil_v5\ARM\ARMCC\Bin
+C Compiler:      Armcc.exe V5.06 update 6 (build 750)
+Assembler:       Armasm.exe V5.06 update 6 (build 750)
+Linker/Locator:  ArmLink.exe V5.06 update 6 (build 750)
+Library Manager: ArmAr.exe V5.06 update 6 (build 750)
+Hex Converter:   FromElf.exe V5.06 update 6 (build 750)
+CPU DLL:         SARMCM3.DLL V5.25.2.0
+Dialog DLL:      DARMCM1.DLL V1.19.1.0
+Target DLL:      Segger\JL2CM3.dll V2.99.29.0
+Dialog DLL:      TARMCM1.DLL V1.14.0.0
+ 
+
    Project:
    
+G:\SunDisplay\module\2020ϸ\ʾ CN2048  ע\JC144ʾdemo_  STM32F030 UART\JC144  STM32F030 UART\User\STM32F030Demo.uvprojx
+Project File Date:  10/19/2020
+
+
    Output:
    
+*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
+Build target 'Stm32f030demo'
+compiling main.c...
+linking...
+Program Size: Code=8828 RO-data=224 RW-data=60 ZI-data=1652  
+FromELF: creating hex file...
+"..\OBJ\TEST.axf" - 0 Error(s), 0 Warning(s).
+
+
    Software Packages used:
    
+
+Package Vendor: ARM
+                http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack
+                ARM.CMSIS.5.3.0
+                CMSIS (Cortex Microcontroller Software Interface Standard)
+   * Component: CORE Version: 5.1.1
+
+Package Vendor: Keil
+                http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack
+                Keil.STM32F0xx_DFP.2.0.0
+                STMicroelectronics STM32F0 Series Device Support, Drivers and Examples
+
+
    Collection of Component include folders:
    
+  .\RTE\_Stm32f030demo
+  F:\tool_setup\ARM\CMSIS\5.3.0\CMSIS\Include
+  F:\tool_setup\Keil\STM32F0xx_DFP\2.0.0\Drivers\CMSIS\Device\ST\STM32F0xx\Include
+
+
    Collection of Component Files used:
    
+
+   * Component: ARM::CMSIS:CORE:5.1.1
+Build Time Elapsed:  00:00:01
+
    + + diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/TEST.hex b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/TEST.hex new file mode 100644 index 0000000..7b5a841 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/TEST.hex @@ -0,0 +1,573 @@ +:020000040800F2 +:10000000B0060020990A0008950800089708000823 +:1000100000000000000000000000000000000000E0 +:100020000000000000000000000000009B08000825 +:1000300000000000000000009D0800089F08000864 +:10004000AB0A0008AB0A0008AB0A0008AB0A0008BC +:10005000AB0A0008AB0A0008AB0A0008AB0A0008AC +:10006000AB0A0008AB0A0008AB0A0008AB0A00089C +:10007000AB0A0008AB0A0008AB0A0008AB0A00088C +:10008000AB0A0008AB0A000800000000AB0A000839 +:10009000AB0A0008AB0A0008AB0A0008AB0A00086C +:1000A000AB0A0008AB0A0008AB0A0008570F0008AB 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+:102310008D46704710B50446C046C0462046FDF7BE +:1023200022FF10BD004870474C00002030380A28BA +:1023300001D2012070470020704700005C23000894 +:10234000000000203C000000040100089823000861 +:102350003C0000207406000020010008006CDC0234 +:102360000000000000000000010203040607080945 +:10237000000000000000000000000000000000005D +:102380000000000000000000000000000102030443 +:0823900001020304060708091D +:0400000508000A994C +:00000001FF diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/TEST.htm b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/TEST.htm new file mode 100644 index 0000000..3ab29a4 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/TEST.htm @@ -0,0 +1,845 @@ + + +Static Call Graph - [..\OBJ\TEST.axf] +
    +

    Static Call Graph for image ..\OBJ\TEST.axf

    +

    #<CALLGRAPH># ARM Linker, 5060750: Last Updated: Mon Oct 19 21:37:39 2020 +

    +

    Maximum Stack Usage = 264 bytes + Unknown(Functions without stacksize, Cycles, Untraceable Function Pointers)

    +Call chain for Maximum Stack Depth:

    +__rt_entry_main ⇒ main ⇒ USART1_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +

    +

    +Functions with no stack information +

    + +

    +

    +Mutually Recursive functions +

  • ADC1_COMP_IRQHandler   ⇒   ADC1_COMP_IRQHandler
    + +

    +

    +Function Pointers +

      +
    • ADC1_COMP_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • CEC_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • DMA1_Channel1_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • DMA1_Channel2_3_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • DMA1_Channel4_5_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • EXTI0_1_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • EXTI2_3_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • EXTI4_15_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • FLASH_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • HardFault_Handler from stm32f0xx_it.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • I2C1_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • I2C2_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • NMI_Handler from stm32f0xx_it.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • PVD_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • PendSV_Handler from stm32f0xx_it.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • RCC_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • RTC_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • Reset_Handler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • SPI1_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • SPI2_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • SVC_Handler from stm32f0xx_it.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • SysTick_Handler from stm32f0xx_it.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • SystemInit from system_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(.text) +
    • TIM14_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • TIM15_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • TIM16_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • TIM17_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • TIM1_BRK_UP_TRG_COM_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • TIM1_CC_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • TIM2_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • TIM3_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • TIM6_DAC_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • TS_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • USART1_IRQHandler from usart1.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • USART2_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • WWDG_IRQHandler from startup_stm32f0xx.o(.text) referenced from startup_stm32f0xx.o(RESET) +
    • __main from __main.o(!!!main) referenced from startup_stm32f0xx.o(.text) +
    • _printf_input_char from _printf_char_common.o(.text) referenced from _printf_char_common.o(.text) +
    • _sputc from _sputc.o(.text) referenced from noretval__2sprintf.o(.text) +
    +

    +

    +Global Symbols +

    +

    __main (Thumb, 8 bytes, Stack size 0 bytes, __main.o(!!!main)) +

    [Calls]

    • >>   __rt_entry +
    • >>   __scatterload +
    + +

    __scatterload (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter)) +

    [Called By]

    • >>   __main +
    + +

    __scatterload_rt2 (Thumb, 52 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED) +

    [Calls]

    • >>   __rt_entry +
    + +

    __scatterload_rt2_thumb_only (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED) + +

    __scatterload_null (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED) + +

    __scatterload_copy (Thumb, 26 bytes, Stack size unknown bytes, __scatter_copy.o(!!handler_copy), UNUSED) +

    [Calls]

    • >>   __scatterload_copy +
    +
    [Called By]
    • >>   __scatterload_copy +
    + +

    __scatterload_zeroinit (Thumb, 28 bytes, Stack size unknown bytes, __scatter_zi.o(!!handler_zi), UNUSED) + +

    _printf_percent (Thumb, 0 bytes, Stack size unknown bytes, _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000)) +

    [Called By]

    • >>   __printf +
    + +

    _printf_d (Thumb, 0 bytes, Stack size unknown bytes, _printf_d.o(.ARM.Collect$$_printf_percent$$00000009)) +

    [Stack]

    • Max Depth = 88 + Unknown Stack Size +
    • Call Chain = _printf_d ⇒ _printf_int_dec ⇒ _printf_int_common ⇒ _printf_post_padding +
    +
    [Calls]
    • >>   _printf_percent_end +
    • >>   _printf_int_dec +
    + +

    _printf_percent_end (Thumb, 0 bytes, Stack size unknown bytes, _printf_percent_end.o(.ARM.Collect$$_printf_percent$$00000017)) +

    [Called By]

    • >>   _printf_d +
    + +

    __rt_lib_init (Thumb, 0 bytes, Stack size unknown bytes, libinit.o(.ARM.Collect$$libinit$$00000000)) +

    [Called By]

    • >>   __rt_entry_li +
    + +

    __rt_lib_init_alloca_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000002E)) + +

    __rt_lib_init_argv_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000002C)) + +

    __rt_lib_init_atexit_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001B)) + +

    __rt_lib_init_clock_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000021)) + +

    __rt_lib_init_cpp_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000032)) + +

    __rt_lib_init_exceptions_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000030)) + +

    __rt_lib_init_fp_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000002)) + +

    __rt_lib_init_fp_trap_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001F)) + +

    __rt_lib_init_getenv_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000023)) + +

    __rt_lib_init_heap_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000A)) + +

    __rt_lib_init_lc_collate_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000011)) + +

    __rt_lib_init_lc_ctype_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000013)) + +

    __rt_lib_init_lc_monetary_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000015)) + +

    __rt_lib_init_lc_numeric_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000017)) + +

    __rt_lib_init_lc_time_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000019)) + +

    __rt_lib_init_preinit_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000004)) + +

    __rt_lib_init_rand_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000E)) + +

    __rt_lib_init_return (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000033)) + +

    __rt_lib_init_signal_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001D)) + +

    __rt_lib_init_stdio_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000025)) + +

    __rt_lib_init_user_alloc_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000C)) + +

    __rt_lib_shutdown (Thumb, 0 bytes, Stack size unknown bytes, libshutdown.o(.ARM.Collect$$libshutdown$$00000000)) +

    [Called By]

    • >>   __rt_exit_ls +
    + +

    __rt_lib_shutdown_cpp_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000002)) + +

    __rt_lib_shutdown_fp_trap_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000007)) + +

    __rt_lib_shutdown_heap_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F)) + +

    __rt_lib_shutdown_return (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000010)) + +

    __rt_lib_shutdown_signal_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A)) + +

    __rt_lib_shutdown_stdio_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000004)) + +

    __rt_lib_shutdown_user_alloc_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C)) + +

    __rt_entry (Thumb, 0 bytes, Stack size unknown bytes, __rtentry.o(.ARM.Collect$$rtentry$$00000000)) +

    [Called By]

    • >>   __main +
    • >>   __scatterload_rt2 +
    + +

    __rt_entry_presh_1 (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$00000002)) + +

    __rt_entry_sh (Thumb, 0 bytes, Stack size unknown bytes, __rtentry4.o(.ARM.Collect$$rtentry$$00000004)) +

    [Stack]

    • Max Depth = 8 + Unknown Stack Size +
    • Call Chain = __rt_entry_sh ⇒ __user_setup_stackheap +
    +
    [Calls]
    • >>   __user_setup_stackheap +
    + +

    __rt_entry_li (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000A)) +

    [Calls]

    • >>   __rt_lib_init +
    + +

    __rt_entry_postsh_1 (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$00000009)) + +

    __rt_entry_main (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000D)) +

    [Stack]

    • Max Depth = 264 + Unknown Stack Size +
    • Call Chain = __rt_entry_main ⇒ main ⇒ USART1_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   exit +
    • >>   main +
    + +

    __rt_entry_postli_1 (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000C)) + +

    __rt_exit (Thumb, 0 bytes, Stack size unknown bytes, rtexit.o(.ARM.Collect$$rtexit$$00000000)) +

    [Called By]

    • >>   exit +
    + +

    __rt_exit_ls (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000003)) +

    [Calls]

    • >>   __rt_lib_shutdown +
    + +

    __rt_exit_prels_1 (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000002)) + +

    __rt_exit_exit (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000004)) +

    [Calls]

    • >>   _sys_exit +
    + +

    main (Thumb, 1734 bytes, Stack size 128 bytes, main.o(.text)) +

    [Stack]

    • Max Depth = 264 + Unknown Stack Size +
    • Call Chain = main ⇒ USART1_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   __2sprintf +
    • >>   delay_ms +
    • >>   delay_init +
    • >>   UartSend +
    • >>   USART1_Init +
    • >>   CheckBusy +
    +
    [Called By]
    • >>   __rt_entry_main +
    + +

    NMI_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f0xx_it.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    HardFault_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32f0xx_it.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    SVC_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f0xx_it.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    PendSV_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f0xx_it.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    SysTick_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f0xx_it.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    SystemInit (Thumb, 110 bytes, Stack size 8 bytes, system_stm32f0xx.o(.text)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = SystemInit ⇒ SetSysClock +
    +
    [Calls]
    • >>   SetSysClock +
    +
    [Address Reference Count : 1]
    • startup_stm32f0xx.o(.text) +
    +

    SystemCoreClockUpdate (Thumb, 154 bytes, Stack size 24 bytes, system_stm32f0xx.o(.text), UNUSED) +

    [Calls]

    • >>   __aeabi_uidivmod +
    + +

    Reset_Handler (Thumb, 8 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) + +

    ADC1_COMP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +

    [Calls]

    • >>   ADC1_COMP_IRQHandler +
    +
    [Called By]
    • >>   ADC1_COMP_IRQHandler +
    +
    [Address Reference Count : 1]
    • startup_stm32f0xx.o(RESET) +
    +

    CEC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    DMA1_Channel1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    DMA1_Channel2_3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    DMA1_Channel4_5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    EXTI0_1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    EXTI2_3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    EXTI4_15_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    FLASH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    I2C1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    I2C2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    PVD_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    RCC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    RTC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    SPI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    SPI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    TIM14_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    TIM15_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    TIM16_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    TIM17_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    TIM1_BRK_UP_TRG_COM_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    TIM1_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    TIM2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    TIM3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    TIM6_DAC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    TS_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    USART2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    WWDG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f0xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f0xx.o(RESET) +
    +

    __user_initial_stackheap (Thumb, 0 bytes, Stack size unknown bytes, startup_stm32f0xx.o(.text)) +

    [Called By]

    • >>   __user_setup_stackheap +
    + +

    _sys_exit (Thumb, 4 bytes, Stack size 0 bytes, usart1.o(.text)) +

    [Called By]

    • >>   __rt_exit_exit +
    + +

    fputc (Thumb, 22 bytes, Stack size 0 bytes, usart1.o(.text), UNUSED) + +

    USART1_Init (Thumb, 168 bytes, Stack size 48 bytes, usart1.o(.text)) +

    [Stack]

    • Max Depth = 136
    • Call Chain = USART1_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   USART_Init +
    • >>   USART_ITConfig +
    • >>   USART_Cmd +
    • >>   RCC_APB2PeriphClockCmd +
    • >>   RCC_AHBPeriphClockCmd +
    • >>   NVIC_Init +
    • >>   GPIO_PinAFConfig +
    • >>   GPIO_Init +
    +
    [Called By]
    • >>   main +
    + +

    UartGet (Thumb, 26 bytes, Stack size 0 bytes, usart1.o(.text), UNUSED) + +

    CheckBusy (Thumb, 24 bytes, Stack size 0 bytes, usart1.o(.text)) +

    [Called By]

    • >>   main +
    + +

    get_var (Thumb, 76 bytes, Stack size 0 bytes, usart1.o(.text), UNUSED) + +

    getch (Thumb, 186 bytes, Stack size 0 bytes, usart1.o(.text)) +

    [Called By]

    • >>   USART1_IRQHandler +
    + +

    GetValue (Thumb, 608 bytes, Stack size 8 bytes, usart1.o(.text), UNUSED) + +

    UartSend (Thumb, 44 bytes, Stack size 16 bytes, usart1.o(.text)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = UartSend +
    +
    [Calls]
    • >>   USART_SendData +
    • >>   USART_GetFlagStatus +
    +
    [Called By]
    • >>   main +
    + +

    USART1_IRQHandler (Thumb, 32 bytes, Stack size 8 bytes, usart1.o(.text)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = USART1_IRQHandler ⇒ USART_GetITStatus +
    +
    [Calls]
    • >>   USART_ReceiveData +
    • >>   USART_GetITStatus +
    • >>   getch +
    +
    [Address Reference Count : 1]
    • startup_stm32f0xx.o(RESET) +
    +

    delay_init (Thumb, 44 bytes, Stack size 8 bytes, delay.o(.text)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = delay_init +
    +
    [Calls]
    • >>   __aeabi_uidivmod +
    • >>   SysTick_CLKSourceConfig +
    +
    [Called By]
    • >>   main +
    + +

    delay_us (Thumb, 74 bytes, Stack size 0 bytes, delay.o(.text), UNUSED) + +

    delay_ms (Thumb, 74 bytes, Stack size 0 bytes, delay.o(.text)) +

    [Called By]

    • >>   main +
    + +

    GPIO_DeInit (Thumb, 132 bytes, Stack size 8 bytes, stm32f0xx_gpio.o(.text), UNUSED) +

    [Calls]

    • >>   RCC_AHBPeriphResetCmd +
    + +

    GPIO_Init (Thumb, 144 bytes, Stack size 20 bytes, stm32f0xx_gpio.o(.text)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = GPIO_Init +
    +
    [Called By]
    • >>   USART1_Init +
    + +

    GPIO_StructInit (Thumb, 20 bytes, Stack size 0 bytes, stm32f0xx_gpio.o(.text), UNUSED) + +

    GPIO_PinLockConfig (Thumb, 34 bytes, Stack size 8 bytes, stm32f0xx_gpio.o(.text), UNUSED) + +

    GPIO_ReadInputDataBit (Thumb, 20 bytes, Stack size 0 bytes, stm32f0xx_gpio.o(.text), UNUSED) + +

    GPIO_ReadInputData (Thumb, 6 bytes, Stack size 0 bytes, stm32f0xx_gpio.o(.text), UNUSED) + +

    GPIO_ReadOutputDataBit (Thumb, 20 bytes, Stack size 0 bytes, stm32f0xx_gpio.o(.text), UNUSED) + +

    GPIO_ReadOutputData (Thumb, 6 bytes, Stack size 0 bytes, stm32f0xx_gpio.o(.text), UNUSED) + +

    GPIO_SetBits (Thumb, 4 bytes, Stack size 0 bytes, stm32f0xx_gpio.o(.text), UNUSED) + +

    GPIO_ResetBits (Thumb, 4 bytes, Stack size 0 bytes, stm32f0xx_gpio.o(.text), UNUSED) + +

    GPIO_WriteBit (Thumb, 12 bytes, Stack size 0 bytes, stm32f0xx_gpio.o(.text), UNUSED) + +

    GPIO_Write (Thumb, 4 bytes, Stack size 0 bytes, stm32f0xx_gpio.o(.text), UNUSED) + +

    GPIO_PinAFConfig (Thumb, 68 bytes, Stack size 20 bytes, stm32f0xx_gpio.o(.text)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = GPIO_PinAFConfig +
    +
    [Called By]
    • >>   USART1_Init +
    + +

    RCC_DeInit (Thumb, 104 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_HSEConfig (Thumb, 12 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_GetFlagStatus (Thumb, 68 bytes, Stack size 8 bytes, stm32f0xx_rcc.o(.text), UNUSED) +

    [Called By]

    • >>   RCC_WaitForHSEStartUp +
    + +

    RCC_WaitForHSEStartUp (Thumb, 60 bytes, Stack size 16 bytes, stm32f0xx_rcc.o(.text), UNUSED) +

    [Calls]

    • >>   RCC_GetFlagStatus +
    + +

    RCC_AdjustHSICalibrationValue (Thumb, 26 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_HSICmd (Thumb, 32 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_AdjustHSI14CalibrationValue (Thumb, 26 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_HSI14Cmd (Thumb, 32 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_HSI14ADCRequestCmd (Thumb, 32 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_LSEConfig (Thumb, 34 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_LSEDriveConfig (Thumb, 22 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_LSICmd (Thumb, 32 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_PLLConfig (Thumb, 30 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_PLLCmd (Thumb, 36 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_PREDIV1Config (Thumb, 24 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_ClockSecuritySystemCmd (Thumb, 36 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_MCOConfig (Thumb, 6 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_SYSCLKConfig (Thumb, 24 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_GetSYSCLKSource (Thumb, 10 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_HCLKConfig (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_PCLKConfig (Thumb, 30 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_ADCCLKConfig (Thumb, 52 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_CECCLKConfig (Thumb, 22 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_I2CCLKConfig (Thumb, 22 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_USARTCLKConfig (Thumb, 22 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_GetClocksFreq (Thumb, 368 bytes, Stack size 32 bytes, stm32f0xx_rcc.o(.text)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = RCC_GetClocksFreq +
    +
    [Calls]
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   USART_Init +
    + +

    RCC_RTCCLKConfig (Thumb, 12 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_RTCCLKCmd (Thumb, 36 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_BackupResetCmd (Thumb, 36 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_AHBPeriphClockCmd (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text)) +

    [Called By]

    • >>   USART1_Init +
    + +

    RCC_APB2PeriphClockCmd (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text)) +

    [Called By]

    • >>   USART1_Init +
    + +

    RCC_APB1PeriphClockCmd (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_AHBPeriphResetCmd (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) +

    [Called By]

    • >>   GPIO_DeInit +
    + +

    RCC_APB2PeriphResetCmd (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) +

    [Called By]

    • >>   USART_DeInit +
    + +

    RCC_APB1PeriphResetCmd (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) +

    [Called By]

    • >>   USART_DeInit +
    + +

    RCC_ITConfig (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_ClearFlag (Thumb, 16 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_GetITStatus (Thumb, 22 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    RCC_ClearITPendingBit (Thumb, 6 bytes, Stack size 0 bytes, stm32f0xx_rcc.o(.text), UNUSED) + +

    NVIC_Init (Thumb, 106 bytes, Stack size 0 bytes, stm32f0xx_misc.o(.text)) +

    [Called By]

    • >>   USART1_Init +
    + +

    NVIC_SystemLPConfig (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_misc.o(.text), UNUSED) + +

    SysTick_CLKSourceConfig (Thumb, 32 bytes, Stack size 0 bytes, stm32f0xx_misc.o(.text)) +

    [Called By]

    • >>   delay_init +
    + +

    USART_DeInit (Thumb, 56 bytes, Stack size 8 bytes, stm32f0xx_usart.o(.text), UNUSED) +

    [Calls]

    • >>   RCC_APB1PeriphResetCmd +
    • >>   RCC_APB2PeriphResetCmd +
    + +

    USART_Init (Thumb, 234 bytes, Stack size 56 bytes, stm32f0xx_usart.o(.text)) +

    [Stack]

    • Max Depth = 88
    • Call Chain = USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   __aeabi_uidivmod +
    • >>   RCC_GetClocksFreq +
    +
    [Called By]
    • >>   USART1_Init +
    + +

    USART_StructInit (Thumb, 24 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_ClockInit (Thumb, 36 bytes, Stack size 8 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_ClockStructInit (Thumb, 12 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_Cmd (Thumb, 24 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text)) +

    [Called By]

    • >>   USART1_Init +
    + +

    USART_DirectionModeCmd (Thumb, 20 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_OverSampling8Cmd (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_OneBitMethodCmd (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_MSBFirstCmd (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_DataInvCmd (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_InvPinCmd (Thumb, 20 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_SWAPPinCmd (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_ReceiverTimeOutCmd (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_SetReceiverTimeOut (Thumb, 16 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_SetPrescaler (Thumb, 18 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_STOPModeCmd (Thumb, 24 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_StopModeWakeUpSourceConfig (Thumb, 18 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_AutoBaudRateCmd (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_AutoBaudRateConfig (Thumb, 18 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_AutoBaudRateNewRequest (Thumb, 12 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_SendData (Thumb, 8 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text)) +

    [Called By]

    • >>   UartSend +
    + +

    USART_ReceiveData (Thumb, 10 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text)) +

    [Called By]

    • >>   USART1_IRQHandler +
    + +

    USART_SetAddress (Thumb, 18 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_MuteModeCmd (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_MuteModeWakeUpConfig (Thumb, 18 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_AddressDetectionConfig (Thumb, 16 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_LINBreakDetectLengthConfig (Thumb, 16 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_LINCmd (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_HalfDuplexCmd (Thumb, 24 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_SetGuardTime (Thumb, 16 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_SmartCardCmd (Thumb, 24 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_SmartCardNACKCmd (Thumb, 24 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_SetAutoRetryCount (Thumb, 20 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_SetBlockLength (Thumb, 30 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_IrDAConfig (Thumb, 16 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_IrDACmd (Thumb, 24 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_DECmd (Thumb, 28 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_DEPolarityConfig (Thumb, 18 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_SetDEAssertionTime (Thumb, 20 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_SetDEDeassertionTime (Thumb, 20 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_DMACmd (Thumb, 20 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_DMAReceptionErrorConfig (Thumb, 18 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_ITConfig (Thumb, 66 bytes, Stack size 24 bytes, stm32f0xx_usart.o(.text)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = USART_ITConfig +
    +
    [Called By]
    • >>   USART1_Init +
    + +

    USART_RequestCmd (Thumb, 20 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_OverrunDetectionConfig (Thumb, 18 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_GetFlagStatus (Thumb, 20 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text)) +

    [Called By]

    • >>   UartSend +
    + +

    USART_ClearFlag (Thumb, 4 bytes, Stack size 0 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    USART_GetITStatus (Thumb, 78 bytes, Stack size 16 bytes, stm32f0xx_usart.o(.text)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = USART_GetITStatus +
    +
    [Called By]
    • >>   USART1_IRQHandler +
    + +

    USART_ClearITPendingBit (Thumb, 18 bytes, Stack size 8 bytes, stm32f0xx_usart.o(.text), UNUSED) + +

    __use_no_semihosting (Thumb, 2 bytes, Stack size 0 bytes, use_no_semi_2.o(.text), UNUSED) + +

    __2sprintf (Thumb, 36 bytes, Stack size 32 bytes, noretval__2sprintf.o(.text)) +

    [Stack]

    • Max Depth = 128 + Unknown Stack Size +
    • Call Chain = __2sprintf ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   _sputc +
    • >>   _printf_char_common +
    +
    [Called By]
    • >>   main +
    + +

    _printf_pre_padding (Thumb, 44 bytes, Stack size 16 bytes, _printf_pad.o(.text)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = _printf_pre_padding +
    +
    [Called By]
    • >>   _printf_int_common +
    + +

    _printf_post_padding (Thumb, 34 bytes, Stack size 16 bytes, _printf_pad.o(.text)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = _printf_post_padding +
    +
    [Called By]
    • >>   _printf_int_common +
    + +

    _printf_int_dec (Thumb, 90 bytes, Stack size 32 bytes, _printf_dec.o(.text)) +

    [Stack]

    • Max Depth = 88
    • Call Chain = _printf_int_dec ⇒ _printf_int_common ⇒ _printf_post_padding +
    +
    [Calls]
    • >>   __rt_udiv10 +
    • >>   _printf_int_common +
    • >>   _printf_truncate_unsigned (Weak Reference) +
    • >>   _printf_truncate_signed (Weak Reference) +
    +
    [Called By]
    • >>   _printf_d +
    + +

    __printf (Thumb, 270 bytes, Stack size 32 bytes, __printf_wp.o(.text)) +

    [Stack]

    • Max Depth = 32 + Unknown Stack Size +
    • Call Chain = __printf +
    +
    [Calls]
    • >>   _printf_percent +
    • >>   _is_digit +
    +
    [Called By]
    • >>   _printf_char_common +
    + +

    __aeabi_uidiv (Thumb, 0 bytes, Stack size 0 bytes, aeabi_sdiv.o(.text), UNUSED) + +

    __aeabi_uidivmod (Thumb, 20 bytes, Stack size 0 bytes, aeabi_sdiv.o(.text)) +

    [Called By]

    • >>   RCC_GetClocksFreq +
    • >>   USART_Init +
    • >>   SystemCoreClockUpdate +
    • >>   delay_init +
    + +

    __aeabi_idiv (Thumb, 0 bytes, Stack size 8 bytes, aeabi_sdiv.o(.text), UNUSED) + +

    __aeabi_idivmod (Thumb, 326 bytes, Stack size 8 bytes, aeabi_sdiv.o(.text), UNUSED) + +

    __use_two_region_memory (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED) + +

    __rt_heap_escrow$2region (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED) + +

    __rt_heap_expand$2region (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED) + +

    __I$use$semihosting (Thumb, 0 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED) + +

    __use_no_semihosting_swi (Thumb, 2 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED) + +

    _printf_int_common (Thumb, 176 bytes, Stack size 40 bytes, _printf_intcommon.o(.text)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = _printf_int_common ⇒ _printf_post_padding +
    +
    [Calls]
    • >>   _printf_post_padding +
    • >>   _printf_pre_padding +
    +
    [Called By]
    • >>   _printf_int_dec +
    + +

    _printf_char_common (Thumb, 32 bytes, Stack size 64 bytes, _printf_char_common.o(.text)) +

    [Stack]

    • Max Depth = 96 + Unknown Stack Size +
    • Call Chain = _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   __printf +
    +
    [Called By]
    • >>   __2sprintf +
    + +

    _sputc (Thumb, 10 bytes, Stack size 0 bytes, _sputc.o(.text)) +

    [Called By]

    • >>   __2sprintf +
    +
    [Address Reference Count : 1]
    • noretval__2sprintf.o(.text) +
    +

    __rt_udiv10 (Thumb, 40 bytes, Stack size 0 bytes, rtudiv10.o(.text)) +

    [Called By]

    • >>   _printf_int_dec +
    + +

    __user_setup_stackheap (Thumb, 62 bytes, Stack size 8 bytes, sys_stackheap_outer.o(.text)) +

    [Stack]

    • Max Depth = 8 + Unknown Stack Size +
    • Call Chain = __user_setup_stackheap +
    +
    [Calls]
    • >>   __user_perproc_libspace +
    • >>   __user_initial_stackheap +
    +
    [Called By]
    • >>   __rt_entry_sh +
    + +

    exit (Thumb, 16 bytes, Stack size 8 bytes, exit.o(.text)) +

    [Stack]

    • Max Depth = 8 + Unknown Stack Size +
    • Call Chain = exit +
    +
    [Calls]
    • >>   __rt_exit +
    • >>   _call_atexit_fns (Weak Reference) +
    +
    [Called By]
    • >>   __rt_entry_main +
    + +

    __user_libspace (Thumb, 8 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED) + +

    __user_perproc_libspace (Thumb, 0 bytes, Stack size 0 bytes, libspace.o(.text)) +

    [Called By]

    • >>   __user_setup_stackheap +
    + +

    __user_perthread_libspace (Thumb, 0 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED) + +

    _is_digit (Thumb, 14 bytes, Stack size 0 bytes, __printf_wp.o(i._is_digit)) +

    [Called By]

    • >>   __printf +
    +

    +

    +Local Symbols +

    +

    SetSysClock (Thumb, 206 bytes, Stack size 12 bytes, system_stm32f0xx.o(.text)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = SetSysClock +
    +
    [Called By]
    • >>   SystemInit +
    + +

    _printf_input_char (Thumb, 10 bytes, Stack size 0 bytes, _printf_char_common.o(.text)) +
    [Address Reference Count : 1]

    • _printf_char_common.o(.text) +

    +

    +Undefined Global Symbols +

    +

    _call_atexit_fns (ARM, 0 bytes, Stack size 0 bytes, UNDEFINED) +

    [Called By]

    • >>   exit +
    + +

    _printf_truncate_signed (ARM, 0 bytes, Stack size 0 bytes, UNDEFINED) +

    [Called By]

    • >>   _printf_int_dec +
    + +

    _printf_truncate_unsigned (ARM, 0 bytes, Stack size 0 bytes, UNDEFINED) +

    [Called By]

    • >>   _printf_int_dec +
    +
    diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/TEST.lnp b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/TEST.lnp new file mode 100644 index 0000000..fd36cf4 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/TEST.lnp @@ -0,0 +1,14 @@ +--cpu Cortex-M0 +"..\obj\main.o" +"..\obj\stm32f0xx_it.o" +"..\obj\system_stm32f0xx.o" +"..\obj\startup_stm32f0xx.o" +"..\obj\usart1.o" +"..\obj\delay.o" +"..\obj\stm32f0xx_gpio.o" +"..\obj\stm32f0xx_rcc.o" +"..\obj\stm32f0xx_misc.o" +"..\obj\stm32f0xx_usart.o" +--ro-base 0x08000000 --entry 0x08000000 --rw-base 0x20000000 --entry Reset_Handler --first __Vectors --strict --summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols +--info sizes --info totals --info unused --info veneers +--list ".\TEST.map" -o ..\OBJ\TEST.axf \ No newline at end of file diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/delay.crf b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/delay.crf new file mode 100644 index 0000000..ca95c25 Binary files /dev/null and b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/delay.crf differ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/delay.d b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/delay.d new file mode 100644 index 0000000..296dbd2 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/delay.d @@ -0,0 +1,14 @@ +..\obj\delay.o: ..\SYSTEM\delay.c +..\obj\delay.o: ..\SYSTEM\delay.h +..\obj\delay.o: ..\User\stm32f0xx.h +..\obj\delay.o: ..\CORE\core_cm0.h +..\obj\delay.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\delay.o: ..\CORE\core_cmInstr.h +..\obj\delay.o: ..\CORE\core_cmFunc.h +..\obj\delay.o: ..\User\system_stm32f0xx.h +..\obj\delay.o: ..\User\stm32f0xx_conf.h +..\obj\delay.o: ..\STM32F03x_FWLib\inc\stm32f0xx_gpio.h +..\obj\delay.o: ..\User\stm32f0xx.h +..\obj\delay.o: ..\STM32F03x_FWLib\inc\stm32f0xx_rcc.h +..\obj\delay.o: ..\STM32F03x_FWLib\inc\stm32f0xx_usart.h +..\obj\delay.o: ..\STM32F03x_FWLib\inc\stm32f0xx_misc.h diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/delay.o b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/delay.o new file mode 100644 index 0000000..bd497e4 Binary files /dev/null and b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/delay.o differ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/keilkill.bat b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/keilkill.bat new file mode 100644 index 0000000..55fe6bd --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/keilkill.bat @@ -0,0 +1,17 @@ +del *.crf /s +del *.d /s +del *.o /s +del *.htm /s +del *.tra /s +del *.axf /s +del *.lnp /s + +del *.plg /s +del *.iex /s +del *.map /s +del *.dep /s +del *.bak /s +del *.lst /s +del *.uvopt/s +del *.uvgui.*/s +exit diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/key.crf b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/key.crf new file mode 100644 index 0000000..88e49e7 Binary files /dev/null and b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/key.crf differ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/key.d b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/key.d new file mode 100644 index 0000000..39fc6c7 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/key.d @@ -0,0 +1,14 @@ +..\obj\key.o: ..\HARDWARE\Key.c +..\obj\key.o: ..\User\stm32f0xx.h +..\obj\key.o: ..\CORE\core_cm0.h +..\obj\key.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\key.o: ..\CORE\core_cmInstr.h +..\obj\key.o: ..\CORE\core_cmFunc.h +..\obj\key.o: ..\User\system_stm32f0xx.h +..\obj\key.o: ..\User\stm32f0xx_conf.h +..\obj\key.o: ..\STM32F03x_FWLib\inc\stm32f0xx_gpio.h +..\obj\key.o: ..\User\stm32f0xx.h +..\obj\key.o: ..\STM32F03x_FWLib\inc\stm32f0xx_rcc.h +..\obj\key.o: ..\STM32F03x_FWLib\inc\stm32f0xx_usart.h +..\obj\key.o: ..\STM32F03x_FWLib\inc\stm32f0xx_misc.h +..\obj\key.o: ..\SYSTEM\delay.h diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/key.o b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/key.o new file mode 100644 index 0000000..6761eb8 Binary files /dev/null and b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/key.o differ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/led.crf b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/led.crf new file mode 100644 index 0000000..de063ce Binary files /dev/null and b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/led.crf differ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/led.d b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/led.d new file mode 100644 index 0000000..77363ac --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/led.d @@ -0,0 +1,14 @@ +..\obj\led.o: ..\HARDWARE\led.c +..\obj\led.o: ..\HARDWARE\LED.h +..\obj\led.o: ..\User\stm32f0xx.h +..\obj\led.o: ..\CORE\core_cm0.h +..\obj\led.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\led.o: ..\CORE\core_cmInstr.h +..\obj\led.o: ..\CORE\core_cmFunc.h +..\obj\led.o: ..\User\system_stm32f0xx.h +..\obj\led.o: ..\User\stm32f0xx_conf.h +..\obj\led.o: ..\STM32F03x_FWLib\inc\stm32f0xx_gpio.h +..\obj\led.o: ..\User\stm32f0xx.h +..\obj\led.o: ..\STM32F03x_FWLib\inc\stm32f0xx_rcc.h +..\obj\led.o: ..\STM32F03x_FWLib\inc\stm32f0xx_usart.h +..\obj\led.o: ..\STM32F03x_FWLib\inc\stm32f0xx_misc.h diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/led.o b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/led.o new file mode 100644 index 0000000..3d47878 Binary files /dev/null and b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/led.o differ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/main.crf b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/main.crf new file mode 100644 index 0000000..7d5784c Binary files /dev/null and b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/main.crf differ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/main.d b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/main.d new file mode 100644 index 0000000..19179a2 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/main.d @@ -0,0 +1,18 @@ +..\obj\main.o: main.c +..\obj\main.o: stm32f0xx.h +..\obj\main.o: ..\CORE\core_cm0.h +..\obj\main.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\main.o: ..\CORE\core_cmInstr.h +..\obj\main.o: ..\CORE\core_cmFunc.h +..\obj\main.o: system_stm32f0xx.h +..\obj\main.o: stm32f0xx_conf.h +..\obj\main.o: ..\STM32F03x_FWLib\inc\stm32f0xx_gpio.h +..\obj\main.o: ..\User\stm32f0xx.h +..\obj\main.o: ..\STM32F03x_FWLib\inc\stm32f0xx_rcc.h +..\obj\main.o: ..\STM32F03x_FWLib\inc\stm32f0xx_usart.h +..\obj\main.o: ..\STM32F03x_FWLib\inc\stm32f0xx_misc.h +..\obj\main.o: ..\SYSTEM\delay.h +..\obj\main.o: ..\HARDWARE\led.h +..\obj\main.o: ..\HARDWARE\USART1.h +..\obj\main.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h +..\obj\main.o: ..\HARDWARE\Key.h diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/main.o b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/main.o new file mode 100644 index 0000000..3648874 Binary files /dev/null and b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/main.o differ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/startup_stm32f0xx.d b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/startup_stm32f0xx.d new file mode 100644 index 0000000..35ffc43 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/startup_stm32f0xx.d @@ -0,0 +1 @@ +..\obj\startup_stm32f0xx.o: ..\CORE\startup_stm32f0xx.s diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/startup_stm32f0xx.o b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/startup_stm32f0xx.o new file mode 100644 index 0000000..14c9ae0 Binary files /dev/null and b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/startup_stm32f0xx.o differ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_gpio.crf b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_gpio.crf new file mode 100644 index 0000000..cc51b29 Binary files /dev/null and b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_gpio.crf differ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_gpio.d b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_gpio.d new file mode 100644 index 0000000..1f9ca5c --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_gpio.d @@ -0,0 +1,14 @@ +..\obj\stm32f0xx_gpio.o: ..\STM32F03x_FWLib\src\stm32f0xx_gpio.c +..\obj\stm32f0xx_gpio.o: ..\STM32F03x_FWLib\inc\stm32f0xx_gpio.h +..\obj\stm32f0xx_gpio.o: ..\User\stm32f0xx.h +..\obj\stm32f0xx_gpio.o: ..\CORE\core_cm0.h +..\obj\stm32f0xx_gpio.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\stm32f0xx_gpio.o: ..\CORE\core_cmInstr.h +..\obj\stm32f0xx_gpio.o: ..\CORE\core_cmFunc.h +..\obj\stm32f0xx_gpio.o: ..\User\system_stm32f0xx.h +..\obj\stm32f0xx_gpio.o: ..\User\stm32f0xx_conf.h +..\obj\stm32f0xx_gpio.o: ..\STM32F03x_FWLib\inc\stm32f0xx_gpio.h +..\obj\stm32f0xx_gpio.o: ..\STM32F03x_FWLib\inc\stm32f0xx_rcc.h +..\obj\stm32f0xx_gpio.o: ..\User\stm32f0xx.h +..\obj\stm32f0xx_gpio.o: ..\STM32F03x_FWLib\inc\stm32f0xx_usart.h +..\obj\stm32f0xx_gpio.o: ..\STM32F03x_FWLib\inc\stm32f0xx_misc.h diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_gpio.o b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_gpio.o new file mode 100644 index 0000000..7785651 Binary files /dev/null and b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_gpio.o differ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_it.crf b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_it.crf new file mode 100644 index 0000000..5283bee Binary files /dev/null and b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_it.crf differ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_it.d b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_it.d new file mode 100644 index 0000000..0646dfd --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_it.d @@ -0,0 +1,14 @@ +..\obj\stm32f0xx_it.o: stm32f0xx_it.c +..\obj\stm32f0xx_it.o: stm32f0xx_it.h +..\obj\stm32f0xx_it.o: stm32f0xx.h +..\obj\stm32f0xx_it.o: ..\CORE\core_cm0.h +..\obj\stm32f0xx_it.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\stm32f0xx_it.o: ..\CORE\core_cmInstr.h +..\obj\stm32f0xx_it.o: ..\CORE\core_cmFunc.h +..\obj\stm32f0xx_it.o: system_stm32f0xx.h +..\obj\stm32f0xx_it.o: stm32f0xx_conf.h +..\obj\stm32f0xx_it.o: ..\STM32F03x_FWLib\inc\stm32f0xx_gpio.h +..\obj\stm32f0xx_it.o: ..\User\stm32f0xx.h +..\obj\stm32f0xx_it.o: ..\STM32F03x_FWLib\inc\stm32f0xx_rcc.h +..\obj\stm32f0xx_it.o: ..\STM32F03x_FWLib\inc\stm32f0xx_usart.h +..\obj\stm32f0xx_it.o: ..\STM32F03x_FWLib\inc\stm32f0xx_misc.h diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_it.o b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_it.o new file mode 100644 index 0000000..95fc5b8 Binary files /dev/null and b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_it.o differ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_misc.crf b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_misc.crf new file mode 100644 index 0000000..51ade6c Binary files /dev/null and b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_misc.crf differ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_misc.d b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_misc.d new file mode 100644 index 0000000..99139da --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_misc.d @@ -0,0 +1,14 @@ +..\obj\stm32f0xx_misc.o: ..\STM32F03x_FWLib\src\stm32f0xx_misc.c +..\obj\stm32f0xx_misc.o: ..\STM32F03x_FWLib\inc\stm32f0xx_misc.h +..\obj\stm32f0xx_misc.o: ..\User\stm32f0xx.h +..\obj\stm32f0xx_misc.o: ..\CORE\core_cm0.h +..\obj\stm32f0xx_misc.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\stm32f0xx_misc.o: ..\CORE\core_cmInstr.h +..\obj\stm32f0xx_misc.o: ..\CORE\core_cmFunc.h +..\obj\stm32f0xx_misc.o: ..\User\system_stm32f0xx.h +..\obj\stm32f0xx_misc.o: ..\User\stm32f0xx_conf.h +..\obj\stm32f0xx_misc.o: ..\STM32F03x_FWLib\inc\stm32f0xx_gpio.h +..\obj\stm32f0xx_misc.o: ..\User\stm32f0xx.h +..\obj\stm32f0xx_misc.o: ..\STM32F03x_FWLib\inc\stm32f0xx_rcc.h +..\obj\stm32f0xx_misc.o: ..\STM32F03x_FWLib\inc\stm32f0xx_usart.h +..\obj\stm32f0xx_misc.o: ..\STM32F03x_FWLib\inc\stm32f0xx_misc.h diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_misc.o b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_misc.o new file mode 100644 index 0000000..d5e6f98 Binary files /dev/null and b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_misc.o differ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_rcc.crf b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_rcc.crf new file mode 100644 index 0000000..e16ec36 Binary files /dev/null and b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_rcc.crf differ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_rcc.d b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_rcc.d new file mode 100644 index 0000000..d339a1d --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_rcc.d @@ -0,0 +1,14 @@ +..\obj\stm32f0xx_rcc.o: ..\STM32F03x_FWLib\src\stm32f0xx_rcc.c +..\obj\stm32f0xx_rcc.o: ..\STM32F03x_FWLib\inc\stm32f0xx_rcc.h +..\obj\stm32f0xx_rcc.o: ..\User\stm32f0xx.h +..\obj\stm32f0xx_rcc.o: ..\CORE\core_cm0.h +..\obj\stm32f0xx_rcc.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\stm32f0xx_rcc.o: ..\CORE\core_cmInstr.h +..\obj\stm32f0xx_rcc.o: ..\CORE\core_cmFunc.h +..\obj\stm32f0xx_rcc.o: ..\User\system_stm32f0xx.h +..\obj\stm32f0xx_rcc.o: ..\User\stm32f0xx_conf.h +..\obj\stm32f0xx_rcc.o: ..\STM32F03x_FWLib\inc\stm32f0xx_gpio.h +..\obj\stm32f0xx_rcc.o: ..\User\stm32f0xx.h +..\obj\stm32f0xx_rcc.o: ..\STM32F03x_FWLib\inc\stm32f0xx_rcc.h +..\obj\stm32f0xx_rcc.o: ..\STM32F03x_FWLib\inc\stm32f0xx_usart.h +..\obj\stm32f0xx_rcc.o: ..\STM32F03x_FWLib\inc\stm32f0xx_misc.h diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 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UART/OBJ/stm32f0xx_usart.d b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_usart.d new file mode 100644 index 0000000..2c05be9 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_usart.d @@ -0,0 +1,14 @@ +..\obj\stm32f0xx_usart.o: ..\STM32F03x_FWLib\src\stm32f0xx_usart.c +..\obj\stm32f0xx_usart.o: ..\STM32F03x_FWLib\inc\stm32f0xx_usart.h +..\obj\stm32f0xx_usart.o: ..\User\stm32f0xx.h +..\obj\stm32f0xx_usart.o: ..\CORE\core_cm0.h +..\obj\stm32f0xx_usart.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\stm32f0xx_usart.o: ..\CORE\core_cmInstr.h +..\obj\stm32f0xx_usart.o: ..\CORE\core_cmFunc.h +..\obj\stm32f0xx_usart.o: ..\User\system_stm32f0xx.h +..\obj\stm32f0xx_usart.o: ..\User\stm32f0xx_conf.h +..\obj\stm32f0xx_usart.o: ..\STM32F03x_FWLib\inc\stm32f0xx_gpio.h +..\obj\stm32f0xx_usart.o: ..\User\stm32f0xx.h +..\obj\stm32f0xx_usart.o: ..\STM32F03x_FWLib\inc\stm32f0xx_rcc.h +..\obj\stm32f0xx_usart.o: ..\STM32F03x_FWLib\inc\stm32f0xx_usart.h +..\obj\stm32f0xx_usart.o: ..\STM32F03x_FWLib\inc\stm32f0xx_misc.h diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_usart.o b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_usart.o new file mode 100644 index 0000000..eddfa2f Binary files /dev/null and b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/stm32f0xx_usart.o differ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/system_stm32f0xx.crf b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/system_stm32f0xx.crf new file mode 100644 index 0000000..94407b7 Binary files /dev/null and b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/system_stm32f0xx.crf differ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/system_stm32f0xx.d b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/system_stm32f0xx.d new file mode 100644 index 0000000..275523e --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/system_stm32f0xx.d @@ -0,0 +1,13 @@ +..\obj\system_stm32f0xx.o: system_stm32f0xx.c +..\obj\system_stm32f0xx.o: stm32f0xx.h +..\obj\system_stm32f0xx.o: ..\CORE\core_cm0.h +..\obj\system_stm32f0xx.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\system_stm32f0xx.o: ..\CORE\core_cmInstr.h +..\obj\system_stm32f0xx.o: ..\CORE\core_cmFunc.h +..\obj\system_stm32f0xx.o: system_stm32f0xx.h +..\obj\system_stm32f0xx.o: stm32f0xx_conf.h +..\obj\system_stm32f0xx.o: ..\STM32F03x_FWLib\inc\stm32f0xx_gpio.h +..\obj\system_stm32f0xx.o: ..\User\stm32f0xx.h +..\obj\system_stm32f0xx.o: ..\STM32F03x_FWLib\inc\stm32f0xx_rcc.h +..\obj\system_stm32f0xx.o: ..\STM32F03x_FWLib\inc\stm32f0xx_usart.h +..\obj\system_stm32f0xx.o: ..\STM32F03x_FWLib\inc\stm32f0xx_misc.h diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/system_stm32f0xx.o b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/system_stm32f0xx.o new file mode 100644 index 0000000..2b2e29e Binary files /dev/null and b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/system_stm32f0xx.o differ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/usart1.crf b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/usart1.crf new file mode 100644 index 0000000..0f9b47d Binary files /dev/null and b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/usart1.crf differ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/usart1.d b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/usart1.d new file mode 100644 index 0000000..b499e4c --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/usart1.d @@ -0,0 +1,15 @@ +..\obj\usart1.o: ..\HARDWARE\USART1.c +..\obj\usart1.o: ..\HARDWARE\USART1.h +..\obj\usart1.o: ..\User\stm32f0xx.h +..\obj\usart1.o: ..\CORE\core_cm0.h +..\obj\usart1.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\usart1.o: ..\CORE\core_cmInstr.h +..\obj\usart1.o: ..\CORE\core_cmFunc.h +..\obj\usart1.o: ..\User\system_stm32f0xx.h +..\obj\usart1.o: ..\User\stm32f0xx_conf.h +..\obj\usart1.o: ..\STM32F03x_FWLib\inc\stm32f0xx_gpio.h +..\obj\usart1.o: ..\User\stm32f0xx.h +..\obj\usart1.o: ..\STM32F03x_FWLib\inc\stm32f0xx_rcc.h +..\obj\usart1.o: ..\STM32F03x_FWLib\inc\stm32f0xx_usart.h +..\obj\usart1.o: ..\STM32F03x_FWLib\inc\stm32f0xx_misc.h +..\obj\usart1.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/usart1.o b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/usart1.o new file mode 100644 index 0000000..269800a Binary files /dev/null and b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/usart1.o differ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/usart1_api.crf b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/usart1_api.crf new file mode 100644 index 0000000..3073025 Binary files /dev/null and b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/usart1_api.crf differ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/usart1_api.d b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/usart1_api.d new file mode 100644 index 0000000..54a1c7f --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/usart1_api.d @@ -0,0 +1,15 @@ +..\obj\usart1_api.o: ..\HARDWARE\USART1_API.c +..\obj\usart1_api.o: ..\HARDWARE\USART1.h +..\obj\usart1_api.o: ..\User\stm32f0xx.h +..\obj\usart1_api.o: ..\CORE\core_cm0.h +..\obj\usart1_api.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\usart1_api.o: ..\CORE\core_cmInstr.h +..\obj\usart1_api.o: ..\CORE\core_cmFunc.h +..\obj\usart1_api.o: ..\User\system_stm32f0xx.h +..\obj\usart1_api.o: ..\User\stm32f0xx_conf.h +..\obj\usart1_api.o: ..\STM32F03x_FWLib\inc\stm32f0xx_gpio.h +..\obj\usart1_api.o: ..\User\stm32f0xx.h +..\obj\usart1_api.o: ..\STM32F03x_FWLib\inc\stm32f0xx_rcc.h +..\obj\usart1_api.o: ..\STM32F03x_FWLib\inc\stm32f0xx_usart.h +..\obj\usart1_api.o: ..\STM32F03x_FWLib\inc\stm32f0xx_misc.h +..\obj\usart1_api.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/usart1_api.o b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/usart1_api.o new file mode 100644 index 0000000..f709995 Binary files /dev/null and b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/OBJ/usart1_api.o differ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_adc.h b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_adc.h new file mode 100644 index 0000000..4f466e2 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_adc.h @@ -0,0 +1,432 @@ +/** + ****************************************************************************** + * @file stm32f0xx_adc.h + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file contains all the functions prototypes for the ADC firmware + * library + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_ADC_H +#define __STM32F0XX_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief ADC Init structure definition + */ + +typedef struct +{ + uint32_t ADC_Resolution; /*!< Selects the resolution of the conversion. + This parameter can be a value of @ref ADC_Resolution */ + + FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in + Continuous or Single mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ADC_ExternalTrigConvEdge; /*!< Selects the external trigger Edge and enables the + trigger of a regular group. This parameter can be a value + of @ref ADC_external_trigger_edge_conversion */ + + uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog + to digital conversion of regular channels. This parameter + can be a value of @ref ADC_external_trigger_sources_for_channels_conversion */ + + uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right. + This parameter can be a value of @ref ADC_data_align */ + + uint32_t ADC_ScanDirection; /*!< Specifies in which direction the channels will be scanned + in the sequence. + This parameter can be a value of @ref ADC_Scan_Direction */ +}ADC_InitTypeDef; + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Constants + * @{ + */ +#define IS_ADC_ALL_PERIPH(PERIPH) ((PERIPH) == ADC1) + +/** @defgroup ADC_JitterOff + * @{ + */ +#define ADC_JitterOff_PCLKDiv2 ADC_CFGR2_JITOFFDIV2 +#define ADC_JitterOff_PCLKDiv4 ADC_CFGR2_JITOFFDIV4 + +#define IS_ADC_JITTEROFF(JITTEROFF) (((JITTEROFF) & 0x3FFFFFFF) == (uint32_t)RESET) + +/** + * @} + */ + +/** @defgroup ADC_Resolution + * @{ + */ +#define ADC_Resolution_12b ((uint32_t)0x00000000) +#define ADC_Resolution_10b ADC_CFGR1_RES_0 +#define ADC_Resolution_8b ADC_CFGR1_RES_1 +#define ADC_Resolution_6b ADC_CFGR1_RES + +#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \ + ((RESOLUTION) == ADC_Resolution_10b) || \ + ((RESOLUTION) == ADC_Resolution_8b) || \ + ((RESOLUTION) == ADC_Resolution_6b)) + +/** + * @} + */ + +/** @defgroup ADC_external_trigger_edge_conversion + * @{ + */ +#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000) +#define ADC_ExternalTrigConvEdge_Rising ADC_CFGR1_EXTEN_0 +#define ADC_ExternalTrigConvEdge_Falling ADC_CFGR1_EXTEN_1 +#define ADC_ExternalTrigConvEdge_RisingFalling ADC_CFGR1_EXTEN + +#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \ + ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \ + ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \ + ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling)) +/** + * @} + */ + +/** @defgroup ADC_external_trigger_sources_for_channels_conversion + * @{ + */ + +/* TIM1 */ +#define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T1_CC4 ADC_CFGR1_EXTSEL_0 + +/* TIM2 */ +#define ADC_ExternalTrigConv_T2_TRGO ADC_CFGR1_EXTSEL_1 + +/* TIM3 */ +#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_0 | ADC_CFGR1_EXTSEL_1)) + +/* TIM15 */ +#define ADC_ExternalTrigConv_T15_TRGO ADC_CFGR1_EXTSEL_2 + +#define IS_ADC_EXTERNAL_TRIG_CONV(CONV) (((CONV) == ADC_ExternalTrigConv_T1_TRGO) || \ + ((CONV) == ADC_ExternalTrigConv_T1_CC4) || \ + ((CONV) == ADC_ExternalTrigConv_T2_TRGO) || \ + ((CONV) == ADC_ExternalTrigConv_T3_TRGO) || \ + ((CONV) == ADC_ExternalTrigConv_T15_TRGO)) +/** + * @} + */ + +/** @defgroup ADC_data_align + * @{ + */ + +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ADC_CFGR1_ALIGN + +#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ + ((ALIGN) == ADC_DataAlign_Left)) +/** + * @} + */ + +/** @defgroup ADC_Scan_Direction + * @{ + */ + +#define ADC_ScanDirection_Upward ((uint32_t)0x00000000) +#define ADC_ScanDirection_Backward ADC_CFGR1_SCANDIR + +#define IS_ADC_SCAN_DIRECTION(DIRECTION) (((DIRECTION) == ADC_ScanDirection_Upward) || \ + ((DIRECTION) == ADC_ScanDirection_Backward)) +/** + * @} + */ + +/** @defgroup ADC_Scan_Direction + * @{ + */ + +#define ADC_DMAMode_OneShot ((uint32_t)0x00000000) +#define ADC_DMAMode_Circular ADC_CFGR1_DMACFG + +#define IS_ADC_DMA_MODE(MODE) (((MODE) == ADC_DMAMode_OneShot) || \ + ((MODE) == ADC_DMAMode_Circular)) +/** + * @} + */ + +/** @defgroup ADC_analog_watchdog_selection + * @{ + */ + +#define ADC_AnalogWatchdog_Channel_0 ((uint32_t)0x00000000) +#define ADC_AnalogWatchdog_Channel_1 ((uint32_t)0x04000000) +#define ADC_AnalogWatchdog_Channel_2 ((uint32_t)0x08000000) +#define ADC_AnalogWatchdog_Channel_3 ((uint32_t)0x0C000000) +#define ADC_AnalogWatchdog_Channel_4 ((uint32_t)0x10000000) +#define ADC_AnalogWatchdog_Channel_5 ((uint32_t)0x14000000) +#define ADC_AnalogWatchdog_Channel_6 ((uint32_t)0x18000000) +#define ADC_AnalogWatchdog_Channel_7 ((uint32_t)0x1C000000) +#define ADC_AnalogWatchdog_Channel_8 ((uint32_t)0x20000000) +#define ADC_AnalogWatchdog_Channel_9 ((uint32_t)0x24000000) +#define ADC_AnalogWatchdog_Channel_10 ((uint32_t)0x28000000) +#define ADC_AnalogWatchdog_Channel_11 ((uint32_t)0x2C000000) +#define ADC_AnalogWatchdog_Channel_12 ((uint32_t)0x30000000) +#define ADC_AnalogWatchdog_Channel_13 ((uint32_t)0x34000000) +#define ADC_AnalogWatchdog_Channel_14 ((uint32_t)0x38000000) +#define ADC_AnalogWatchdog_Channel_15 ((uint32_t)0x3C000000) +#define ADC_AnalogWatchdog_Channel_16 ((uint32_t)0x40000000) +#define ADC_AnalogWatchdog_Channel_17 ((uint32_t)0x44000000) +#define ADC_AnalogWatchdog_Channel_18 ((uint32_t)0x48000000) + + +#define IS_ADC_ANALOG_WATCHDOG_CHANNEL(CHANNEL) (((CHANNEL) == ADC_AnalogWatchdog_Channel_0) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_1) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_2) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_3) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_4) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_5) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_6) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_7) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_8) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_9) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_10) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_11) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_12) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_13) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_14) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_15) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_16) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_17) || \ + ((CHANNEL) == ADC_AnalogWatchdog_Channel_18)) +/** + * @} + */ + +/** @defgroup ADC_sampling_times + * @{ + */ + +#define ADC_SampleTime_1_5Cycles ((uint32_t)0x00000000) +#define ADC_SampleTime_7_5Cycles ((uint32_t)0x00000001) +#define ADC_SampleTime_13_5Cycles ((uint32_t)0x00000002) +#define ADC_SampleTime_28_5Cycles ((uint32_t)0x00000003) +#define ADC_SampleTime_41_5Cycles ((uint32_t)0x00000004) +#define ADC_SampleTime_55_5Cycles ((uint32_t)0x00000005) +#define ADC_SampleTime_71_5Cycles ((uint32_t)0x00000006) +#define ADC_SampleTime_239_5Cycles ((uint32_t)0x00000007) + +#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1_5Cycles) || \ + ((TIME) == ADC_SampleTime_7_5Cycles) || \ + ((TIME) == ADC_SampleTime_13_5Cycles) || \ + ((TIME) == ADC_SampleTime_28_5Cycles) || \ + ((TIME) == ADC_SampleTime_41_5Cycles) || \ + ((TIME) == ADC_SampleTime_55_5Cycles) || \ + ((TIME) == ADC_SampleTime_71_5Cycles) || \ + ((TIME) == ADC_SampleTime_239_5Cycles)) +/** + * @} + */ + +/** @defgroup ADC_thresholds + * @{ + */ + +#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) + +/** + * @} + */ + +/** @defgroup ADC_channels + * @{ + */ + +#define ADC_Channel_0 ADC_CHSELR_CHSEL0 +#define ADC_Channel_1 ADC_CHSELR_CHSEL1 +#define ADC_Channel_2 ADC_CHSELR_CHSEL2 +#define ADC_Channel_3 ADC_CHSELR_CHSEL3 +#define ADC_Channel_4 ADC_CHSELR_CHSEL4 +#define ADC_Channel_5 ADC_CHSELR_CHSEL5 +#define ADC_Channel_6 ADC_CHSELR_CHSEL6 +#define ADC_Channel_7 ADC_CHSELR_CHSEL7 +#define ADC_Channel_8 ADC_CHSELR_CHSEL8 +#define ADC_Channel_9 ADC_CHSELR_CHSEL9 +#define ADC_Channel_10 ADC_CHSELR_CHSEL10 +#define ADC_Channel_11 ADC_CHSELR_CHSEL11 +#define ADC_Channel_12 ADC_CHSELR_CHSEL12 +#define ADC_Channel_13 ADC_CHSELR_CHSEL13 +#define ADC_Channel_14 ADC_CHSELR_CHSEL14 +#define ADC_Channel_15 ADC_CHSELR_CHSEL15 +#define ADC_Channel_16 ADC_CHSELR_CHSEL16 +#define ADC_Channel_17 ADC_CHSELR_CHSEL17 +#define ADC_Channel_18 ADC_CHSELR_CHSEL18 + +#define ADC_Channel_TempSensor ((uint32_t)ADC_Channel_16) +#define ADC_Channel_Vrefint ((uint32_t)ADC_Channel_17) +#define ADC_Channel_Vbat ((uint32_t)ADC_Channel_18) + +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) != (uint32_t)RESET) && (((CHANNEL) & 0xFFF80000) == (uint32_t)RESET)) + +/** + * @} + */ + +/** @defgroup ADC_interrupts_definition + * @{ + */ + +#define ADC_IT_ADRDY ADC_IER_ADRDYIE +#define ADC_IT_EOSMP ADC_IER_EOSMPIE +#define ADC_IT_EOC ADC_IER_EOCIE +#define ADC_IT_EOSEQ ADC_IER_EOSEQIE +#define ADC_IT_OVR ADC_IER_OVRIE +#define ADC_IT_AWD ADC_IER_AWDIE + +#define IS_ADC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFFF60) == (uint32_t)RESET)) + +#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_ADRDY) || ((IT) == ADC_IT_EOSMP) || \ + ((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_EOSEQ) || \ + ((IT) == ADC_IT_OVR) || ((IT) == ADC_IT_AWD)) + +#define IS_ADC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFFF60) == (uint32_t)RESET)) + +/** + * @} + */ + +/** @defgroup ADC_flags_definition + * @{ + */ + +#define ADC_FLAG_ADRDY ADC_ISR_ADRDY +#define ADC_FLAG_EOSMP ADC_ISR_EOSMP +#define ADC_FLAG_EOC ADC_ISR_EOC +#define ADC_FLAG_EOSEQ ADC_ISR_EOSEQ +#define ADC_FLAG_OVR ADC_ISR_OVR +#define ADC_FLAG_AWD ADC_ISR_AWD + +#define ADC_FLAG_ADEN ((uint32_t)0x01000001) +#define ADC_FLAG_ADDIS ((uint32_t)0x01000002) +#define ADC_FLAG_ADSTART ((uint32_t)0x01000004) +#define ADC_FLAG_ADSTP ((uint32_t)0x01000008) +#define ADC_FLAG_ADCAL ((uint32_t)0x11000000) + +#define IS_ADC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xEFFFFF60) == (uint32_t)RESET)) + +#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_ADRDY) || ((FLAG) == ADC_FLAG_EOSMP) || \ + ((FLAG) == ADC_FLAG_EOC) || ((FLAG)== ADC_FLAG_EOSEQ) || \ + ((FLAG) == ADC_FLAG_AWD) || ((FLAG)== ADC_FLAG_OVR) || \ + ((FLAG) == ADC_FLAG_ADEN) || ((FLAG)== ADC_FLAG_ADDIS) || \ + ((FLAG) == ADC_FLAG_ADSTART) || ((FLAG)== ADC_FLAG_ADSTP) || \ + ((FLAG) == ADC_FLAG_ADCAL)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Function used to set the ADC configuration to the default reset state *****/ +void ADC_DeInit(ADC_TypeDef* ADCx); + +/* Initialization and Configuration functions *********************************/ +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); +void ADC_JitterCmd(ADC_TypeDef* ADCx, uint32_t ADC_JitterOff, FunctionalState NewState); +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); + +/* Power saving functions *****************************************************/ +void ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_WaitModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); + +/* Analog Watchdog configuration functions ************************************/ +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold); +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog_Channel); +void ADC_AnalogWatchdogSingleChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState); + +/* Temperature Sensor , Vrefint and Vbat management function ******************/ +void ADC_TempSensorCmd(FunctionalState NewState); +void ADC_VrefintCmd(FunctionalState NewState); +void ADC_VbatCmd(FunctionalState NewState); + +/* Channels Configuration functions *******************************************/ +void ADC_ChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_Channel, uint32_t ADC_SampleTime); +void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_OverrunModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +uint32_t ADC_GetCalibrationFactor(ADC_TypeDef* ADCx); +void ADC_StopOfConversion(ADC_TypeDef* ADCx); +void ADC_StartOfConversion(ADC_TypeDef* ADCx); +uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); + +/* Regular Channels DMA Configuration functions *******************************/ +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_DMARequestModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMARequestMode); + +/* Interrupts and flags management functions **********************************/ +void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState); +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG); +void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG); +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT); +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F0XX_ADC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_cec.h b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_cec.h new file mode 100644 index 0000000..6f928e4 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_cec.h @@ -0,0 +1,300 @@ +/** + ****************************************************************************** + * @file stm32f0xx_cec.h + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file contains all the functions prototypes for the CEC firmware + * library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_CEC_H +#define __STM32F0XX_CEC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CEC + * @{ + */ +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief CEC Init structure definition + */ +typedef struct +{ + uint32_t CEC_SignalFreeTime; /*!< Specifies the CEC Signal Free Time configuration. + This parameter can be a value of @ref CEC_Signal_Free_Time */ + uint32_t CEC_RxTolerance; /*!< Specifies the CEC Reception Tolerance. + This parameter can be a value of @ref CEC_RxTolerance */ + uint32_t CEC_StopReception; /*!< Specifies the CEC Stop Reception. + This parameter can be a value of @ref CEC_Stop_Reception */ + uint32_t CEC_BitRisingError; /*!< Specifies the CEC Bit Rising Error generation. + This parameter can be a value of @ref CEC_Bit_Rising_Error_Generation */ + uint32_t CEC_LongBitPeriodError; /*!< Specifies the CEC Long Bit Error generation. + This parameter can be a value of @ref CEC_Long_Bit_Error_Generation */ + uint32_t CEC_BRDNoGen; /*!< Specifies the CEC Broadcast Error generation. + This parameter can be a value of @ref CEC_BDR_No_Gen */ + uint32_t CEC_SFTOption; /*!< Specifies the CEC Signal Free Time option. + This parameter can be a value of @ref CEC_SFT_Option */ + +}CEC_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CEC_Exported_Constants + * @{ + */ + +/** @defgroup CEC_Signal_Free_Time + * @{ + */ +#define CEC_SignalFreeTime_Standard ((uint32_t)0x00000000) /*!< CEC Signal Free Time Standard */ +#define CEC_SignalFreeTime_1T ((uint32_t)0x00000001) /*!< CEC 1.5 nominal data bit periods */ +#define CEC_SignalFreeTime_2T ((uint32_t)0x00000002) /*!< CEC 2.5 nominal data bit periods */ +#define CEC_SignalFreeTime_3T ((uint32_t)0x00000003) /*!< CEC 3.5 nominal data bit periods */ +#define CEC_SignalFreeTime_4T ((uint32_t)0x00000004) /*!< CEC 4.5 nominal data bit periods */ +#define CEC_SignalFreeTime_5T ((uint32_t)0x00000005) /*!< CEC 5.5 nominal data bit periods */ +#define CEC_SignalFreeTime_6T ((uint32_t)0x00000006) /*!< CEC 6.5 nominal data bit periods */ +#define CEC_SignalFreeTime_7T ((uint32_t)0x00000007) /*!< CEC 7.5 nominal data bit periods */ + +#define IS_CEC_SIGNAL_FREE_TIME(TIME) (((TIME) == CEC_SignalFreeTime_Standard) || \ + ((TIME) == CEC_SignalFreeTime_1T)|| \ + ((TIME) == CEC_SignalFreeTime_2T)|| \ + ((TIME) == CEC_SignalFreeTime_3T)|| \ + ((TIME) == CEC_SignalFreeTime_4T)|| \ + ((TIME) == CEC_SignalFreeTime_5T)|| \ + ((TIME) == CEC_SignalFreeTime_6T)|| \ + ((TIME) == CEC_SignalFreeTime_7T)) +/** + * @} + */ + +/** @defgroup CEC_RxTolerance + * @{ + */ +#define CEC_RxTolerance_Standard ((uint32_t)0x00000000) /*!< Standard Tolerance Margin */ +#define CEC_RxTolerance_Extended CEC_CFGR_RXTOL /*!< Extended Tolerance Margin */ + +#define IS_CEC_RX_TOLERANCE(TOLERANCE) (((TOLERANCE) == CEC_RxTolerance_Standard) || \ + ((TOLERANCE) == CEC_RxTolerance_Extended)) +/** + * @} + */ + +/** @defgroup CEC_Stop_Reception + * @{ + */ +#define CEC_StopReception_Off ((uint32_t)0x00000000) /*!< No RX Stop on bit Rising Error (BRE) */ +#define CEC_StopReception_On CEC_CFGR_BRESTP /*!< RX Stop on bit Rising Error (BRE) */ + +#define IS_CEC_STOP_RECEPTION(RECEPTION) (((RECEPTION) == CEC_StopReception_On) || \ + ((RECEPTION) == CEC_StopReception_Off)) +/** + * @} + */ + +/** @defgroup CEC_Bit_Rising_Error_Generation + * @{ + */ +#define CEC_BitRisingError_Off ((uint32_t)0x00000000) /*!< Bit Rising Error generation turned Off */ +#define CEC_BitRisingError_On CEC_CFGR_BREGEN /*!< Bit Rising Error generation turned On */ + +#define IS_CEC_BIT_RISING_ERROR(ERROR) (((ERROR) == CEC_BitRisingError_Off) || \ + ((ERROR) == CEC_BitRisingError_On)) +/** + * @} + */ + +/** @defgroup CEC_Long_Bit_Error_Generation + * @{ + */ +#define CEC_LongBitPeriodError_Off ((uint32_t)0x00000000) /*!< Long Bit Period Error generation turned Off */ +#define CEC_LongBitPeriodError_On CEC_CFGR_LREGEN /*!< Long Bit Period Error generation turned On */ + +#define IS_CEC_LONG_BIT_PERIOD_ERROR(ERROR) (((ERROR) == CEC_LongBitPeriodError_Off) || \ + ((ERROR) == CEC_LongBitPeriodError_On)) +/** + * @} + */ + +/** @defgroup CEC_BDR_No_Gen + * @{ + */ + +#define CEC_BRDNoGen_Off ((uint32_t)0x00000000) /*!< Broadcast Bit Rising Error generation turned Off */ +#define CEC_BRDNoGen_On CEC_CFGR_BRDNOGEN /*!< Broadcast Bit Rising Error generation turned On */ + +#define IS_CEC_BDR_NO_GEN_ERROR(ERROR) (((ERROR) == CEC_BRDNoGen_Off) || \ + ((ERROR) == CEC_BRDNoGen_On)) +/** + * @} + */ + +/** @defgroup CEC_SFT_Option + * @{ + */ +#define CEC_SFTOption_Off ((uint32_t)0x00000000) /*!< SFT option turned Off */ +#define CEC_SFTOption_On CEC_CFGR_SFTOPT /*!< SFT option turned On */ + +#define IS_CEC_SFT_OPTION(OPTION) (((OPTION) == CEC_SFTOption_Off) || \ + ((OPTION) == CEC_SFTOption_On)) +/** + * @} + */ + +/** @defgroup CEC_Own_Address + * @{ + */ +#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10) + +/** + * @} + */ + +/** @defgroup CEC_Interrupt_Configuration_definition + * @{ + */ +#define CEC_IT_TXACKE CEC_IER_TXACKEIE +#define CEC_IT_TXERR CEC_IER_TXERRIE +#define CEC_IT_TXUDR CEC_IER_TXUDRIE +#define CEC_IT_TXEND CEC_IER_TXENDIE +#define CEC_IT_TXBR CEC_IER_TXBRIE +#define CEC_IT_ARBLST CEC_IER_ARBLSTIE +#define CEC_IT_RXACKE CEC_IER_RXACKEIE +#define CEC_IT_LBPE CEC_IER_LBPEIE +#define CEC_IT_SBPE CEC_IER_SBPEIE +#define CEC_IT_BRE CEC_IER_BREIEIE +#define CEC_IT_RXOVR CEC_IER_RXOVRIE +#define CEC_IT_RXEND CEC_IER_RXENDIE +#define CEC_IT_RXBR CEC_IER_RXBRIE + +#define IS_CEC_IT(IT) ((((IT) & (uint32_t)0xFFFFE000) == 0x00) && ((IT) != 0x00)) + +#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TXACKE) || \ + ((IT) == CEC_IT_TXERR)|| \ + ((IT) == CEC_IT_TXUDR)|| \ + ((IT) == CEC_IT_TXEND)|| \ + ((IT) == CEC_IT_TXBR)|| \ + ((IT) == CEC_IT_ARBLST)|| \ + ((IT) == CEC_IT_RXACKE)|| \ + ((IT) == CEC_IT_LBPE)|| \ + ((IT) == CEC_IT_SBPE)|| \ + ((IT) == CEC_IT_BRE)|| \ + ((IT) == CEC_IT_RXOVR)|| \ + ((IT) == CEC_IT_RXEND)|| \ + ((IT) == CEC_IT_RXBR)) +/** + * @} + */ + +/** @defgroup CEC_ISR_register_flags_definition + * @{ + */ +#define CEC_FLAG_TXACKE CEC_ISR_TXACKE +#define CEC_FLAG_TXERR CEC_ISR_TXERR +#define CEC_FLAG_TXUDR CEC_ISR_TXUDR +#define CEC_FLAG_TXEND CEC_ISR_TXEND +#define CEC_FLAG_TXBR CEC_ISR_TXBR +#define CEC_FLAG_ARBLST CEC_ISR_ARBLST +#define CEC_FLAG_RXACKE CEC_ISR_RXACKE +#define CEC_FLAG_LBPE CEC_ISR_LBPE +#define CEC_FLAG_SBPE CEC_ISR_SBPE +#define CEC_FLAG_BRE CEC_ISR_BRE +#define CEC_FLAG_RXOVR CEC_ISR_RXOVR +#define CEC_FLAG_RXEND CEC_ISR_RXEND +#define CEC_FLAG_RXBR CEC_ISR_RXBR + +#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFE000) == 0x00) && ((FLAG) != 0x00)) + +#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_TXACKE) || \ + ((FLAG) == CEC_FLAG_TXERR)|| \ + ((FLAG) == CEC_FLAG_TXUDR)|| \ + ((FLAG) == CEC_FLAG_TXEND)|| \ + ((FLAG) == CEC_FLAG_TXBR)|| \ + ((FLAG) == CEC_FLAG_ARBLST)|| \ + ((FLAG) == CEC_FLAG_RXACKE)|| \ + ((FLAG) == CEC_FLAG_LBPE)|| \ + ((FLAG) == CEC_FLAG_SBPE)|| \ + ((FLAG) == CEC_FLAG_BRE)|| \ + ((FLAG) == CEC_FLAG_RXOVR)|| \ + ((FLAG) == CEC_FLAG_RXEND)|| \ + ((FLAG) == CEC_FLAG_RXBR)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Function used to set the CEC configuration to the default reset state *****/ +void CEC_DeInit(void); + +/* CEC_Initialization and Configuration functions *****************************/ +void CEC_Init(CEC_InitTypeDef* CEC_InitStruct); +void CEC_StructInit(CEC_InitTypeDef* CEC_InitStruct); +void CEC_Cmd(FunctionalState NewState); +void CEC_ListenModeCmd(FunctionalState NewState); +void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress); +void CEC_OwnAddressClear(void); + +/* CEC_Data transfers functions ***********************************************/ +void CEC_SendData(uint8_t Data); +uint8_t CEC_ReceiveData(void); +void CEC_StartOfMessage(void); +void CEC_EndOfMessage(void); + +/* CEC_Interrupts and flags management functions ******************************/ +void CEC_ITConfig(uint16_t CEC_IT, FunctionalState NewState); +FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG); +void CEC_ClearFlag(uint32_t CEC_FLAG); +ITStatus CEC_GetITStatus(uint16_t CEC_IT); +void CEC_ClearITPendingBit(uint16_t CEC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0XX_CEC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_comp.h b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_comp.h new file mode 100644 index 0000000..87c8887 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_comp.h @@ -0,0 +1,243 @@ +/** + ****************************************************************************** + * @file stm32f0xx_comp.h + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file contains all the functions prototypes for the COMP firmware + * library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_COMP_H +#define __STM32F0XX_COMP_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup COMP + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief COMP Init structure definition + */ + +typedef struct +{ + + uint32_t COMP_InvertingInput; /*!< Selects the inverting input of the comparator. + This parameter can be a value of @ref COMP_InvertingInput */ + + uint32_t COMP_Output; /*!< Selects the output redirection of the comparator. + This parameter can be a value of @ref COMP_Output */ + + uint32_t COMP_OutputPol; /*!< Selects the output polarity of the comparator. + This parameter can be a value of @ref COMP_OutputPolarity */ + + uint32_t COMP_Hysteresis; /*!< Selects the hysteresis voltage of the comparator. + This parameter can be a value of @ref COMP_Hysteresis */ + + uint32_t COMP_Mode; /*!< Selects the operating mode of the comparator + and allows to adjust the speed/consumption. + This parameter can be a value of @ref COMP_Mode */ + +}COMP_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup COMP_Exported_Constants + * @{ + */ + +/** @defgroup COMP_Selection + * @{ + */ + +#define COMP_Selection_COMP1 ((uint32_t)0x00000000) /*!< COMP1 Selection */ +#define COMP_Selection_COMP2 ((uint32_t)0x00000010) /*!< COMP2 Selection */ + +#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \ + ((PERIPH) == COMP_Selection_COMP2)) + +/** + * @} + */ + +/** @defgroup COMP_InvertingInput + * @{ + */ + +#define COMP_InvertingInput_1_4VREFINT ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */ +#define COMP_InvertingInput_1_2VREFINT COMP_CSR_COMP1INSEL_0 /*!< 1/2 VREFINT connected to comparator inverting input */ +#define COMP_InvertingInput_3_4VREFINT COMP_CSR_COMP1INSEL_1 /*!< 3/4 VREFINT connected to comparator inverting input */ +#define COMP_InvertingInput_VREFINT ((uint32_t)0x00000030) /*!< VREFINT connected to comparator inverting input */ +#define COMP_InvertingInput_DAC1 COMP_CSR_COMP1INSEL_2 /*!< DAC1_OUT connected to comparator inverting input */ +#define COMP_InvertingInput_IO ((uint32_t)0x00000060) /*!< I/O (PA0 for COMP1 and PA2 for COMP2) connected to comparator inverting input */ + +#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_1_4VREFINT) || \ + ((INPUT) == COMP_InvertingInput_1_2VREFINT) || \ + ((INPUT) == COMP_InvertingInput_3_4VREFINT) || \ + ((INPUT) == COMP_InvertingInput_VREFINT) || \ + ((INPUT) == COMP_InvertingInput_DAC1) || \ + ((INPUT) == COMP_InvertingInput_1_4VREFINT) || \ + ((INPUT) == COMP_InvertingInput_IO)) +/** + * @} + */ + +/** @defgroup COMP_Output + * @{ + */ + +#define COMP_Output_None ((uint32_t)0x00000000) /*!< COMP output isn't connected to other peripherals */ +#define COMP_Output_TIM1BKIN COMP_CSR_COMP1OUTSEL_0 /*!< COMP output connected to TIM1 Break Input (BKIN) */ +#define COMP_Output_TIM1IC1 COMP_CSR_COMP1OUTSEL_1 /*!< COMP output connected to TIM1 Input Capture 1 */ +#define COMP_Output_TIM1OCREFCLR ((uint32_t)0x00000300) /*!< COMP output connected to TIM1 OCREF Clear */ +#define COMP_Output_TIM2IC4 COMP_CSR_COMP1OUTSEL_2 /*!< COMP output connected to TIM2 Input Capture 4 */ +#define COMP_Output_TIM2OCREFCLR ((uint32_t)0x00000500) /*!< COMP output connected to TIM2 OCREF Clear */ +#define COMP_Output_TIM3IC1 ((uint32_t)0x00000600) /*!< COMP output connected to TIM3 Input Capture 1 */ +#define COMP_Output_TIM3OCREFCLR COMP_CSR_COMP1OUTSEL /*!< COMP output connected to TIM3 OCREF Clear */ + + +#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_Output_None) || \ + ((OUTPUT) == COMP_Output_TIM1BKIN) || \ + ((OUTPUT) == COMP_Output_TIM1IC1) || \ + ((OUTPUT) == COMP_Output_TIM1OCREFCLR) || \ + ((OUTPUT) == COMP_Output_TIM2IC4) || \ + ((OUTPUT) == COMP_Output_TIM2OCREFCLR) || \ + ((OUTPUT) == COMP_Output_TIM3IC1) || \ + ((OUTPUT) == COMP_Output_TIM3OCREFCLR)) +/** + * @} + */ + +/** @defgroup COMP_OutputPolarity + * @{ + */ +#define COMP_OutputPol_NonInverted ((uint32_t)0x00000000) /*!< COMP output on GPIO isn't inverted */ +#define COMP_OutputPol_Inverted COMP_CSR_COMP1POL /*!< COMP output on GPIO is inverted */ + +#define IS_COMP_OUTPUT_POL(POL) (((POL) == COMP_OutputPol_NonInverted) || \ + ((POL) == COMP_OutputPol_Inverted)) + +/** + * @} + */ + +/** @defgroup COMP_Hysteresis + * @{ + */ +/* Please refer to the electrical characteristics in the device datasheet for + the hysteresis level */ +#define COMP_Hysteresis_No 0x00000000 /*!< No hysteresis */ +#define COMP_Hysteresis_Low COMP_CSR_COMP1HYST_0 /*!< Hysteresis level low */ +#define COMP_Hysteresis_Medium COMP_CSR_COMP1HYST_1 /*!< Hysteresis level medium */ +#define COMP_Hysteresis_High COMP_CSR_COMP1HYST /*!< Hysteresis level high */ + +#define IS_COMP_HYSTERESIS(HYSTERESIS) (((HYSTERESIS) == COMP_Hysteresis_No) || \ + ((HYSTERESIS) == COMP_Hysteresis_Low) || \ + ((HYSTERESIS) == COMP_Hysteresis_Medium) || \ + ((HYSTERESIS) == COMP_Hysteresis_High)) +/** + * @} + */ + +/** @defgroup COMP_Mode + * @{ + */ +/* Please refer to the electrical characteristics in the device datasheet for + the power consumption values */ +#define COMP_Mode_HighSpeed 0x00000000 /*!< High Speed */ +#define COMP_Mode_MediumSpeed COMP_CSR_COMP1MODE_0 /*!< Medium Speed */ +#define COMP_Mode_LowPower COMP_CSR_COMP1MODE_1 /*!< Low power mode */ +#define COMP_Mode_UltraLowPower COMP_CSR_COMP1MODE /*!< Ultra-low power mode */ + +#define IS_COMP_MODE(MODE) (((MODE) == COMP_Mode_UltraLowPower) || \ + ((MODE) == COMP_Mode_LowPower) || \ + ((MODE) == COMP_Mode_MediumSpeed) || \ + ((MODE) == COMP_Mode_HighSpeed)) +/** + * @} + */ + +/** @defgroup COMP_OutputLevel + * @{ + */ +/* When output polarity is not inverted, comparator output is high when + the non-inverting input is at a higher voltage than the inverting input */ +#define COMP_OutputLevel_High COMP_CSR_COMP1OUT +/* When output polarity is not inverted, comparator output is low when + the non-inverting input is at a lower voltage than the inverting input*/ +#define COMP_OutputLevel_Low ((uint32_t)0x00000000) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Function used to set the COMP configuration to the default reset state ****/ +void COMP_DeInit(void); + +/* Initialization and Configuration functions *********************************/ +void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct); +void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct); +void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState); +void COMP_SwitchCmd(FunctionalState NewState); +uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection); + +/* Window mode control function ***********************************************/ +void COMP_WindowCmd(FunctionalState NewState); + +/* COMP configuration locking function ****************************************/ +void COMP_LockConfig(uint32_t COMP_Selection); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F0XX_COMP_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_crc.h b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_crc.h new file mode 100644 index 0000000..1863d6c --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_crc.h @@ -0,0 +1,100 @@ +/** + ****************************************************************************** + * @file stm32f0xx_crc.h + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file contains all the functions prototypes for the CRC firmware + * library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_CRC_H +#define __STM32F0XX_CRC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/*!< Includes ----------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CRC_Exported_Constants + * @{ + */ +#define CRC_ReverseInputData_No ((uint32_t)0x00000000) /*!< No reverse operation of Input Data */ +#define CRC_ReverseInputData_8bits CRC_CR_REV_IN_0 /*!< Reverse operation of Input Data on 8 bits */ +#define CRC_ReverseInputData_16bits CRC_CR_REV_IN_1 /*!< Reverse operation of Input Data on 16 bits */ +#define CRC_ReverseInputData_32bits CRC_CR_REV_IN /*!< Reverse operation of Input Data on 32 bits */ + +#define IS_CRC_REVERSE_INPUT_DATA(DATA) (((DATA) == CRC_ReverseInputData_No) || \ + ((DATA) == CRC_ReverseInputData_8bits) || \ + ((DATA) == CRC_ReverseInputData_16bits) || \ + ((DATA) == CRC_ReverseInputData_32bits)) + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +/* Configuration of the CRC computation unit **********************************/ +void CRC_DeInit(void); +void CRC_ResetDR(void); +void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData); +void CRC_ReverseOutputDataCmd(FunctionalState NewState); +void CRC_SetInitRegister(uint32_t CRC_InitValue); + +/* CRC computation ************************************************************/ +uint32_t CRC_CalcCRC(uint32_t CRC_Data); +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); +uint32_t CRC_GetCRC(void); + +/* Independent register (IDR) access (write/read) *****************************/ +void CRC_SetIDRegister(uint8_t CRC_IDValue); +uint8_t CRC_GetIDRegister(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0XX_CRC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_dac.h b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_dac.h new file mode 100644 index 0000000..4ea4977 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_dac.h @@ -0,0 +1,207 @@ +/** + ****************************************************************************** + * @file stm32f0xx_dac.h + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file contains all the functions prototypes for the DAC firmware + * library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_DAC_H +#define __STM32F0XX_DAC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DAC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief DAC Init structure definition + */ + +typedef struct +{ + uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. + This parameter can be a value of @ref DAC_Trigger */ + + uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. + This parameter can be a value of @ref DAC_OutputBuffer */ +}DAC_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DAC_Exported_Constants + * @{ + */ + +/** @defgroup DAC_Trigger + * @{ + */ + +#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register + has been loaded, and not by external trigger */ +#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ + +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ + ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T3_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T15_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ + ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ + ((TRIGGER) == DAC_Trigger_Software)) + +/** + * @} + */ + +/** @defgroup DAC_OutputBuffer + * @{ + */ + +#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) +#define DAC_OutputBuffer_Disable DAC_CR_BOFF1 +#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ + ((STATE) == DAC_OutputBuffer_Disable)) +/** + * @} + */ + +/** @defgroup DAC_Channel_selection + * @{ + */ + +#define DAC_Channel_1 ((uint32_t)0x00000000) +#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1)) + +/** + * @} + */ + +/** @defgroup DAC_data_alignment + * @{ + */ + +#define DAC_Align_12b_R ((uint32_t)0x00000000) +#define DAC_Align_12b_L ((uint32_t)0x00000004) +#define DAC_Align_8b_R ((uint32_t)0x00000008) +#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ + ((ALIGN) == DAC_Align_12b_L) || \ + ((ALIGN) == DAC_Align_8b_R)) +/** + * @} + */ + +/** @defgroup DAC_data + * @{ + */ + +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) + +/** + * @} + */ + +/** @defgroup DAC_interrupts_definition + * @{ + */ + +#define DAC_IT_DMAUDR DAC_SR_DMAUDR1 +#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) + +/** + * @} + */ + + +/** @defgroup DAC_flags_definition + * @{ + */ + +#define DAC_FLAG_DMAUDR DAC_SR_DMAUDR1 + +#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Function used to set the DAC configuration to the default reset state *****/ +void DAC_DeInit(void); + +/* DAC channels configuration: trigger, output buffer, data format functions */ +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); + +/* DMA management functions ***************************************************/ +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); +FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG); +void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG); +ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT); +void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F0XX_DAC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_dbgmcu.h b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_dbgmcu.h new file mode 100644 index 0000000..588562d --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_dbgmcu.h @@ -0,0 +1,105 @@ +/** + ****************************************************************************** + * @file stm32f0xx_dbgmcu.h + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file contains all the functions prototypes for the DBGMCU firmware + * library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_DBGMCU_H +#define __STM32F0XX_DBGMCU_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DBGMCU + * @{ + */ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + + +/** @defgroup DBGMCU_Exported_Constants + * @{ + */ + +#define DBGMCU_STOP DBGMCU_CR_DBG_STOP +#define DBGMCU_STANDBY DBGMCU_CR_DBG_STANDBY +#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF9) == 0x00) && ((PERIPH) != 0x00)) + +#define DBGMCU_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP +#define DBGMCU_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP +#define DBGMCU_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP +#define DBGMCU_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP +#define DBGMCU_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP +#define DBGMCU_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP +#define DBGMCU_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP +#define DBGMCU_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT +#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFFDFE2EC) == 0x00) && ((PERIPH) != 0x00)) + +#define DBGMCU_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP +#define DBGMCU_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP +#define DBGMCU_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP +#define DBGMCU_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP +#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8F7FF) == 0x00) && ((PERIPH) != 0x00)) + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Device and Revision ID management functions ********************************/ +uint32_t DBGMCU_GetREVID(void); +uint32_t DBGMCU_GetDEVID(void); + +/* Peripherals Configuration functions ****************************************/ +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); +void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); +void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0XX_DBGMCU_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_dma.h b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_dma.h new file mode 100644 index 0000000..ba65cdf --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_dma.h @@ -0,0 +1,351 @@ +/** + ****************************************************************************** + * @file stm32f0xx_dma.h + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file contains all the functions prototypes for the DMA firmware + * library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_DMA_H +#define __STM32F0XX_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief DMA Init structures definition + */ +typedef struct +{ + uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */ + + uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */ + + uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination. + This parameter can be a value of @ref DMA_data_transfer_direction */ + + uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. + The data unit is equal to the configuration set in DMA_PeripheralDataSize + or DMA_MemoryDataSize members depending in the transfer direction */ + + uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not. + This parameter can be a value of @ref DMA_peripheral_incremented_mode */ + + uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not. + This parameter can be a value of @ref DMA_memory_incremented_mode */ + + uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_peripheral_data_size */ + + uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_memory_data_size */ + + uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_circular_normal_mode + @note: The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_priority_level */ + + uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer. + This parameter can be a value of @ref DMA_memory_to_memory */ +}DMA_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Constants + * @{ + */ + +#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \ + ((PERIPH) == DMA1_Channel2) || \ + ((PERIPH) == DMA1_Channel3) || \ + ((PERIPH) == DMA1_Channel4) || \ + ((PERIPH) == DMA1_Channel5)) + +/** @defgroup DMA_data_transfer_direction + * @{ + */ + +#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) +#define DMA_DIR_PeripheralDST DMA_CCR_DIR + +#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralSRC) || \ + ((DIR) == DMA_DIR_PeripheralDST)) +/** + * @} + */ + +/** @defgroup DMA_peripheral_incremented_mode + * @{ + */ + +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) +#define DMA_PeripheralInc_Enable DMA_CCR_PINC + +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Disable) || \ + ((STATE) == DMA_PeripheralInc_Enable)) +/** + * @} + */ + +/** @defgroup DMA_memory_incremented_mode + * @{ + */ + +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) +#define DMA_MemoryInc_Enable DMA_CCR_MINC + +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Disable) || \ + ((STATE) == DMA_MemoryInc_Enable)) +/** + * @} + */ + +/** @defgroup DMA_peripheral_data_size + * @{ + */ + +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord DMA_CCR_PSIZE_0 +#define DMA_PeripheralDataSize_Word DMA_CCR_PSIZE_1 + +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ + ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ + ((SIZE) == DMA_PeripheralDataSize_Word)) +/** + * @} + */ + +/** @defgroup DMA_memory_data_size + * @{ + */ + +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord DMA_CCR_MSIZE_0 +#define DMA_MemoryDataSize_Word DMA_CCR_MSIZE_1 + +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ + ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ + ((SIZE) == DMA_MemoryDataSize_Word)) +/** + * @} + */ + +/** @defgroup DMA_circular_normal_mode + * @{ + */ + +#define DMA_Mode_Normal ((uint32_t)0x00000000) +#define DMA_Mode_Circular DMA_CCR_CIRC + +#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal) || ((MODE) == DMA_Mode_Circular)) +/** + * @} + */ + +/** @defgroup DMA_priority_level + * @{ + */ + +#define DMA_Priority_VeryHigh DMA_CCR_PL +#define DMA_Priority_High DMA_CCR_PL_1 +#define DMA_Priority_Medium DMA_CCR_PL_0 +#define DMA_Priority_Low ((uint32_t)0x00000000) + +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ + ((PRIORITY) == DMA_Priority_High) || \ + ((PRIORITY) == DMA_Priority_Medium) || \ + ((PRIORITY) == DMA_Priority_Low)) +/** + * @} + */ + +/** @defgroup DMA_memory_to_memory + * @{ + */ + +#define DMA_M2M_Disable ((uint32_t)0x00000000) +#define DMA_M2M_Enable DMA_CCR_MEM2MEM + +#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Disable) || ((STATE) == DMA_M2M_Enable)) + +/** + * @} + */ + +/** @defgroup DMA_interrupts_definition + * @{ + */ + +#define DMA_IT_TC DMA_CCR_TCIE +#define DMA_IT_HT DMA_CCR_HTIE +#define DMA_IT_TE DMA_CCR_TEIE + +#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) + +#define DMA1_IT_GL1 DMA_ISR_GIF1 +#define DMA1_IT_TC1 DMA_ISR_TCIF1 +#define DMA1_IT_HT1 DMA_ISR_HTIF1 +#define DMA1_IT_TE1 DMA_ISR_TEIF1 +#define DMA1_IT_GL2 DMA_ISR_GIF2 +#define DMA1_IT_TC2 DMA_ISR_TCIF2 +#define DMA1_IT_HT2 DMA_ISR_HTIF2 +#define DMA1_IT_TE2 DMA_ISR_TEIF2 +#define DMA1_IT_GL3 DMA_ISR_GIF3 +#define DMA1_IT_TC3 DMA_ISR_TCIF3 +#define DMA1_IT_HT3 DMA_ISR_HTIF3 +#define DMA1_IT_TE3 DMA_ISR_TEIF3 +#define DMA1_IT_GL4 DMA_ISR_GIF4 +#define DMA1_IT_TC4 DMA_ISR_TCIF4 +#define DMA1_IT_HT4 DMA_ISR_HTIF4 +#define DMA1_IT_TE4 DMA_ISR_TEIF4 +#define DMA1_IT_GL5 DMA_ISR_GIF5 +#define DMA1_IT_TC5 DMA_ISR_TCIF5 +#define DMA1_IT_HT5 DMA_ISR_HTIF5 +#define DMA1_IT_TE5 DMA_ISR_TEIF5 + +#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0xFFF00000) == 0x00) && ((IT) != 0x00)) + +#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \ + ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \ + ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \ + ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \ + ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \ + ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \ + ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \ + ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \ + ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \ + ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5)) + +/** + * @} + */ + +/** @defgroup DMA_flags_definition + * @{ + */ +#define DMA1_FLAG_GL1 DMA_ISR_GIF1 +#define DMA1_FLAG_TC1 DMA_ISR_TCIF1 +#define DMA1_FLAG_HT1 DMA_ISR_HTIF1 +#define DMA1_FLAG_TE1 DMA_ISR_TEIF1 +#define DMA1_FLAG_GL2 DMA_ISR_GIF2 +#define DMA1_FLAG_TC2 DMA_ISR_TCIF2 +#define DMA1_FLAG_HT2 DMA_ISR_HTIF2 +#define DMA1_FLAG_TE2 DMA_ISR_TEIF2 +#define DMA1_FLAG_GL3 DMA_ISR_GIF3 +#define DMA1_FLAG_TC3 DMA_ISR_TCIF3 +#define DMA1_FLAG_HT3 DMA_ISR_HTIF3 +#define DMA1_FLAG_TE3 DMA_ISR_TEIF3 +#define DMA1_FLAG_GL4 DMA_ISR_GIF4 +#define DMA1_FLAG_TC4 DMA_ISR_TCIF4 +#define DMA1_FLAG_HT4 DMA_ISR_HTIF4 +#define DMA1_FLAG_TE4 DMA_ISR_TEIF4 +#define DMA1_FLAG_GL5 DMA_ISR_GIF5 +#define DMA1_FLAG_TC5 DMA_ISR_TCIF5 +#define DMA1_FLAG_HT5 DMA_ISR_HTIF5 +#define DMA1_FLAG_TE5 DMA_ISR_TEIF5 + +#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0xFFF00000) == 0x00) && ((FLAG) != 0x00)) + +#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \ + ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \ + ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \ + ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \ + ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \ + ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \ + ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \ + ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \ + ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \ + ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5)) + +/** + * @} + */ + +/** @defgroup DMA_Buffer_Size + * @{ + */ + +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Function used to set the DMA configuration to the default reset state ******/ +void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); + +/* Initialization and Configuration functions *********************************/ +void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); +void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); + +/* Data Counter functions******************************************************/ +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); + +/* Interrupts and flags management functions **********************************/ +void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); +FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG); +void DMA_ClearFlag(uint32_t DMA_FLAG); +ITStatus DMA_GetITStatus(uint32_t DMA_IT); +void DMA_ClearITPendingBit(uint32_t DMA_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F0XX_DMA_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_exti.h b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_exti.h new file mode 100644 index 0000000..aa7dbf7 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_exti.h @@ -0,0 +1,194 @@ +/** + ****************************************************************************** + * @file stm32f0xx_exti.h + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file contains all the functions prototypes for the EXTI + * firmware library + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_EXTI_H +#define __STM32F0XX_EXTI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief EXTI mode enumeration + */ + +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +}EXTIMode_TypeDef; + +#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) + +/** + * @brief EXTI Trigger enumeration + */ + +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +}EXTITrigger_TypeDef; + +#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ + ((TRIGGER) == EXTI_Trigger_Falling) || \ + ((TRIGGER) == EXTI_Trigger_Rising_Falling)) +/** + * @brief EXTI Init Structure definition + */ + +typedef struct +{ + uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. + This parameter can be any combination of @ref EXTI_Lines */ + + EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ +}EXTI_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup EXTI_Exported_Constants + * @{ + */ +/** @defgroup EXTI_Lines + * @{ + */ + +#define EXTI_Line0 ((uint32_t)0x00000001) /*!< External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00000002) /*!< External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00000004) /*!< External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00000008) /*!< External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00000010) /*!< External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00000020) /*!< External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00000040) /*!< External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00000080) /*!< External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00000100) /*!< External interrupt line 8 */ +#define EXTI_Line9 ((uint32_t)0x00000200) /*!< External interrupt line 9 */ +#define EXTI_Line10 ((uint32_t)0x00000400) /*!< External interrupt line 10 */ +#define EXTI_Line11 ((uint32_t)0x00000800) /*!< External interrupt line 11 */ +#define EXTI_Line12 ((uint32_t)0x00001000) /*!< External interrupt line 12 */ +#define EXTI_Line13 ((uint32_t)0x00002000) /*!< External interrupt line 13 */ +#define EXTI_Line14 ((uint32_t)0x00004000) /*!< External interrupt line 14 */ +#define EXTI_Line15 ((uint32_t)0x00008000) /*!< External interrupt line 15 */ +#define EXTI_Line16 ((uint32_t)0x00010000) /*!< External interrupt line 16 + Connected to the PVD Output */ +#define EXTI_Line17 ((uint32_t)0x00020000) /*!< Internal interrupt line 17 + Connected to the RTC Alarm + event */ +#define EXTI_Line19 ((uint32_t)0x00080000) /*!< Internal interrupt line 19 + Connected to the RTC Tamper + and Time Stamp events */ +#define EXTI_Line21 ((uint32_t)0x00200000) /*!< Internal interrupt line 21 + Connected to the Comparator 1 + event */ +#define EXTI_Line22 ((uint32_t)0x00400000) /*!< Internal interrupt line 22 + Connected to the Comparator 2 + event */ +#define EXTI_Line23 ((uint32_t)0x00800000) /*!< Internal interrupt line 23 + Connected to the I2C1 wakeup + event */ +#define EXTI_Line25 ((uint32_t)0x02000000) /*!< Internal interrupt line 25 + Connected to the USART1 wakeup + event */ +#define EXTI_Line27 ((uint32_t)0x08000000) /*!< Internal interrupt line 27 + Connected to the CEC wakeup + event */ + +#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xF5140000) == 0x00) && ((LINE) != (uint16_t)0x00)) + +#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ + ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ + ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ + ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ + ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ + ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ + ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ + ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ + ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ + ((LINE) == EXTI_Line19) || ((LINE) == EXTI_Line21) || \ + ((LINE) == EXTI_Line22)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +/* Function used to set the EXTI configuration to the default reset state *****/ +void EXTI_DeInit(void); + +/* Initialization and Configuration functions *********************************/ +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); + +/* Interrupts and flags management functions **********************************/ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); +void EXTI_ClearFlag(uint32_t EXTI_Line); +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); +void EXTI_ClearITPendingBit(uint32_t EXTI_Line); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0XX_EXTI_H */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_flash.h b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_flash.h new file mode 100644 index 0000000..cdf6e5d --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_flash.h @@ -0,0 +1,320 @@ +/** + ****************************************************************************** + * @file stm32f0xx_flash.h + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file contains all the functions prototypes for the FLASH + * firmware library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_FLASH_H +#define __STM32F0XX_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief FLASH Status + */ +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_WRP, + FLASH_ERROR_PROGRAM, + FLASH_COMPLETE, + FLASH_TIMEOUT +}FLASH_Status; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup FLASH_Exported_Constants + * @{ + */ + +/** @defgroup FLASH_Latency + * @{ + */ +#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */ +#define FLASH_Latency_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */ + +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ + ((LATENCY) == FLASH_Latency_1)) +/** + * @} + */ + +/** @defgroup FLASH_Interrupts + * @{ + */ + +#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of programming interrupt source */ +#define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error interrupt source */ +#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) +/** + * @} + */ + +/** @defgroup FLASH_Address + * @{ + */ + +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0800FFFF)) + +/** + * @} + */ + +/** @defgroup FLASH_OB_DATA_ADDRESS + * @{ + */ +#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806)) + +/** + * @} + */ + +/** @defgroup FLASH_Option_Bytes_Write_Protection + * @{ + */ + + +#define OB_WRP_Pages0to3 ((uint32_t)0x00000001) /* Write protection of page 0 to 3 */ +#define OB_WRP_Pages4to7 ((uint32_t)0x00000002) /* Write protection of page 4 to 7 */ +#define OB_WRP_Pages8to11 ((uint32_t)0x00000004) /* Write protection of page 8 to 11 */ +#define OB_WRP_Pages12to15 ((uint32_t)0x00000008) /* Write protection of page 12 to 15 */ +#define OB_WRP_Pages16to19 ((uint32_t)0x00000010) /* Write protection of page 16 to 19 */ +#define OB_WRP_Pages20to23 ((uint32_t)0x00000020) /* Write protection of page 20 to 23 */ +#define OB_WRP_Pages24to27 ((uint32_t)0x00000040) /* Write protection of page 24 to 27 */ +#define OB_WRP_Pages28to31 ((uint32_t)0x00000080) /* Write protection of page 28 to 31 */ +#define OB_WRP_Pages32to35 ((uint32_t)0x00000100) /* Write protection of page 32 to 35 */ +#define OB_WRP_Pages36to39 ((uint32_t)0x00000200) /* Write protection of page 36 to 39 */ +#define OB_WRP_Pages40to43 ((uint32_t)0x00000400) /* Write protection of page 40 to 43 */ +#define OB_WRP_Pages44to47 ((uint32_t)0x00000800) /* Write protection of page 44 to 47 */ +#define OB_WRP_Pages48to51 ((uint32_t)0x00001000) /* Write protection of page 48 to 51 */ +#define OB_WRP_Pages52to55 ((uint32_t)0x00002000) /* Write protection of page 52 to 55 */ +#define OB_WRP_Pages56to59 ((uint32_t)0x00004000) /* Write protection of page 56 to 59 */ +#define OB_WRP_Pages60to63 ((uint32_t)0x00008000) /* Write protection of page 60 to 63 */ + +#define OB_WRP_AllPages ((uint32_t)0x0000FFFF) /*!< Write protection of all Sectors */ + +#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000)) + +/** + * @} + */ + +/** @defgroup FLASH_Option_Bytes_Read_Protection + * @{ + */ + +/** + * @brief FLASH_Read Protection Level + */ +#define OB_RDP_Level_0 ((uint8_t)0xAA) +#define OB_RDP_Level_1 ((uint8_t)0xBB) +/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2 + it's no more possible to go back to level 1 or 0 */ + +#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\ + ((LEVEL) == OB_RDP_Level_1))/*||\ + ((LEVEL) == OB_RDP_Level_2))*/ +/** + * @} + */ + +/** @defgroup FLASH_Option_Bytes_IWatchdog + * @{ + */ + +#define OB_IWDG_SW ((uint8_t)0x01) /*!< Software IWDG selected */ +#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */ +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) + +/** + * @} + */ + +/** @defgroup FLASH_Option_Bytes_nRST_STOP + * @{ + */ + +#define OB_STOP_NoRST ((uint8_t)0x02) /*!< No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */ +#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) + +/** + * @} + */ + +/** @defgroup FLASH_Option_Bytes_nRST_STDBY + * @{ + */ + +#define OB_STDBY_NoRST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */ +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) + +/** + * @} + */ + +/** @defgroup FLASH_Option_Bytes_BOOT1 + * @{ + */ + +#define OB_BOOT1_RESET ((uint8_t)0x00) /*!< BOOT1 Reset */ +#define OB_BOOT1_SET ((uint8_t)0x10) /*!< BOOT1 Set */ +#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET)) + +/** + * @} + */ + +/** @defgroup FLASH_Option_Bytes_VDDA_Analog_Monitoring + * @{ + */ + +#define OB_VDDA_ANALOG_ON ((uint8_t)0x00) /*!< Analog monitoring on VDDA Power source ON */ +#define OB_VDDA_ANALOG_OFF ((uint8_t)0x20) /*!< Analog monitoring on VDDA Power source OFF */ + +#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF)) + +/** + * @} + */ + +/** @defgroup FLASH_Option_Bytes_SRAM_Parity_Enable + * @{ + */ + +#define OB_SRAM_PARITY_SET ((uint8_t)0x00) /*!< SRAM parity enable Set */ +#define OB_SRAM_PARITY_RESET ((uint8_t)0x40) /*!< SRAM parity enable reset */ + +#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET)) + +/** + * @} + */ + +/** @defgroup FLASH_Flags + * @{ + */ + +#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ +#define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */ +#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */ + +#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFC3) == 0x00000000) && ((FLAG) != 0x00000000)) + +#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_PGERR) || \ + ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP)) +/** + * @} + */ + +/** @defgroup FLASH_Timeout_definition + * @{ + */ +#define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x000B0000) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/** + * @brief FLASH memory functions that can be executed from FLASH. + */ +/* FLASH Interface configuration functions ************************************/ +void FLASH_SetLatency(uint32_t FLASH_Latency); +void FLASH_PrefetchBufferCmd(FunctionalState NewState); +FlagStatus FLASH_GetPrefetchBufferStatus(void); + +/* FLASH Memory Programming functions *****************************************/ +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_Status FLASH_ErasePage(uint32_t Page_Address); +FLASH_Status FLASH_EraseAllPages(void); +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); + +/* FLASH Option Bytes Programming functions *****************************************/ +void FLASH_OB_Unlock(void); +void FLASH_OB_Lock(void); +void FLASH_OB_Launch(void); +FLASH_Status FLASH_OB_Erase(void); +FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP); +FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP); +FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); +FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1); +FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG); +FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity); +FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER); +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); +uint8_t FLASH_OB_GetUser(void); +uint32_t FLASH_OB_GetWRP(void); +FlagStatus FLASH_OB_GetRDP(void); + +/* FLASH Interrupts and flags management functions **********************************/ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); +void FLASH_ClearFlag(uint32_t FLASH_FLAG); +FLASH_Status FLASH_GetStatus(void); +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0XX_FLASH_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_gpio.h b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_gpio.h new file mode 100644 index 0000000..8ee96db --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_gpio.h @@ -0,0 +1,350 @@ +/** + ****************************************************************************** + * @file stm32f0xx_gpio.h + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file contains all the functions prototypes for the GPIO + * firmware library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_GPIO_H +#define __STM32F0XX_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ +/* Exported types ------------------------------------------------------------*/ + +#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ + ((PERIPH) == GPIOB) || \ + ((PERIPH) == GPIOC) || \ + ((PERIPH) == GPIOD) || \ + ((PERIPH) == GPIOF)) + +#define IS_GPIO_LIST_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ + ((PERIPH) == GPIOB)) + +/** @defgroup Configuration_Mode_enumeration + * @{ + */ +typedef enum +{ + GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */ + GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */ + GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */ + GPIO_Mode_AN = 0x03 /*!< GPIO Analog In/Out Mode */ +}GPIOMode_TypeDef; + +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)|| ((MODE) == GPIO_Mode_OUT) || \ + ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN)) +/** + * @} + */ + +/** @defgroup Output_type_enumeration + * @{ + */ +typedef enum +{ + GPIO_OType_PP = 0x00, + GPIO_OType_OD = 0x01 +}GPIOOType_TypeDef; + +#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD)) + +/** + * @} + */ + +/** @defgroup Output_Maximum_frequency_enumeration + * @{ + */ +typedef enum +{ + GPIO_Speed_Level_1 = 0x01, /*!< Medium Speed */ + GPIO_Speed_Level_2 = 0x02, /*!< Fast Speed */ + GPIO_Speed_Level_3 = 0x03 /*!< High Speed */ +}GPIOSpeed_TypeDef; + +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_Level_1) || ((SPEED) == GPIO_Speed_Level_2) || \ + ((SPEED) == GPIO_Speed_Level_3)) +/** + * @} + */ + +/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration + * @{ + */ +typedef enum +{ + GPIO_PuPd_NOPULL = 0x00, + GPIO_PuPd_UP = 0x01, + GPIO_PuPd_DOWN = 0x02 +}GPIOPuPd_TypeDef; + +#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \ + ((PUPD) == GPIO_PuPd_DOWN)) +/** + * @} + */ + +/** @defgroup Bit_SET_and_Bit_RESET_enumeration + * @{ + */ +typedef enum +{ + Bit_RESET = 0, + Bit_SET +}BitAction; + +#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) +/** + * @} + */ + +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIOMode_TypeDef */ + + GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIOSpeed_TypeDef */ + + GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins. + This parameter can be a value of @ref GPIOOType_TypeDef */ + + GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + This parameter can be a value of @ref GPIOPuPd_TypeDef */ +}GPIO_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Constants + * @{ + */ + +/** @defgroup GPIO_pins_define + * @{ + */ +#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */ + +#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00) + +#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ + ((PIN) == GPIO_Pin_1) || \ + ((PIN) == GPIO_Pin_2) || \ + ((PIN) == GPIO_Pin_3) || \ + ((PIN) == GPIO_Pin_4) || \ + ((PIN) == GPIO_Pin_5) || \ + ((PIN) == GPIO_Pin_6) || \ + ((PIN) == GPIO_Pin_7) || \ + ((PIN) == GPIO_Pin_8) || \ + ((PIN) == GPIO_Pin_9) || \ + ((PIN) == GPIO_Pin_10) || \ + ((PIN) == GPIO_Pin_11) || \ + ((PIN) == GPIO_Pin_12) || \ + ((PIN) == GPIO_Pin_13) || \ + ((PIN) == GPIO_Pin_14) || \ + ((PIN) == GPIO_Pin_15)) + +/** + * @} + */ + +/** @defgroup GPIO_Pin_sources + * @{ + */ +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource8 ((uint8_t)0x08) +#define GPIO_PinSource9 ((uint8_t)0x09) +#define GPIO_PinSource10 ((uint8_t)0x0A) +#define GPIO_PinSource11 ((uint8_t)0x0B) +#define GPIO_PinSource12 ((uint8_t)0x0C) +#define GPIO_PinSource13 ((uint8_t)0x0D) +#define GPIO_PinSource14 ((uint8_t)0x0E) +#define GPIO_PinSource15 ((uint8_t)0x0F) + +#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ + ((PINSOURCE) == GPIO_PinSource1) || \ + ((PINSOURCE) == GPIO_PinSource2) || \ + ((PINSOURCE) == GPIO_PinSource3) || \ + ((PINSOURCE) == GPIO_PinSource4) || \ + ((PINSOURCE) == GPIO_PinSource5) || \ + ((PINSOURCE) == GPIO_PinSource6) || \ + ((PINSOURCE) == GPIO_PinSource7) || \ + ((PINSOURCE) == GPIO_PinSource8) || \ + ((PINSOURCE) == GPIO_PinSource9) || \ + ((PINSOURCE) == GPIO_PinSource10) || \ + ((PINSOURCE) == GPIO_PinSource11) || \ + ((PINSOURCE) == GPIO_PinSource12) || \ + ((PINSOURCE) == GPIO_PinSource13) || \ + ((PINSOURCE) == GPIO_PinSource14) || \ + ((PINSOURCE) == GPIO_PinSource15)) +/** + * @} + */ + +/** @defgroup GPIO_Alternate_function_selection_define + * @{ + */ + +/** + * @brief AF 0 selection + */ +#define GPIO_AF_0 ((uint8_t)0x00) /* WKUP, EVENTOUT, TIM15, SPI1, TIM17, + MCO, SWDAT, SWCLK, TIM14, BOOT, + USART1, CEC, IR_OUT, SPI2 */ +/** + * @brief AF 1 selection + */ +#define GPIO_AF_1 ((uint8_t)0x01) /* USART2, CEC, Tim3, USART1, USART2, + EVENTOUT, I2C1, I2C2, TIM15 */ +/** + * @brief AF 2 selection + */ +#define GPIO_AF_2 ((uint8_t)0x02) /* TIM2, TIM1, EVENTOUT, TIM16, TIM17 */ +/** + * @brief AF 3 selection + */ +#define GPIO_AF_3 ((uint8_t)0x03) /* TS, I2C1, TIM15, EVENTOUT */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF_4 ((uint8_t)0x04) /* TIM14 */ +/** + * @brief AF 5 selection + */ +#define GPIO_AF_5 ((uint8_t)0x05) /* TIM16, TIM17 */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF_6 ((uint8_t)0x06) /* EVENTOUT */ +/** + * @brief AF 7 selection + */ +#define GPIO_AF_7 ((uint8_t)0x07) /* COMP1 OUT and COMP2 OUT */ + +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_0) || ((AF) == GPIO_AF_1) || \ + ((AF) == GPIO_AF_2) || ((AF) == GPIO_AF_3) || \ + ((AF) == GPIO_AF_4) || ((AF) == GPIO_AF_5) || \ + ((AF) == GPIO_AF_6) || ((AF) == GPIO_AF_7)) + +/** + * @} + */ + +/** @defgroup GPIO_Speed_Legacy + * @{ + */ + +#define GPIO_Speed_10MHz GPIO_Speed_Level_1 /*!< Fast Speed:10MHz */ +#define GPIO_Speed_2MHz GPIO_Speed_Level_2 /*!< Medium Speed:2MHz */ +#define GPIO_Speed_50MHz GPIO_Speed_Level_3 /*!< High Speed:50MHz */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +/* Function used to set the GPIO configuration to the default reset state *****/ +void GPIO_DeInit(GPIO_TypeDef* GPIOx); + +/* Initialization and Configuration functions *********************************/ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); + +/* GPIO Read and Write functions **********************************************/ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); + +/* GPIO Alternate functions configuration functions ***************************/ +void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0XX_GPIO_H */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_i2c.h b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_i2c.h new file mode 100644 index 0000000..f12c05b --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_i2c.h @@ -0,0 +1,478 @@ +/** + ****************************************************************************** + * @file stm32f0xx_i2c.h + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file contains all the functions prototypes for the I2C firmware + * library + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_I2C_H +#define __STM32F0XX_I2C_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief I2C Init structure definition + */ + +typedef struct +{ + uint32_t I2C_Timing; /*!< Specifies the I2C_TIMINGR_register value. + This parameter must be set by referring to I2C_Timing_Config_Tool*/ + + uint32_t I2C_AnalogFilter; /*!< Enables or disables analog noise filter. + This parameter can be a value of @ref I2C_Analog_Filter*/ + + uint32_t I2C_DigitalFilter; /*!< Configures the digital noise filter. + This parameter can be a number between 0x00 and 0x0F*/ + + uint32_t I2C_Mode; /*!< Specifies the I2C mode. + This parameter can be a value of @ref I2C_mode*/ + + uint32_t I2C_OwnAddress1; /*!< Specifies the device own address 1. + This parameter can be a 7-bit or 10-bit address*/ + + uint32_t I2C_Ack; /*!< Enables or disables the acknowledgement. + This parameter can be a value of @ref I2C_acknowledgement*/ + + uint32_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. + This parameter can be a value of @ref I2C_acknowledged_address*/ +}I2C_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + + +/** @defgroup I2C_Exported_Constants + * @{ + */ + +#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ + ((PERIPH) == I2C2)) + +#define IS_I2C_1_PERIPH(PERIPH) ((PERIPH) == I2C1) + +/** @defgroup I2C_Analog_Filter + * @{ + */ + +#define I2C_AnalogFilter_Enable ((uint32_t)0x00000000) +#define I2C_AnalogFilter_Disable I2C_CR1_ANFOFF + +#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_AnalogFilter_Enable) || \ + ((FILTER) == I2C_AnalogFilter_Disable)) +/** + * @} + */ + +/** @defgroup I2C_Digital_Filter + * @{ + */ + +#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F) +/** + * @} + */ + +/** @defgroup I2C_mode + * @{ + */ + +#define I2C_Mode_I2C ((uint32_t)0x00000000) +#define I2C_Mode_SMBusDevice I2C_CR1_SMBDEN +#define I2C_Mode_SMBusHost I2C_CR1_SMBHEN + +#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ + ((MODE) == I2C_Mode_SMBusDevice) || \ + ((MODE) == I2C_Mode_SMBusHost)) +/** + * @} + */ + +/** @defgroup I2C_acknowledgement + * @{ + */ + +#define I2C_Ack_Enable ((uint32_t)0x00000000) +#define I2C_Ack_Disable I2C_CR2_NACK + +#define IS_I2C_ACK(ACK) (((ACK) == I2C_Ack_Enable) || \ + ((ACK) == I2C_Ack_Disable)) +/** + * @} + */ + +/** @defgroup I2C_acknowledged_address + * @{ + */ + +#define I2C_AcknowledgedAddress_7bit ((uint32_t)0x00000000) +#define I2C_AcknowledgedAddress_10bit I2C_OAR1_OA1MODE + +#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ + ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) +/** + * @} + */ + +/** @defgroup I2C_own_address1 + * @{ + */ + +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF) +/** + * @} + */ + +/** @defgroup I2C_transfer_direction + * @{ + */ + +#define I2C_Direction_Transmitter ((uint16_t)0x0000) +#define I2C_Direction_Receiver ((uint16_t)0x0400) + +#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ + ((DIRECTION) == I2C_Direction_Receiver)) +/** + * @} + */ + +/** @defgroup I2C_DMA_transfer_requests + * @{ + */ + +#define I2C_DMAReq_Tx I2C_CR1_TXDMAEN +#define I2C_DMAReq_Rx I2C_CR1_RXDMAEN + +#define IS_I2C_DMA_REQ(REQ) ((((REQ) & (uint32_t)0xFFFF3FFF) == 0x00) && ((REQ) != 0x00)) +/** + * @} + */ + +/** @defgroup I2C_slave_address + * @{ + */ + +#define IS_I2C_SLAVE_ADDRESS(ADDRESS) ((ADDRESS) <= (uint16_t)0x03FF) +/** + * @} + */ + + +/** @defgroup I2C_own_address2 + * @{ + */ + +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF) + +/** + * @} + */ + +/** @defgroup I2C_own_address2_mask + * @{ + */ + +#define I2C_OA2_NoMask ((uint8_t)0x00) +#define I2C_OA2_Mask01 ((uint8_t)0x01) +#define I2C_OA2_Mask02 ((uint8_t)0x02) +#define I2C_OA2_Mask03 ((uint8_t)0x03) +#define I2C_OA2_Mask04 ((uint8_t)0x04) +#define I2C_OA2_Mask05 ((uint8_t)0x05) +#define I2C_OA2_Mask06 ((uint8_t)0x06) +#define I2C_OA2_Mask07 ((uint8_t)0x07) + +#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NoMask) || \ + ((MASK) == I2C_OA2_Mask01) || \ + ((MASK) == I2C_OA2_Mask02) || \ + ((MASK) == I2C_OA2_Mask03) || \ + ((MASK) == I2C_OA2_Mask04) || \ + ((MASK) == I2C_OA2_Mask05) || \ + ((MASK) == I2C_OA2_Mask06) || \ + ((MASK) == I2C_OA2_Mask07)) + +/** + * @} + */ + +/** @defgroup I2C_timeout + * @{ + */ + +#define IS_I2C_TIMEOUT(TIMEOUT) ((TIMEOUT) <= (uint16_t)0x0FFF) + +/** + * @} + */ + +/** @defgroup I2C_registers + * @{ + */ + +#define I2C_Register_CR1 ((uint8_t)0x00) +#define I2C_Register_CR2 ((uint8_t)0x04) +#define I2C_Register_OAR1 ((uint8_t)0x08) +#define I2C_Register_OAR2 ((uint8_t)0x0C) +#define I2C_Register_TIMINGR ((uint8_t)0x10) +#define I2C_Register_TIMEOUTR ((uint8_t)0x14) +#define I2C_Register_ISR ((uint8_t)0x18) +#define I2C_Register_ICR ((uint8_t)0x1C) +#define I2C_Register_PECR ((uint8_t)0x20) +#define I2C_Register_RXDR ((uint8_t)0x24) +#define I2C_Register_TXDR ((uint8_t)0x28) + +#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ + ((REGISTER) == I2C_Register_CR2) || \ + ((REGISTER) == I2C_Register_OAR1) || \ + ((REGISTER) == I2C_Register_OAR2) || \ + ((REGISTER) == I2C_Register_TIMINGR) || \ + ((REGISTER) == I2C_Register_TIMEOUTR) || \ + ((REGISTER) == I2C_Register_ISR) || \ + ((REGISTER) == I2C_Register_ICR) || \ + ((REGISTER) == I2C_Register_PECR) || \ + ((REGISTER) == I2C_Register_RXDR) || \ + ((REGISTER) == I2C_Register_TXDR)) +/** + * @} + */ + +/** @defgroup I2C_interrupts_definition + * @{ + */ + +#define I2C_IT_ERRI I2C_CR1_ERRIE +#define I2C_IT_TCI I2C_CR1_TCIE +#define I2C_IT_STOPI I2C_CR1_STOPIE +#define I2C_IT_NACKI I2C_CR1_NACKIE +#define I2C_IT_ADDRI I2C_CR1_ADDRIE +#define I2C_IT_RXI I2C_CR1_RXIE +#define I2C_IT_TXI I2C_CR1_TXIE + +#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint32_t)0xFFFFFF01) == 0x00) && ((IT) != 0x00)) + +/** + * @} + */ + +/** @defgroup I2C_flags_definition + * @{ + */ + +#define I2C_FLAG_TXE I2C_ISR_TXE +#define I2C_FLAG_TXIS I2C_ISR_TXIS +#define I2C_FLAG_RXNE I2C_ISR_RXNE +#define I2C_FLAG_ADDR I2C_ISR_ADDR +#define I2C_FLAG_NACKF I2C_ISR_NACKF +#define I2C_FLAG_STOPF I2C_ISR_STOPF +#define I2C_FLAG_TC I2C_ISR_TC +#define I2C_FLAG_TCR I2C_ISR_TCR +#define I2C_FLAG_BERR I2C_ISR_BERR +#define I2C_FLAG_ARLO I2C_ISR_ARLO +#define I2C_FLAG_OVR I2C_ISR_OVR +#define I2C_FLAG_PECERR I2C_ISR_PECERR +#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT +#define I2C_FLAG_ALERT I2C_ISR_ALERT +#define I2C_FLAG_BUSY I2C_ISR_BUSY + +#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFF4000) == 0x00) && ((FLAG) != 0x00)) + +#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_TXIS) || \ + ((FLAG) == I2C_FLAG_RXNE) || ((FLAG) == I2C_FLAG_ADDR) || \ + ((FLAG) == I2C_FLAG_NACKF) || ((FLAG) == I2C_FLAG_STOPF) || \ + ((FLAG) == I2C_FLAG_TC) || ((FLAG) == I2C_FLAG_TCR) || \ + ((FLAG) == I2C_FLAG_BERR) || ((FLAG) == I2C_FLAG_ARLO) || \ + ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_PECERR) || \ + ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_ALERT) || \ + ((FLAG) == I2C_FLAG_BUSY)) + +/** + * @} + */ + + +/** @defgroup I2C_interrupts_definition + * @{ + */ + +#define I2C_IT_TXIS I2C_ISR_TXIS +#define I2C_IT_RXNE I2C_ISR_RXNE +#define I2C_IT_ADDR I2C_ISR_ADDR +#define I2C_IT_NACKF I2C_ISR_NACKF +#define I2C_IT_STOPF I2C_ISR_STOPF +#define I2C_IT_TC I2C_ISR_TC +#define I2C_IT_TCR I2C_ISR_TCR +#define I2C_IT_BERR I2C_ISR_BERR +#define I2C_IT_ARLO I2C_ISR_ARLO +#define I2C_IT_OVR I2C_ISR_OVR +#define I2C_IT_PECERR I2C_ISR_PECERR +#define I2C_IT_TIMEOUT I2C_ISR_TIMEOUT +#define I2C_IT_ALERT I2C_ISR_ALERT + +#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFFFFC001) == 0x00) && ((IT) != 0x00)) + +#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_TXIS) || ((IT) == I2C_IT_RXNE) || \ + ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_NACKF) || \ + ((IT) == I2C_IT_STOPF) || ((IT) == I2C_IT_TC) || \ + ((IT) == I2C_IT_TCR) || ((IT) == I2C_IT_BERR) || \ + ((IT) == I2C_IT_ARLO) || ((IT) == I2C_IT_OVR) || \ + ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_TIMEOUT) || \ + ((IT) == I2C_IT_ALERT)) + + +/** + * @} + */ + +/** @defgroup I2C_ReloadEndMode_definition + * @{ + */ + +#define I2C_Reload_Mode I2C_CR2_RELOAD +#define I2C_AutoEnd_Mode I2C_CR2_AUTOEND +#define I2C_SoftEnd_Mode ((uint32_t)0x00000000) + + +#define IS_RELOAD_END_MODE(MODE) (((MODE) == I2C_Reload_Mode) || \ + ((MODE) == I2C_AutoEnd_Mode) || \ + ((MODE) == I2C_SoftEnd_Mode)) + + +/** + * @} + */ + +/** @defgroup I2C_StartStopMode_definition + * @{ + */ + +#define I2C_No_StartStop ((uint32_t)0x00000000) +#define I2C_Generate_Stop I2C_CR2_STOP +#define I2C_Generate_Start_Read (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) +#define I2C_Generate_Start_Write I2C_CR2_START + + +#define IS_START_STOP_MODE(MODE) (((MODE) == I2C_Generate_Stop) || \ + ((MODE) == I2C_Generate_Start_Read) || \ + ((MODE) == I2C_Generate_Start_Write) || \ + ((MODE) == I2C_No_StartStop)) + + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + + +/* Initialization and Configuration functions *********************************/ +void I2C_DeInit(I2C_TypeDef* I2Cx); +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState); +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_StopModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask); +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address); +void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); + +/* Communications handling functions ******************************************/ +void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes); +void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction); +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); +uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx); +uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx); +void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode); + +/* SMBUS management functions ************************************************/ +void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout); +void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout); +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); + +/* I2C registers management functions *****************************************/ +uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); + +/* Data transfers management functions ****************************************/ +void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); +uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); + +/* DMA transfers management functions *****************************************/ +void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); +void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); + + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F0XX_I2C_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_iwdg.h b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_iwdg.h new file mode 100644 index 0000000..564293b --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_iwdg.h @@ -0,0 +1,140 @@ +/** + ****************************************************************************** + * @file stm32f0xx_iwdg.h + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file contains all the functions prototypes for the IWDG + * firmware library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_IWDG_H +#define __STM32F0XX_IWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup IWDG + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup IWDG_Exported_Constants + * @{ + */ + +/** @defgroup IWDG_WriteAccess + * @{ + */ + +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) +#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ + ((ACCESS) == IWDG_WriteAccess_Disable)) +/** + * @} + */ + +/** @defgroup IWDG_prescaler + * @{ + */ + +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) +#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ + ((PRESCALER) == IWDG_Prescaler_8) || \ + ((PRESCALER) == IWDG_Prescaler_16) || \ + ((PRESCALER) == IWDG_Prescaler_32) || \ + ((PRESCALER) == IWDG_Prescaler_64) || \ + ((PRESCALER) == IWDG_Prescaler_128)|| \ + ((PRESCALER) == IWDG_Prescaler_256)) +/** + * @} + */ + +/** @defgroup IWDG_Flag + * @{ + */ + +#define IWDG_FLAG_PVU IWDG_SR_PVU +#define IWDG_FLAG_RVU IWDG_SR_RVU +#define IWDG_FLAG_WVU IWDG_SR_WVU +#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU) || \ + ((FLAG) == IWDG_FLAG_WVU)) + +#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) + +#define IS_IWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0xFFF) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Prescaler and Counter configuration functions ******************************/ +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); +void IWDG_SetReload(uint16_t Reload); +void IWDG_ReloadCounter(void); +void IWDG_SetWindowValue(uint16_t WindowValue); + +/* IWDG activation function ***************************************************/ +void IWDG_Enable(void); + +/* Flag management function ***************************************************/ +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0XX_IWDG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_misc.h b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_misc.h new file mode 100644 index 0000000..3eb7930 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_misc.h @@ -0,0 +1,143 @@ +/** + ****************************************************************************** + * @file stm32f0xx_misc.h + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file contains all the functions prototypes for the miscellaneous + * firmware library functions (add-on to CMSIS functions). + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_MISC_H +#define __STM32F0XX_MISC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup MISC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief NVIC Init Structure definition + */ + +typedef struct +{ + uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. + This parameter can be a value of @ref IRQn_Type + (For the complete STM32 Devices IRQ Channels list, + please refer to stm32f0xx.h file) */ + + uint8_t NVIC_IRQChannelPriority; /*!< Specifies the priority level for the IRQ channel specified + in NVIC_IRQChannel. This parameter can be a value + between 0 and 3. */ + + FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel + will be enabled or disabled. + This parameter can be set either to ENABLE or DISABLE */ +} NVIC_InitTypeDef; + +/** + * +@verbatim + +@endverbatim +*/ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup MISC_Exported_Constants + * @{ + */ + +/** @defgroup MISC_System_Low_Power + * @{ + */ + +#define NVIC_LP_SEVONPEND ((uint8_t)0x10) +#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) +#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) +#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ + ((LP) == NVIC_LP_SLEEPDEEP) || \ + ((LP) == NVIC_LP_SLEEPONEXIT)) +/** + * @} + */ + +/** @defgroup MISC_Preemption_Priority_Group + * @{ + */ +#define IS_NVIC_PRIORITY(PRIORITY) ((PRIORITY) < 0x04) + +/** + * @} + */ + +/** @defgroup MISC_SysTick_clock_source + * @{ + */ + +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ + ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0XX_MISC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_pwr.h b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_pwr.h new file mode 100644 index 0000000..857b7c9 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_pwr.h @@ -0,0 +1,186 @@ +/** + ****************************************************************************** + * @file stm32f0xx_pwr.h + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file contains all the functions prototypes for the PWR firmware + * library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_PWR_H +#define __STM32F0XX_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Constants + * @{ + */ + +/** @defgroup PWR_PVD_detection_level + * @{ + */ + +#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0 +#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1 +#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2 +#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3 +#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4 +#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5 +#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6 +#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7 + +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \ + ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \ + ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \ + ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7)) +/** + * @} + */ + +/** @defgroup PWR_WakeUp_Pins + * @{ + */ + +#define PWR_WakeUpPin_1 PWR_CSR_EWUP1 +#define PWR_WakeUpPin_2 PWR_CSR_EWUP2 +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || \ + ((PIN) == PWR_WakeUpPin_2)) +/** + * @} + */ + + +/** @defgroup PWR_Regulator_state_is_Sleep_STOP_mode + * @{ + */ + +#define PWR_Regulator_ON ((uint32_t)0x00000000) +#define PWR_Regulator_LowPower PWR_CR_LPSDSR +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ + ((REGULATOR) == PWR_Regulator_LowPower)) +/** + * @} + */ + +/** @defgroup PWR_SLEEP_mode_entry + * @{ + */ + +#define PWR_SLEEPEntry_WFI ((uint8_t)0x01) +#define PWR_SLEEPEntry_WFE ((uint8_t)0x02) +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE)) + +/** + * @} + */ + +/** @defgroup PWR_STOP_mode_entry + * @{ + */ + +#define PWR_STOPEntry_WFI ((uint8_t)0x01) +#define PWR_STOPEntry_WFE ((uint8_t)0x02) +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) + +/** + * @} + */ + +/** @defgroup PWR_Flag + * @{ + */ + +#define PWR_FLAG_WU PWR_CSR_WUF +#define PWR_FLAG_SB PWR_CSR_SBF +#define PWR_FLAG_PVDO PWR_CSR_PVDO +#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF + +#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ + ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY)) + +#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Function used to set the PWR configuration to the default reset state ******/ +void PWR_DeInit(void); + +/* Backup Domain Access function **********************************************/ +void PWR_BackupAccessCmd(FunctionalState NewState); + +/* PVD configuration functions ************************************************/ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); +void PWR_PVDCmd(FunctionalState NewState); + +/* WakeUp pins configuration functions ****************************************/ +void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState); + +/* Low Power modes configuration functions ************************************/ +void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry); +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); +void PWR_EnterSTANDBYMode(void); + +/* Flags management functions *************************************************/ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); +void PWR_ClearFlag(uint32_t PWR_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0XX_PWR_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_rcc.h b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_rcc.h new file mode 100644 index 0000000..31c16b1 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_rcc.h @@ -0,0 +1,523 @@ +/** + ****************************************************************************** + * @file stm32f0xx_rcc.h + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file contains all the functions prototypes for the RCC + * firmware library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_RCC_H +#define __STM32F0XX_RCC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +typedef struct +{ + uint32_t SYSCLK_Frequency; + uint32_t HCLK_Frequency; + uint32_t PCLK_Frequency; + uint32_t ADCCLK_Frequency; + uint32_t CECCLK_Frequency; + uint32_t I2C1CLK_Frequency; + uint32_t USART1CLK_Frequency; +}RCC_ClocksTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Constants + * @{ + */ + +/** @defgroup RCC_HSE_configuration + * @{ + */ + +#define RCC_HSE_OFF ((uint8_t)0x00) +#define RCC_HSE_ON ((uint8_t)0x01) +#define RCC_HSE_Bypass ((uint8_t)0x05) +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ + ((HSE) == RCC_HSE_Bypass)) + +/** + * @} + */ + +/** @defgroup RCC_PLL_Clock_Source + * @{ + */ + +#define RCC_PLLSource_HSI_Div2 RCC_CFGR_PLLSRC_HSI_Div2 +#define RCC_PLLSource_PREDIV1 RCC_CFGR_PLLSRC_PREDIV1 + +#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ + ((SOURCE) == RCC_PLLSource_PREDIV1)) +/** + * @} + */ + +/** @defgroup RCC_PLL_Multiplication_Factor + * @{ + */ + +#define RCC_PLLMul_2 RCC_CFGR_PLLMULL2 +#define RCC_PLLMul_3 RCC_CFGR_PLLMULL3 +#define RCC_PLLMul_4 RCC_CFGR_PLLMULL4 +#define RCC_PLLMul_5 RCC_CFGR_PLLMULL5 +#define RCC_PLLMul_6 RCC_CFGR_PLLMULL6 +#define RCC_PLLMul_7 RCC_CFGR_PLLMULL7 +#define RCC_PLLMul_8 RCC_CFGR_PLLMULL8 +#define RCC_PLLMul_9 RCC_CFGR_PLLMULL9 +#define RCC_PLLMul_10 RCC_CFGR_PLLMULL10 +#define RCC_PLLMul_11 RCC_CFGR_PLLMULL11 +#define RCC_PLLMul_12 RCC_CFGR_PLLMULL12 +#define RCC_PLLMul_13 RCC_CFGR_PLLMULL13 +#define RCC_PLLMul_14 RCC_CFGR_PLLMULL14 +#define RCC_PLLMul_15 RCC_CFGR_PLLMULL15 +#define RCC_PLLMul_16 RCC_CFGR_PLLMULL16 +#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ + ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ + ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ + ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ + ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ + ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ + ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ + ((MUL) == RCC_PLLMul_16)) +/** + * @} + */ + +/** @defgroup RCC_PREDIV1_division_factor + * @{ + */ +#define RCC_PREDIV1_Div1 RCC_CFGR2_PREDIV1_DIV1 +#define RCC_PREDIV1_Div2 RCC_CFGR2_PREDIV1_DIV2 +#define RCC_PREDIV1_Div3 RCC_CFGR2_PREDIV1_DIV3 +#define RCC_PREDIV1_Div4 RCC_CFGR2_PREDIV1_DIV4 +#define RCC_PREDIV1_Div5 RCC_CFGR2_PREDIV1_DIV5 +#define RCC_PREDIV1_Div6 RCC_CFGR2_PREDIV1_DIV6 +#define RCC_PREDIV1_Div7 RCC_CFGR2_PREDIV1_DIV7 +#define RCC_PREDIV1_Div8 RCC_CFGR2_PREDIV1_DIV8 +#define RCC_PREDIV1_Div9 RCC_CFGR2_PREDIV1_DIV9 +#define RCC_PREDIV1_Div10 RCC_CFGR2_PREDIV1_DIV10 +#define RCC_PREDIV1_Div11 RCC_CFGR2_PREDIV1_DIV11 +#define RCC_PREDIV1_Div12 RCC_CFGR2_PREDIV1_DIV12 +#define RCC_PREDIV1_Div13 RCC_CFGR2_PREDIV1_DIV13 +#define RCC_PREDIV1_Div14 RCC_CFGR2_PREDIV1_DIV14 +#define RCC_PREDIV1_Div15 RCC_CFGR2_PREDIV1_DIV15 +#define RCC_PREDIV1_Div16 RCC_CFGR2_PREDIV1_DIV16 + +#define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \ + ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \ + ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \ + ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \ + ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \ + ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \ + ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \ + ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16)) +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source + * @{ + */ + +#define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI +#define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE +#define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL +#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ + ((SOURCE) == RCC_SYSCLKSource_HSE) || \ + ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Source + * @{ + */ + +#define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1 +#define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2 +#define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4 +#define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8 +#define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16 +#define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64 +#define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128 +#define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256 +#define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512 +#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ + ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ + ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ + ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ + ((HCLK) == RCC_SYSCLK_Div512)) +/** + * @} + */ + +/** @defgroup RCC_APB_Clock_Source + * @{ + */ + +#define RCC_HCLK_Div1 RCC_CFGR_PPRE_DIV1 +#define RCC_HCLK_Div2 RCC_CFGR_PPRE_DIV2 +#define RCC_HCLK_Div4 RCC_CFGR_PPRE_DIV4 +#define RCC_HCLK_Div8 RCC_CFGR_PPRE_DIV8 +#define RCC_HCLK_Div16 RCC_CFGR_PPRE_DIV16 +#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ + ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ + ((PCLK) == RCC_HCLK_Div16)) +/** + * @} + */ + +/** @defgroup RCC_ADC_clock_source + * @{ + */ + +#define RCC_ADCCLK_HSI14 ((uint32_t)0x00000000) +#define RCC_ADCCLK_PCLK_Div2 ((uint32_t)0x01000000) +#define RCC_ADCCLK_PCLK_Div4 ((uint32_t)0x01004000) + +#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADCCLK_HSI14) || ((ADCCLK) == RCC_ADCCLK_PCLK_Div2) || \ + ((ADCCLK) == RCC_ADCCLK_PCLK_Div4)) + +/** + * @} + */ + +/** @defgroup RCC_CEC_clock_source + * @{ + */ + +#define RCC_CECCLK_HSI_Div244 ((uint32_t)0x00000000) +#define RCC_CECCLK_LSE RCC_CFGR3_CECSW + +#define IS_RCC_CECCLK(CECCLK) (((CECCLK) == RCC_CECCLK_HSI_Div244) || ((CECCLK) == RCC_CECCLK_LSE)) + +/** + * @} + */ + +/** @defgroup RCC_I2C_clock_source + * @{ + */ + +#define RCC_I2C1CLK_HSI ((uint32_t)0x00000000) +#define RCC_I2C1CLK_SYSCLK RCC_CFGR3_I2C1SW + +#define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK)) + +/** + * @} + */ + +/** @defgroup RCC_USART_clock_source + * @{ + */ + +#define RCC_USART1CLK_PCLK ((uint32_t)0x00000000) +#define RCC_USART1CLK_SYSCLK RCC_CFGR3_USART1SW_0 +#define RCC_USART1CLK_LSE RCC_CFGR3_USART1SW_1 +#define RCC_USART1CLK_HSI RCC_CFGR3_USART1SW + +#define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK) || ((USARTCLK) == RCC_USART1CLK_SYSCLK) || \ + ((USARTCLK) == RCC_USART1CLK_LSE) || ((USARTCLK) == RCC_USART1CLK_HSI)) + +/** + * @} + */ + +/** @defgroup RCC_Interrupt_Source + * @{ + */ + +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_LSERDY ((uint8_t)0x02) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_HSI14RDY ((uint8_t)0x20) +#define RCC_IT_CSS ((uint8_t)0x80) + +#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00)) + +#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ + ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ + ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_HSI14RDY) || \ + ((IT) == RCC_IT_CSS)) + +#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00)) + +/** + * @} + */ + +/** @defgroup RCC_LSE_Configuration + * @{ + */ + +#define RCC_LSE_OFF ((uint32_t)0x00000000) +#define RCC_LSE_ON RCC_BDCR_LSEON +#define RCC_LSE_Bypass ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP)) +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ + ((LSE) == RCC_LSE_Bypass)) +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Source + * @{ + */ + +#define RCC_RTCCLKSource_LSE RCC_BDCR_RTCSEL_LSE +#define RCC_RTCCLKSource_LSI RCC_BDCR_RTCSEL_LSI +#define RCC_RTCCLKSource_HSE_Div32 RCC_BDCR_RTCSEL_HSE + +#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ + ((SOURCE) == RCC_RTCCLKSource_LSI) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div32)) +/** + * @} + */ + +/** @defgroup RCC_LSE_Drive_Configuration + * @{ + */ + +#define RCC_LSEDrive_Low ((uint32_t)0x00000000) +#define RCC_LSEDrive_MediumLow RCC_BDCR_LSEDRV_0 +#define RCC_LSEDrive_MediumHigh RCC_BDCR_LSEDRV_1 +#define RCC_LSEDrive_High RCC_BDCR_LSEDRV +#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \ + ((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High)) +/** + * @} + */ + +/** @defgroup RCC_AHB_Peripherals + * @{ + */ + +#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN +#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN +#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN +#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN +#define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN +#define RCC_AHBPeriph_TS RCC_AHBENR_TSEN +#define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN +#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN +#define RCC_AHBPeriph_SRAM RCC_AHBENR_SRAMEN +#define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN + +#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFEA1FFAA) == 0x00) && ((PERIPH) != 0x00)) +#define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xFEA1FFFF) == 0x00) && ((PERIPH) != 0x00)) + +/** + * @} + */ + +/** @defgroup RCC_APB2_Peripherals + * @{ + */ + +#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN +#define RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1EN +#define RCC_APB2Periph_TIM1 RCC_APB2ENR_TIM1EN +#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN +#define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN +#define RCC_APB2Periph_TIM15 RCC_APB2ENR_TIM15EN +#define RCC_APB2Periph_TIM16 RCC_APB2ENR_TIM16EN +#define RCC_APB2Periph_TIM17 RCC_APB2ENR_TIM17EN +#define RCC_APB2Periph_DBGMCU RCC_APB2ENR_DBGMCUEN + +#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFB8A5FE) == 0x00) && ((PERIPH) != 0x00)) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Peripherals + * @{ + */ + +#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN +#define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN +#define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN +#define RCC_APB1Periph_TIM14 RCC_APB1ENR_TIM14EN +#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN +#define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN +#define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN +#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN +#define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN +#define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN +#define RCC_APB1Periph_DAC RCC_APB1ENR_DACEN +#define RCC_APB1Periph_CEC RCC_APB1ENR_CECEN + +#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x8F9DB6EC) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup RCC_MCO_Clock_Source + * @{ + */ + +#define RCC_MCOSource_NoClock ((uint8_t)0x00) +#define RCC_MCOSource_HSI14 ((uint8_t)0x01) +#define RCC_MCOSource_LSI ((uint8_t)0x02) +#define RCC_MCOSource_LSE ((uint8_t)0x03) +#define RCC_MCOSource_SYSCLK ((uint8_t)0x04) +#define RCC_MCOSource_HSI ((uint8_t)0x05) +#define RCC_MCOSource_HSE ((uint8_t)0x06) +#define RCC_MCOSource_PLLCLK_Div2 ((uint8_t)0x07) + +#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_HSI14) || \ + ((SOURCE) == RCC_MCOSource_SYSCLK) || ((SOURCE) == RCC_MCOSource_HSI) || \ + ((SOURCE) == RCC_MCOSource_HSE) || ((SOURCE) == RCC_MCOSource_PLLCLK_Div2)|| \ + ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE)) +/** + * @} + */ + +/** @defgroup RCC_Flag + * @{ + */ +#define RCC_FLAG_HSIRDY ((uint8_t)0x01) +#define RCC_FLAG_HSERDY ((uint8_t)0x11) +#define RCC_FLAG_PLLRDY ((uint8_t)0x19) +#define RCC_FLAG_LSERDY ((uint8_t)0x21) +#define RCC_FLAG_LSIRDY ((uint8_t)0x41) +#define RCC_FLAG_V18PWRRSTF ((uint8_t)0x57) +#define RCC_FLAG_OBLRST ((uint8_t)0x59) +#define RCC_FLAG_PINRST ((uint8_t)0x5A) +#define RCC_FLAG_PORRST ((uint8_t)0x5B) +#define RCC_FLAG_SFTRST ((uint8_t)0x5C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x5D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x5E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x5F) +#define RCC_FLAG_HSI14RDY ((uint8_t)0x61) + +#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_OBLRST) || \ + ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ + ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \ + ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \ + ((FLAG) == RCC_FLAG_HSI14RDY)|| ((FLAG) == RCC_FLAG_V18PWRRSTF)) + +#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) +#define IS_RCC_HSI14_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Function used to set the RCC clock configuration to the default reset state */ +void RCC_DeInit(void); + +/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ +void RCC_HSEConfig(uint8_t RCC_HSE); +ErrorStatus RCC_WaitForHSEStartUp(void); +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_AdjustHSI14CalibrationValue(uint8_t HSI14CalibrationValue); +void RCC_HSI14Cmd(FunctionalState NewState); +void RCC_HSI14ADCRequestCmd(FunctionalState NewState); +void RCC_LSEConfig(uint32_t RCC_LSE); +void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive); +void RCC_LSICmd(FunctionalState NewState); +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); +void RCC_PLLCmd(FunctionalState NewState); +void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div); +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +void RCC_MCOConfig(uint8_t RCC_MCOSource); + +/* System, AHB and APB busses clocks configuration functions ******************/ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); +uint8_t RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(uint32_t RCC_SYSCLK); +void RCC_PCLKConfig(uint32_t RCC_HCLK); +void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK); +void RCC_CECCLKConfig(uint32_t RCC_CECCLK); +void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK); +void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK); +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); + +/* Peripheral clocks configuration functions **********************************/ +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); +void RCC_RTCCLKCmd(FunctionalState NewState); +void RCC_BackupResetCmd(FunctionalState NewState); + +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); + +void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(uint8_t RCC_IT); +void RCC_ClearITPendingBit(uint8_t RCC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0XX_RCC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_rtc.h b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_rtc.h new file mode 100644 index 0000000..6baafe6 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_rtc.h @@ -0,0 +1,772 @@ +/** + ****************************************************************************** + * @file stm32f0xx_rtc.h + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file contains all the functions prototypes for the RTC firmware + * library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_RTC_H +#define __STM32F0XX_RTC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RTC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief RTC Init structures definition + */ +typedef struct +{ + uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format. + This parameter can be a value of @ref RTC_Hour_Formats */ + + uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. + This parameter must be set to a value lower than 0x7F */ + + uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. + This parameter must be set to a value lower than 0x1FFF */ +}RTC_InitTypeDef; + +/** + * @brief RTC Time structure definition + */ +typedef struct +{ + uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour. + This parameter must be set to a value in the 0-12 range + if the RTC_HourFormat_12 is selected or 0-23 range if + the RTC_HourFormat_24 is selected. */ + + uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes. + This parameter must be set to a value in the 0-59 range. */ + + uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds. + This parameter must be set to a value in the 0-59 range. */ + + uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time. + This parameter can be a value of @ref RTC_AM_PM_Definitions */ +}RTC_TimeTypeDef; + +/** + * @brief RTC Date structure definition + */ +typedef struct +{ + uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay. + This parameter can be a value of @ref RTC_WeekDay_Definitions */ + + uint8_t RTC_Month; /*!< Specifies the RTC Date Month. + This parameter can be a value of @ref RTC_Month_Date_Definitions */ + + uint8_t RTC_Date; /*!< Specifies the RTC Date. + This parameter must be set to a value in the 1-31 range. */ + + uint8_t RTC_Year; /*!< Specifies the RTC Date Year. + This parameter must be set to a value in the 0-99 range. */ +}RTC_DateTypeDef; + +/** + * @brief RTC Alarm structure definition + */ +typedef struct +{ + RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */ + + uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks. + This parameter can be a value of @ref RTC_AlarmMask_Definitions */ + + uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. + This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ + + uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. + This parameter must be set to a value in the 1-31 range + if the Alarm Date is selected. + This parameter can be a value of @ref RTC_WeekDay_Definitions + if the Alarm WeekDay is selected. */ +}RTC_AlarmTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup RTC_Exported_Constants + * @{ + */ + + +/** @defgroup RTC_Hour_Formats + * @{ + */ +#define RTC_HourFormat_24 ((uint32_t)0x00000000) +#define RTC_HourFormat_12 ((uint32_t)0x00000040) +#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \ + ((FORMAT) == RTC_HourFormat_24)) +/** + * @} + */ + +/** @defgroup RTC_Asynchronous_Predivider + * @{ + */ +#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F) + +/** + * @} + */ + + +/** @defgroup RTC_Synchronous_Predivider + * @{ + */ +#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF) + +/** + * @} + */ + +/** @defgroup RTC_Time_Definitions + * @{ + */ +#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12)) +#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23) +#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59) +#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59) + +/** + * @} + */ + +/** @defgroup RTC_AM_PM_Definitions + * @{ + */ +#define RTC_H12_AM ((uint8_t)0x00) +#define RTC_H12_PM ((uint8_t)0x40) +#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM)) + +/** + * @} + */ + +/** @defgroup RTC_Year_Date_Definitions + * @{ + */ +#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99) + +/** + * @} + */ + +/** @defgroup RTC_Month_Date_Definitions + * @{ + */ +#define RTC_Month_January ((uint8_t)0x01) +#define RTC_Month_February ((uint8_t)0x02) +#define RTC_Month_March ((uint8_t)0x03) +#define RTC_Month_April ((uint8_t)0x04) +#define RTC_Month_May ((uint8_t)0x05) +#define RTC_Month_June ((uint8_t)0x06) +#define RTC_Month_July ((uint8_t)0x07) +#define RTC_Month_August ((uint8_t)0x08) +#define RTC_Month_September ((uint8_t)0x09) +#define RTC_Month_October ((uint8_t)0x10) +#define RTC_Month_November ((uint8_t)0x11) +#define RTC_Month_December ((uint8_t)0x12) +#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12)) +#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31)) + +/** + * @} + */ + +/** @defgroup RTC_WeekDay_Definitions + * @{ + */ + +#define RTC_Weekday_Monday ((uint8_t)0x01) +#define RTC_Weekday_Tuesday ((uint8_t)0x02) +#define RTC_Weekday_Wednesday ((uint8_t)0x03) +#define RTC_Weekday_Thursday ((uint8_t)0x04) +#define RTC_Weekday_Friday ((uint8_t)0x05) +#define RTC_Weekday_Saturday ((uint8_t)0x6) +#define RTC_Weekday_Sunday ((uint8_t)0x07) +#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ + ((WEEKDAY) == RTC_Weekday_Tuesday) || \ + ((WEEKDAY) == RTC_Weekday_Wednesday) || \ + ((WEEKDAY) == RTC_Weekday_Thursday) || \ + ((WEEKDAY) == RTC_Weekday_Friday) || \ + ((WEEKDAY) == RTC_Weekday_Saturday) || \ + ((WEEKDAY) == RTC_Weekday_Sunday)) +/** + * @} + */ + + +/** @defgroup RTC_Alarm_Definitions + * @{ + */ +#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31)) +#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ + ((WEEKDAY) == RTC_Weekday_Tuesday) || \ + ((WEEKDAY) == RTC_Weekday_Wednesday) || \ + ((WEEKDAY) == RTC_Weekday_Thursday) || \ + ((WEEKDAY) == RTC_Weekday_Friday) || \ + ((WEEKDAY) == RTC_Weekday_Saturday) || \ + ((WEEKDAY) == RTC_Weekday_Sunday)) + +/** + * @} + */ + + +/** @defgroup RTC_AlarmDateWeekDay_Definitions + * @{ + */ +#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000) +#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000) + +#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \ + ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay)) + +/** + * @} + */ + + +/** @defgroup RTC_AlarmMask_Definitions + * @{ + */ +#define RTC_AlarmMask_None ((uint32_t)0x00000000) +#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000) +#define RTC_AlarmMask_Hours ((uint32_t)0x00800000) +#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000) +#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080) +#define RTC_AlarmMask_All ((uint32_t)0x80808080) +#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) + +/** + * @} + */ + +/** @defgroup RTC_Alarms_Definitions + * @{ + */ +#define RTC_Alarm_A ((uint32_t)0x00000100) +#define IS_RTC_ALARM(ALARM) ((ALARM) == RTC_Alarm_A) +#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A)) != (uint32_t)RESET) + +/** + * @} + */ + +/** @defgroup RTC_Alarm_Sub_Seconds_Masks Definitions. + * @{ + */ +#define RTC_AlarmSubSecondMask_All ((uint8_t)0x00) /*!< All Alarm SS fields are masked. + There is no comparison on sub seconds + for Alarm */ +#define RTC_AlarmSubSecondMask_SS14_1 ((uint8_t)0x01) /*!< SS[14:1] are don't care in Alarm + comparison. Only SS[0] is compared. */ +#define RTC_AlarmSubSecondMask_SS14_2 ((uint8_t)0x02) /*!< SS[14:2] are don't care in Alarm + comparison. Only SS[1:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_3 ((uint8_t)0x03) /*!< SS[14:3] are don't care in Alarm + comparison. Only SS[2:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_4 ((uint8_t)0x04) /*!< SS[14:4] are don't care in Alarm + comparison. Only SS[3:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_5 ((uint8_t)0x05) /*!< SS[14:5] are don't care in Alarm + comparison. Only SS[4:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_6 ((uint8_t)0x06) /*!< SS[14:6] are don't care in Alarm + comparison. Only SS[5:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_7 ((uint8_t)0x07) /*!< SS[14:7] are don't care in Alarm + comparison. Only SS[6:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_8 ((uint8_t)0x08) /*!< SS[14:8] are don't care in Alarm + comparison. Only SS[7:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_9 ((uint8_t)0x09) /*!< SS[14:9] are don't care in Alarm + comparison. Only SS[8:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_10 ((uint8_t)0x0A) /*!< SS[14:10] are don't care in Alarm + comparison. Only SS[9:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_11 ((uint8_t)0x0B) /*!< SS[14:11] are don't care in Alarm + comparison. Only SS[10:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_12 ((uint8_t)0x0C) /*!< SS[14:12] are don't care in Alarm + comparison.Only SS[11:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_13 ((uint8_t)0x0D) /*!< SS[14:13] are don't care in Alarm + comparison. Only SS[12:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14 ((uint8_t)0x0E) /*!< SS[14] is don't care in Alarm + comparison.Only SS[13:0] are compared */ +#define RTC_AlarmSubSecondMask_None ((uint8_t)0x0F) /*!< SS[14:0] are compared and must match + to activate alarm. */ +#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_AlarmSubSecondMask_All) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14) || \ + ((MASK) == RTC_AlarmSubSecondMask_None)) +/** + * @} + */ + +/** @defgroup RTC_Alarm_Sub_Seconds_Value + * @{ + */ + +#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF) + +/** + * @} + */ + +/** @defgroup RTC_Time_Stamp_Edges_definitions + * @{ + */ +#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000) +#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008) +#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \ + ((EDGE) == RTC_TimeStampEdge_Falling)) +/** + * @} + */ + +/** @defgroup RTC_Output_selection_Definitions + * @{ + */ +#define RTC_Output_Disable ((uint32_t)0x00000000) +#define RTC_Output_AlarmA ((uint32_t)0x00200000) + +#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \ + ((OUTPUT) == RTC_Output_AlarmA)) + +/** + * @} + */ + +/** @defgroup RTC_Output_Polarity_Definitions + * @{ + */ +#define RTC_OutputPolarity_High ((uint32_t)0x00000000) +#define RTC_OutputPolarity_Low ((uint32_t)0x00100000) +#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \ + ((POL) == RTC_OutputPolarity_Low)) +/** + * @} + */ + + +/** @defgroup RTC_Calib_Output_selection_Definitions + * @{ + */ +#define RTC_CalibOutput_512Hz ((uint32_t)0x00000000) +#define RTC_CalibOutput_1Hz ((uint32_t)0x00080000) +#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CalibOutput_512Hz) || \ + ((OUTPUT) == RTC_CalibOutput_1Hz)) +/** + * @} + */ + +/** @defgroup RTC_Smooth_calib_period_Definitions + * @{ + */ +#define RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation + period is 32s, else 2exp20 RTCCLK seconds */ +#define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation + period is 16s, else 2exp19 RTCCLK seconds */ +#define RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation + period is 8s, else 2exp18 RTCCLK seconds */ +#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \ + ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \ + ((PERIOD) == RTC_SmoothCalibPeriod_8sec)) + +/** + * @} + */ + +/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions + * @{ + */ +#define RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added + during a X -second window = Y - CALM[8:0]. + with Y = 512, 256, 128 when X = 32, 16, 8 */ +#define RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited + during a 32-second window = CALM[8:0]. */ +#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \ + ((PLUS) == RTC_SmoothCalibPlusPulses_Reset)) + +/** + * @} + */ + +/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions + * @{ + */ +#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF) + +/** + * @} + */ + +/** @defgroup RTC_DayLightSaving_Definitions + * @{ + */ +#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000) +#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000) +#define IS_RTC_DAYLIGHT_SAVING(SAVING) (((SAVING) == RTC_DayLightSaving_SUB1H) || \ + ((SAVING) == RTC_DayLightSaving_ADD1H)) + +#define RTC_StoreOperation_Reset ((uint32_t)0x00000000) +#define RTC_StoreOperation_Set ((uint32_t)0x00040000) +#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \ + ((OPERATION) == RTC_StoreOperation_Set)) +/** + * @} + */ + +/** @defgroup RTC_Tamper_Trigger_Definitions + * @{ + */ +#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000) +#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001) +#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000) +#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000001) +#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \ + ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \ + ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \ + ((TRIGGER) == RTC_TamperTrigger_HighLevel)) + +/** + * @} + */ + +/** @defgroup RTC_Tamper_Filter_Definitions + * @{ + */ +#define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */ + +#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2 + consecutive samples at the active level */ +#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4 + consecutive samples at the active level */ +#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8 + consecutive samples at the active leve. */ +#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \ + ((FILTER) == RTC_TamperFilter_2Sample) || \ + ((FILTER) == RTC_TamperFilter_4Sample) || \ + ((FILTER) == RTC_TamperFilter_8Sample)) +/** + * @} + */ + +/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions + * @{ + */ +#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 32768 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x00000100) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 16384 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 8192 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 4096 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 2048 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 1024 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 512 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 256 */ +#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256)) + +/** + * @} + */ + + /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions + * @{ + */ +#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before + sampling during 1 RTCCLK cycle */ +#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before + sampling during 2 RTCCLK cycles */ +#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before + sampling during 4 RTCCLK cycles */ +#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before + sampling during 8 RTCCLK cycles */ + +#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \ + ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \ + ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \ + ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK)) +/** + * @} + */ + +/** @defgroup RTC_Tamper_Pins_Definitions + * @{ + */ +#define RTC_Tamper_1 RTC_TAFCR_TAMP1E /*!< Tamper detection enable for + input tamper 1 */ +#define RTC_Tamper_2 RTC_TAFCR_TAMP2E /*!< Tamper detection enable for + input tamper 2 */ +#define RTC_Tamper_3 RTC_TAFCR_TAMP3E /*!< Tamper detection enable for + input tamper 3 */ + +#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET)) + +/** + * @} + */ + +/** @defgroup RTC_Output_Type_ALARM_OUT + * @{ + */ +#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000) +#define RTC_OutputType_PushPull ((uint32_t)0x00040000) +#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \ + ((TYPE) == RTC_OutputType_PushPull)) + +/** + * @} + */ + +/** @defgroup RTC_Add_1_Second_Parameter_Definitions + * @{ + */ +#define RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000) +#define RTC_ShiftAdd1S_Set ((uint32_t)0x80000000) +#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \ + ((SEL) == RTC_ShiftAdd1S_Set)) +/** + * @} + */ + +/** @defgroup RTC_Substract_Fraction_Of_Second_Value + * @{ + */ +#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF) + +/** + * @} + */ + +/** @defgroup RTC_Backup_Registers_Definitions + * @{ + */ + +#define RTC_BKP_DR0 ((uint32_t)0x00000000) +#define RTC_BKP_DR1 ((uint32_t)0x00000001) +#define RTC_BKP_DR2 ((uint32_t)0x00000002) +#define RTC_BKP_DR3 ((uint32_t)0x00000003) +#define RTC_BKP_DR4 ((uint32_t)0x00000004) +#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \ + ((BKP) == RTC_BKP_DR1) || \ + ((BKP) == RTC_BKP_DR2) || \ + ((BKP) == RTC_BKP_DR3) || \ + ((BKP) == RTC_BKP_DR4)) +/** + * @} + */ + +/** @defgroup RTC_Input_parameter_format_definitions + * @{ + */ +#define RTC_Format_BIN ((uint32_t)0x000000000) +#define RTC_Format_BCD ((uint32_t)0x000000001) +#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD)) + +/** + * @} + */ + +/** @defgroup RTC_Flags_Definitions + * @{ + */ +#define RTC_FLAG_RECALPF ((uint32_t)0x00010000) +#define RTC_FLAG_TAMP3F ((uint32_t)0x00008000) +#define RTC_FLAG_TAMP2F ((uint32_t)0x00004000) +#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000) +#define RTC_FLAG_TSOVF ((uint32_t)0x00001000) +#define RTC_FLAG_TSF ((uint32_t)0x00000800) +#define RTC_FLAG_ALRAF ((uint32_t)0x00000100) +#define RTC_FLAG_INITF ((uint32_t)0x00000040) +#define RTC_FLAG_RSF ((uint32_t)0x00000020) +#define RTC_FLAG_INITS ((uint32_t)0x00000010) +#define RTC_FLAG_SHPF ((uint32_t)0x00000008) + +#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RECALPF) || ((FLAG) == RTC_FLAG_TAMP3F) || \ + ((FLAG) == RTC_FLAG_TAMP2F) || ((FLAG) == RTC_FLAG_TAMP1F) || \ + ((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \ + ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \ + ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_INITS) || \ + ((FLAG) == RTC_FLAG_SHPF)) +#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF06DF) == (uint32_t)RESET)) + +/** + * @} + */ + +/** @defgroup RTC_Interrupts_Definitions + * @{ + */ +#define RTC_IT_TS ((uint32_t)0x00008000) +#define RTC_IT_ALRA ((uint32_t)0x00001000) +#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */ +#define RTC_IT_TAMP1 ((uint32_t)0x00020000) +#define RTC_IT_TAMP2 ((uint32_t)0x00040000) +#define RTC_IT_TAMP3 ((uint32_t)0x00080000) + +#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF6FFB) == (uint32_t)RESET)) +#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_ALRA) || \ + ((IT) == RTC_IT_TAMP1) || ((IT) == RTC_IT_TAMP2) || \ + ((IT) == RTC_IT_TAMP3)) +#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF16FFF) == (uint32_t)RESET)) + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +/* Function used to set the RTC configuration to the default reset state *****/ +ErrorStatus RTC_DeInit(void); + + +/* Initialization and Configuration functions *********************************/ +ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct); +void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct); +void RTC_WriteProtectionCmd(FunctionalState NewState); +ErrorStatus RTC_EnterInitMode(void); +void RTC_ExitInitMode(void); +ErrorStatus RTC_WaitForSynchro(void); +ErrorStatus RTC_RefClockCmd(FunctionalState NewState); +void RTC_BypassShadowCmd(FunctionalState NewState); + +/* Time and Date configuration functions **************************************/ +ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); +void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct); +void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); +uint32_t RTC_GetSubSecond(void); +ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); +void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct); +void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); + +/* Alarms (Alarm A) configuration functions **********************************/ +void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); +void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct); +void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); +ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState); +void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint8_t RTC_AlarmSubSecondMask); +uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm); + +/* Daylight Saving configuration functions ************************************/ +void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation); +uint32_t RTC_GetStoreOperation(void); + +/* Output pin Configuration function ******************************************/ +void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity); + +/* Digital Calibration configuration functions ********************************/ +void RTC_CalibOutputCmd(FunctionalState NewState); +void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput); +ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, + uint32_t RTC_SmoothCalibPlusPulses, + uint32_t RTC_SmouthCalibMinusPulsesValue); + +/* TimeStamp configuration functions ******************************************/ +void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState); +void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, RTC_DateTypeDef* RTC_StampDateStruct); +uint32_t RTC_GetTimeStampSubSecond(void); + +/* Tampers configuration functions ********************************************/ +void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger); +void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState); +void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter); +void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq); +void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration); +void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState); +void RTC_TamperPullUpCmd(FunctionalState NewState); + +/* Backup Data Registers configuration functions ******************************/ +void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data); +uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR); + +/* Output Type Config configuration functions *********************************/ +void RTC_OutputTypeConfig(uint32_t RTC_OutputType); + +/* RTC_Shift_control_synchonisation_functions *********************************/ +ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS); + +/* Interrupts and flags management functions **********************************/ +void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState); +FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG); +void RTC_ClearFlag(uint32_t RTC_FLAG); +ITStatus RTC_GetITStatus(uint32_t RTC_IT); +void RTC_ClearITPendingBit(uint32_t RTC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F0XX_RTC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_spi.h b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_spi.h new file mode 100644 index 0000000..9fa2505 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_spi.h @@ -0,0 +1,587 @@ +/** + ****************************************************************************** + * @file stm32f0xx_spi.h + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file contains all the functions prototypes for the SPI + * firmware library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_SPI_H +#define __STM32F0XX_SPI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief SPI Init structure definition + */ + +typedef struct +{ + uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_data_direction */ + + uint16_t SPI_Mode; /*!< Specifies the SPI mode (Master/Slave). + This parameter can be a value of @ref SPI_mode */ + + uint16_t SPI_DataSize; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ +}SPI_InitTypeDef; + + +/** + * @brief I2S Init structure definition + */ + +typedef struct +{ + uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref SPI_I2S_Mode */ + + uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref SPI_I2S_Standard */ + + uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref SPI_I2S_Data_Format */ + + uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref SPI_I2S_MCLK_Output */ + + uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref SPI_I2S_Audio_Frequency */ + + uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref SPI_I2S_Clock_Polarity */ +}I2S_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup SPI_Exported_Constants + * @{ + */ + +#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ + ((PERIPH) == SPI2)) + +#define IS_SPI_1_PERIPH(PERIPH) (((PERIPH) == SPI1)) + +/** @defgroup SPI_data_direction + * @{ + */ + +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) +#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ + ((MODE) == SPI_Direction_2Lines_RxOnly) || \ + ((MODE) == SPI_Direction_1Line_Rx) || \ + ((MODE) == SPI_Direction_1Line_Tx)) +/** + * @} + */ + +/** @defgroup SPI_mode + * @{ + */ + +#define SPI_Mode_Master ((uint16_t)0x0104) +#define SPI_Mode_Slave ((uint16_t)0x0000) +#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ + ((MODE) == SPI_Mode_Slave)) +/** + * @} + */ + +/** @defgroup SPI_data_size + * @{ + */ + +#define SPI_DataSize_4b ((uint16_t)0x0300) +#define SPI_DataSize_5b ((uint16_t)0x0400) +#define SPI_DataSize_6b ((uint16_t)0x0500) +#define SPI_DataSize_7b ((uint16_t)0x0600) +#define SPI_DataSize_8b ((uint16_t)0x0700) +#define SPI_DataSize_9b ((uint16_t)0x0800) +#define SPI_DataSize_10b ((uint16_t)0x0900) +#define SPI_DataSize_11b ((uint16_t)0x0A00) +#define SPI_DataSize_12b ((uint16_t)0x0B00) +#define SPI_DataSize_13b ((uint16_t)0x0C00) +#define SPI_DataSize_14b ((uint16_t)0x0D00) +#define SPI_DataSize_15b ((uint16_t)0x0E00) +#define SPI_DataSize_16b ((uint16_t)0x0F00) +#define IS_SPI_DATA_SIZE(SIZE) (((SIZE) == SPI_DataSize_4b) || \ + ((SIZE) == SPI_DataSize_5b) || \ + ((SIZE) == SPI_DataSize_6b) || \ + ((SIZE) == SPI_DataSize_7b) || \ + ((SIZE) == SPI_DataSize_8b) || \ + ((SIZE) == SPI_DataSize_9b) || \ + ((SIZE) == SPI_DataSize_10b) || \ + ((SIZE) == SPI_DataSize_11b) || \ + ((SIZE) == SPI_DataSize_12b) || \ + ((SIZE) == SPI_DataSize_13b) || \ + ((SIZE) == SPI_DataSize_14b) || \ + ((SIZE) == SPI_DataSize_15b) || \ + ((SIZE) == SPI_DataSize_16b)) +/** + * @} + */ + +/** @defgroup SPI_CRC_length + * @{ + */ + +#define SPI_CRCLength_8b ((uint16_t)0x0000) +#define SPI_CRCLength_16b SPI_CR1_CRCL +#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRCLength_8b) || \ + ((LENGTH) == SPI_CRCLength_16b)) +/** + * @} + */ + +/** @defgroup SPI_Clock_Polarity + * @{ + */ + +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High SPI_CR1_CPOL +#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ + ((CPOL) == SPI_CPOL_High)) +/** + * @} + */ + +/** @defgroup SPI_Clock_Phase + * @{ + */ + +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge SPI_CR1_CPHA +#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ + ((CPHA) == SPI_CPHA_2Edge)) +/** + * @} + */ + +/** @defgroup SPI_Slave_Select_management + * @{ + */ + +#define SPI_NSS_Soft SPI_CR1_SSM +#define SPI_NSS_Hard ((uint16_t)0x0000) +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ + ((NSS) == SPI_NSS_Hard)) +/** + * @} + */ + +/** @defgroup SPI_BaudRate_Prescaler + * @{ + */ + +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) +#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_256)) +/** + * @} + */ + +/** @defgroup SPI_MSB_LSB_transmission + * @{ + */ + +#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_LSB SPI_CR1_LSBFIRST +#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ + ((BIT) == SPI_FirstBit_LSB)) +/** + * @} + */ + +/** @defgroup SPI_I2S_Mode + * @{ + */ + +#define I2S_Mode_SlaveTx ((uint16_t)0x0000) +#define I2S_Mode_SlaveRx ((uint16_t)0x0100) +#define I2S_Mode_MasterTx ((uint16_t)0x0200) +#define I2S_Mode_MasterRx ((uint16_t)0x0300) +#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ + ((MODE) == I2S_Mode_SlaveRx) || \ + ((MODE) == I2S_Mode_MasterTx)|| \ + ((MODE) == I2S_Mode_MasterRx)) +/** + * @} + */ + +/** @defgroup SPI_I2S_Standard + * @{ + */ + +#define I2S_Standard_Phillips ((uint16_t)0x0000) +#define I2S_Standard_MSB ((uint16_t)0x0010) +#define I2S_Standard_LSB ((uint16_t)0x0020) +#define I2S_Standard_PCMShort ((uint16_t)0x0030) +#define I2S_Standard_PCMLong ((uint16_t)0x00B0) +#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ + ((STANDARD) == I2S_Standard_MSB) || \ + ((STANDARD) == I2S_Standard_LSB) || \ + ((STANDARD) == I2S_Standard_PCMShort) || \ + ((STANDARD) == I2S_Standard_PCMLong)) +/** + * @} + */ + +/** @defgroup SPI_I2S_Data_Format + * @{ + */ + +#define I2S_DataFormat_16b ((uint16_t)0x0000) +#define I2S_DataFormat_16bextended ((uint16_t)0x0001) +#define I2S_DataFormat_24b ((uint16_t)0x0003) +#define I2S_DataFormat_32b ((uint16_t)0x0005) +#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ + ((FORMAT) == I2S_DataFormat_16bextended) || \ + ((FORMAT) == I2S_DataFormat_24b) || \ + ((FORMAT) == I2S_DataFormat_32b)) +/** + * @} + */ + +/** @defgroup SPI_I2S_MCLK_Output + * @{ + */ + +#define I2S_MCLKOutput_Enable SPI_I2SPR_MCKOE +#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) +#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ + ((OUTPUT) == I2S_MCLKOutput_Disable)) +/** + * @} + */ + +/** @defgroup SPI_I2S_Audio_Frequency + * @{ + */ + +#define I2S_AudioFreq_192k ((uint32_t)192000) +#define I2S_AudioFreq_96k ((uint32_t)96000) +#define I2S_AudioFreq_48k ((uint32_t)48000) +#define I2S_AudioFreq_44k ((uint32_t)44100) +#define I2S_AudioFreq_32k ((uint32_t)32000) +#define I2S_AudioFreq_22k ((uint32_t)22050) +#define I2S_AudioFreq_16k ((uint32_t)16000) +#define I2S_AudioFreq_11k ((uint32_t)11025) +#define I2S_AudioFreq_8k ((uint32_t)8000) +#define I2S_AudioFreq_Default ((uint32_t)2) + +#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ + ((FREQ) <= I2S_AudioFreq_192k)) || \ + ((FREQ) == I2S_AudioFreq_Default)) +/** + * @} + */ + +/** @defgroup SPI_I2S_Clock_Polarity + * @{ + */ + +#define I2S_CPOL_Low ((uint16_t)0x0000) +#define I2S_CPOL_High SPI_I2SCFGR_CKPOL +#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ + ((CPOL) == I2S_CPOL_High)) +/** + * @} + */ + +/** @defgroup SPI_FIFO_reception_threshold + * @{ + */ + +#define SPI_RxFIFOThreshold_HF ((uint16_t)0x0000) +#define SPI_RxFIFOThreshold_QF SPI_CR2_FRXTH +#define IS_SPI_RX_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_RxFIFOThreshold_HF) || \ + ((THRESHOLD) == SPI_RxFIFOThreshold_QF)) +/** + * @} + */ + +/** @defgroup SPI_I2S_DMA_transfer_requests + * @{ + */ + +#define SPI_I2S_DMAReq_Tx SPI_CR2_TXDMAEN +#define SPI_I2S_DMAReq_Rx SPI_CR2_RXDMAEN +#define IS_SPI_I2S_DMA_REQ(REQ) ((((REQ) & (uint16_t)0xFFFC) == 0x00) && ((REQ) != 0x00)) +/** + * @} + */ + +/** @defgroup SPI_last_DMA_transfers + * @{ + */ + +#define SPI_LastDMATransfer_TxEvenRxEven ((uint16_t)0x0000) +#define SPI_LastDMATransfer_TxOddRxEven ((uint16_t)0x4000) +#define SPI_LastDMATransfer_TxEvenRxOdd ((uint16_t)0x2000) +#define SPI_LastDMATransfer_TxOddRxOdd ((uint16_t)0x6000) +#define IS_SPI_LAST_DMA_TRANSFER(TRANSFER) (((TRANSFER) == SPI_LastDMATransfer_TxEvenRxEven) || \ + ((TRANSFER) == SPI_LastDMATransfer_TxOddRxEven) || \ + ((TRANSFER) == SPI_LastDMATransfer_TxEvenRxOdd) || \ + ((TRANSFER) == SPI_LastDMATransfer_TxOddRxOdd)) +/** + * @} + */ +/** @defgroup SPI_NSS_internal_software_management + * @{ + */ + +#define SPI_NSSInternalSoft_Set SPI_CR1_SSI +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) +#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ + ((INTERNAL) == SPI_NSSInternalSoft_Reset)) +/** + * @} + */ + +/** @defgroup SPI_CRC_Transmit_Receive + * @{ + */ + +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) +#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) +/** + * @} + */ + +/** @defgroup SPI_direction_transmit_receive + * @{ + */ + +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) +#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ + ((DIRECTION) == SPI_Direction_Tx)) +/** + * @} + */ + +/** @defgroup SPI_I2S_interrupts_definition + * @{ + */ + +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) + +#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ + ((IT) == SPI_I2S_IT_RXNE) || \ + ((IT) == SPI_I2S_IT_ERR)) + +#define I2S_IT_UDR ((uint8_t)0x53) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_I2S_IT_FRE ((uint8_t)0x58) + +#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \ + ((IT) == SPI_I2S_IT_OVR) || ((IT) == SPI_IT_MODF) || \ + ((IT) == SPI_I2S_IT_FRE)|| ((IT) == I2S_IT_UDR)) +/** + * @} + */ + + +/** @defgroup SPI_transmission_fifo_status_level + * @{ + */ + +#define SPI_TransmissionFIFOStatus_Empty ((uint16_t)0x0000) +#define SPI_TransmissionFIFOStatus_1QuarterFull ((uint16_t)0x0800) +#define SPI_TransmissionFIFOStatus_HalfFull ((uint16_t)0x1000) +#define SPI_TransmissionFIFOStatus_Full ((uint16_t)0x1800) + +/** + * @} + */ + +/** @defgroup SPI_reception_fifo_status_level + * @{ + */ +#define SPI_ReceptionFIFOStatus_Empty ((uint16_t)0x0000) +#define SPI_ReceptionFIFOStatus_1QuarterFull ((uint16_t)0x0200) +#define SPI_ReceptionFIFOStatus_HalfFull ((uint16_t)0x0400) +#define SPI_ReceptionFIFOStatus_Full ((uint16_t)0x0600) + +/** + * @} + */ + + +/** @defgroup SPI_I2S_flags_definition + * @{ + */ + +#define SPI_I2S_FLAG_RXNE SPI_SR_RXNE +#define SPI_I2S_FLAG_TXE SPI_SR_TXE +#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE +#define I2S_FLAG_UDR SPI_SR_UDR +#define SPI_FLAG_CRCERR SPI_SR_CRCERR +#define SPI_FLAG_MODF SPI_SR_MODF +#define SPI_I2S_FLAG_OVR SPI_SR_OVR +#define SPI_I2S_FLAG_BSY SPI_SR_BSY +#define SPI_I2S_FLAG_FRE SPI_SR_FRE + + + +#define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) +#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ + ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ + ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \ + ((FLAG) == SPI_I2S_FLAG_FRE)|| ((FLAG) == I2S_FLAG_CHSIDE)|| \ + ((FLAG) == I2S_FLAG_UDR)) +/** + * @} + */ + +/** @defgroup SPI_CRC_polynomial + * @{ + */ + +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Initialization and Configuration functions *********************************/ +void SPI_I2S_DeInit(SPI_TypeDef* SPIx); +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); +void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); +void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); +void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold); +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); + +/* Data transfers functions ***************************************************/ +void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data); +void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data); +uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx); +uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx); + +/* Hardware CRC Calculation functions *****************************************/ +void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength); +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_TransmitCRC(SPI_TypeDef* SPIx); +uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); + +/* DMA transfers management functions *****************************************/ +void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); +void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer); + +/* Interrupts and flags management functions **********************************/ +void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); +uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx); +uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx); +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F0XX_SPI_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_syscfg.h b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_syscfg.h new file mode 100644 index 0000000..6d5e826 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_syscfg.h @@ -0,0 +1,224 @@ +/** + ****************************************************************************** + * @file stm32f0xx_syscfg.h + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file contains all the functions prototypes for the SYSCFG firmware + * library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/*!< Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_SYSCFG_H +#define __STM32F0XX_SYSCFG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/*!< Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SYSCFG + * @{ + */ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup SYSCFG_Exported_Constants + * @{ + */ + +/** @defgroup SYSCFG_EXTI_Port_Sources + * @{ + */ +#define EXTI_PortSourceGPIOA ((uint8_t)0x00) +#define EXTI_PortSourceGPIOB ((uint8_t)0x01) +#define EXTI_PortSourceGPIOC ((uint8_t)0x02) +#define EXTI_PortSourceGPIOD ((uint8_t)0x03) +#define EXTI_PortSourceGPIOF ((uint8_t)0x05) + +#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOF)) +/** + * @} + */ + +/** @defgroup SYSCFG_EXTI_Pin_sources + * @{ + */ +#define EXTI_PinSource0 ((uint8_t)0x00) +#define EXTI_PinSource1 ((uint8_t)0x01) +#define EXTI_PinSource2 ((uint8_t)0x02) +#define EXTI_PinSource3 ((uint8_t)0x03) +#define EXTI_PinSource4 ((uint8_t)0x04) +#define EXTI_PinSource5 ((uint8_t)0x05) +#define EXTI_PinSource6 ((uint8_t)0x06) +#define EXTI_PinSource7 ((uint8_t)0x07) +#define EXTI_PinSource8 ((uint8_t)0x08) +#define EXTI_PinSource9 ((uint8_t)0x09) +#define EXTI_PinSource10 ((uint8_t)0x0A) +#define EXTI_PinSource11 ((uint8_t)0x0B) +#define EXTI_PinSource12 ((uint8_t)0x0C) +#define EXTI_PinSource13 ((uint8_t)0x0D) +#define EXTI_PinSource14 ((uint8_t)0x0E) +#define EXTI_PinSource15 ((uint8_t)0x0F) + +#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \ + ((PINSOURCE) == EXTI_PinSource1) || \ + ((PINSOURCE) == EXTI_PinSource2) || \ + ((PINSOURCE) == EXTI_PinSource3) || \ + ((PINSOURCE) == EXTI_PinSource4) || \ + ((PINSOURCE) == EXTI_PinSource5) || \ + ((PINSOURCE) == EXTI_PinSource6) || \ + ((PINSOURCE) == EXTI_PinSource7) || \ + ((PINSOURCE) == EXTI_PinSource8) || \ + ((PINSOURCE) == EXTI_PinSource9) || \ + ((PINSOURCE) == EXTI_PinSource10) || \ + ((PINSOURCE) == EXTI_PinSource11) || \ + ((PINSOURCE) == EXTI_PinSource12) || \ + ((PINSOURCE) == EXTI_PinSource13) || \ + ((PINSOURCE) == EXTI_PinSource14) || \ + ((PINSOURCE) == EXTI_PinSource15)) +/** + * @} + */ + +/** @defgroup SYSCFG_Memory_Remap_Config + * @{ + */ +#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00) +#define SYSCFG_MemoryRemap_SystemMemory ((uint8_t)0x01) +#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03) + + +#define IS_SYSCFG_MEMORY_REMAP(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ + ((REMAP) == SYSCFG_MemoryRemap_SystemMemory) || \ + ((REMAP) == SYSCFG_MemoryRemap_SRAM)) + +/** + * @} + */ + +/** @defgroup SYSCFG_DMA_Remap_Config + * @{ + */ +#define SYSCFG_DMARemap_TIM17 SYSCFG_CFGR1_TIM17_DMA_RMP /* Remap TIM17 DMA requests from channel1 to channel2 */ +#define SYSCFG_DMARemap_TIM16 SYSCFG_CFGR1_TIM16_DMA_RMP /* Remap TIM16 DMA requests from channel3 to channel4 */ +#define SYSCFG_DMARemap_USART1Rx SYSCFG_CFGR1_USART1RX_DMA_RMP /* Remap USART1 Rx DMA requests from channel3 to channel5 */ +#define SYSCFG_DMARemap_USART1Tx SYSCFG_CFGR1_USART1TX_DMA_RMP /* Remap USART1 Tx DMA requests from channel2 to channel4 */ +#define SYSCFG_DMARemap_ADC1 SYSCFG_CFGR1_ADC_DMA_RMP /* Remap ADC1 DMA requests from channel1 to channel2 */ + +#define IS_SYSCFG_DMA_REMAP(REMAP) (((REMAP) == SYSCFG_DMARemap_TIM17) || \ + ((REMAP) == SYSCFG_DMARemap_TIM16) || \ + ((REMAP) == SYSCFG_DMARemap_USART1Rx) || \ + ((REMAP) == SYSCFG_DMARemap_USART1Tx) || \ + ((REMAP) == SYSCFG_DMARemap_ADC1)) + +/** + * @} + */ + +/** @defgroup SYSCFG_I2C_FastModePlus_Config + * @{ + */ +#define SYSCFG_I2CFastModePlus_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /* Enable Fast Mode Plus on PB6 */ +#define SYSCFG_I2CFastModePlus_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /* Enable Fast Mode Plus on PB7 */ +#define SYSCFG_I2CFastModePlus_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /* Enable Fast Mode Plus on PB8 */ +#define SYSCFG_I2CFastModePlus_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /* Enable Fast Mode Plus on PB9 */ + +#define IS_SYSCFG_I2C_FMP(PIN) (((PIN) == SYSCFG_I2CFastModePlus_PB6) || \ + ((PIN) == SYSCFG_I2CFastModePlus_PB7) || \ + ((PIN) == SYSCFG_I2CFastModePlus_PB8) || \ + ((PIN) == SYSCFG_I2CFastModePlus_PB9)) + +/** + * @} + */ + +/** @defgroup SYSCFG_Lock_Config + * @{ + */ +#define SYSCFG_Break_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Connects the PVD event to the Break Input of TIM1 */ +#define SYSCFG_Break_SRAMParity SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Connects the SRAM_PARITY error signal to the Break Input of TIM1 */ +#define SYSCFG_Break_Lockup SYSCFG_CFGR2_LOCKUP_LOCK /*!< Connects Lockup output of CortexM0 to the break input of TIM1 */ + +#define IS_SYSCFG_LOCK_CONFIG(CONFIG) (((CONFIG) == SYSCFG_Break_PVD) || \ + ((CONFIG) == SYSCFG_Break_SRAMParity) || \ + ((CONFIG) == SYSCFG_Break_Lockup)) + +/** + * @} + */ + +/** @defgroup SYSCFG_flags_definition + * @{ + */ + +#define SYSCFG_FLAG_PE SYSCFG_CFGR2_SRAM_PE + +#define IS_SYSCFG_FLAG(FLAG) (((FLAG) == SYSCFG_FLAG_PE)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Function used to set the SYSCFG configuration to the default reset state **/ +void SYSCFG_DeInit(void); + +/* SYSCFG configuration functions *********************************************/ +void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap); +void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState); +void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState); +void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex); +void SYSCFG_BreakConfig(uint32_t SYSCFG_Break); +FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag); +void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F0XX_SYSCFG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_tim.h b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_tim.h new file mode 100644 index 0000000..f624095 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_tim.h @@ -0,0 +1,1182 @@ +/** + ****************************************************************************** + * @file stm32f0xx_tim.h + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file contains all the functions prototypes for the TIM + * firmware library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_TIM_H +#define __STM32F0XX_TIM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief TIM Time Base Init structure definition + * @note This sturcture is used with all TIMx. + */ + +typedef struct +{ + uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF. */ + + uint16_t TIM_ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_Clock_Division_CKD */ + + uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + @note This parameter is valid only for TIM1. */ +} TIM_TimeBaseInitTypeDef; + +/** + * @brief TIM Output Compare Init structure definition + */ + +typedef struct +{ + uint16_t TIM_OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_state */ + + uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_N_state + @note This parameter is valid only for TIM1. */ + + uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF ( or 0xFFFFFFFF + for TIM2) */ + + uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1. */ + + uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1. */ + + uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1. */ +} TIM_OCInitTypeDef; + +/** + * @brief TIM Input Capture Init structure definition + */ + +typedef struct +{ + + uint16_t TIM_Channel; /*!< Specifies the TIM channel. + This parameter can be a value of @ref TIM_Channel */ + + uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint16_t TIM_ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between 0x0 and 0xF */ +} TIM_ICInitTypeDef; + +/** + * @brief TIM_BDTR structure definition + * @note This sturcture is used only with TIM1. + */ + +typedef struct +{ + + uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + + uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. + This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. + This parameter can be a value of @ref TIM_Lock_level */ + + uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between 0x00 and 0xFF */ + + uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + + uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref TIM_Break_Polarity */ + + uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BDTRInitTypeDef; + +/** + * @brief TIM Input Capture Init structure definition + */ + +/* Exported constants --------------------------------------------------------*/ + + +/** @defgroup TIM_Exported_constants + * @{ + */ + +#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM14)|| \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST1: TIM 1 */ +#define IS_TIM_LIST1_PERIPH(PERIPH) ((PERIPH) == TIM1) + +/* LIST2: TIM 1, 15, 16 and 17 */ +#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST3: TIM 1, 2 and 3 */ +#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3)) + +/* LIST4: TIM 1, 2, 3, 14, 15, 16 and 17 */ +#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM14) || \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST4: TIM 1, 2, 3, 15, 16 and 17 */ +#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST5: TIM 1, 2, 3 and 15 */ +#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM15)) + +/* LIST7: TIM 1, 2, 3, 6 and 14 */ +#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM14)) + +/* LIST8: TIM 1, 2, 3 and 14 */ +#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM14)) + +/* LIST9: TIM 1, 2, 3, 6 and 15 */ +#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM15)) + +/* LIST10: TIM 1, 2, 3, 6, 15, 16 and 17 */ +#define IS_TIM_LIST10_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST1: TIM 11 */ +#define IS_TIM_LIST11_PERIPH(PERIPH) ((PERIPH) == TIM14) + + +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_and_PWM_modes + * @{ + */ + +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) +#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ + ((MODE) == TIM_OCMode_Active) || \ + ((MODE) == TIM_OCMode_Inactive) || \ + ((MODE) == TIM_OCMode_Toggle)|| \ + ((MODE) == TIM_OCMode_PWM1) || \ + ((MODE) == TIM_OCMode_PWM2)) +#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ + ((MODE) == TIM_OCMode_Active) || \ + ((MODE) == TIM_OCMode_Inactive) || \ + ((MODE) == TIM_OCMode_Toggle)|| \ + ((MODE) == TIM_OCMode_PWM1) || \ + ((MODE) == TIM_OCMode_PWM2) || \ + ((MODE) == TIM_ForcedAction_Active) || \ + ((MODE) == TIM_ForcedAction_InActive)) +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode + * @{ + */ + +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) +#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ + ((MODE) == TIM_OPMode_Repetitive)) +/** + * @} + */ + +/** @defgroup TIM_Channel + * @{ + */ + +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) + +#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2) || \ + ((CHANNEL) == TIM_Channel_3) || \ + ((CHANNEL) == TIM_Channel_4)) +#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2) || \ + ((CHANNEL) == TIM_Channel_3)) +#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2)) + +/** + * @} + */ + +/** @defgroup TIM_Clock_Division_CKD + * @{ + */ + +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) +#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ + ((DIV) == TIM_CKD_DIV2) || \ + ((DIV) == TIM_CKD_DIV4)) +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode + * @{ + */ + +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) +#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ + ((MODE) == TIM_CounterMode_Down) || \ + ((MODE) == TIM_CounterMode_CenterAligned1) || \ + ((MODE) == TIM_CounterMode_CenterAligned2) || \ + ((MODE) == TIM_CounterMode_CenterAligned3)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity + * @{ + */ + +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) +#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ + ((POLARITY) == TIM_OCPolarity_Low)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity + * @{ + */ + +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) +#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ + ((POLARITY) == TIM_OCNPolarity_Low)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_state + * @{ + */ + +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) +#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ + ((STATE) == TIM_OutputState_Enable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_state + * @{ + */ + +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) +#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ + ((STATE) == TIM_OutputNState_Enable)) +/** + * @} + */ + +/** @defgroup TIM_Capture_Compare_state + * @{ + */ + +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) +#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ + ((CCX) == TIM_CCx_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Capture_Compare_N_state + * @{ + */ + +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) +#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ + ((CCXN) == TIM_CCxN_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Break_Input_enable_disable + * @{ + */ + +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) +#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ + ((STATE) == TIM_Break_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Break_Polarity + * @{ + */ + +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) +#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ + ((POLARITY) == TIM_BreakPolarity_High)) +/** + * @} + */ + +/** @defgroup TIM_AOE_Bit_Set_Reset + * @{ + */ + +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ + ((STATE) == TIM_AutomaticOutput_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Lock_level + * @{ + */ + +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) +#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ + ((LEVEL) == TIM_LOCKLevel_1) || \ + ((LEVEL) == TIM_LOCKLevel_2) || \ + ((LEVEL) == TIM_LOCKLevel_3)) +/** + * @} + */ + +/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state + * @{ + */ + +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) +#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ + ((STATE) == TIM_OSSIState_Disable)) +/** + * @} + */ + +/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state + * @{ + */ + +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) +#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ + ((STATE) == TIM_OSSRState_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State + * @{ + */ + +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) +#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ + ((STATE) == TIM_OCIdleState_Reset)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State + * @{ + */ + +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) +#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ + ((STATE) == TIM_OCNIdleState_Reset)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity + * @{ + */ + +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) +#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ + ((POLARITY) == TIM_ICPolarity_Falling)|| \ + ((POLARITY) == TIM_ICPolarity_BothEdge)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection + * @{ + */ + +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ +#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ + ((SELECTION) == TIM_ICSelection_IndirectTI) || \ + ((SELECTION) == TIM_ICSelection_TRC)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler + * @{ + */ + +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ +#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ + ((PRESCALER) == TIM_ICPSC_DIV2) || \ + ((PRESCALER) == TIM_ICPSC_DIV4) || \ + ((PRESCALER) == TIM_ICPSC_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_interrupt_sources + * @{ + */ + +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) +#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) + +#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ + ((IT) == TIM_IT_CC1) || \ + ((IT) == TIM_IT_CC2) || \ + ((IT) == TIM_IT_CC3) || \ + ((IT) == TIM_IT_CC4) || \ + ((IT) == TIM_IT_COM) || \ + ((IT) == TIM_IT_Trigger) || \ + ((IT) == TIM_IT_Break)) +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address + * @{ + */ + +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) +#define TIM_DMABase_OR ((uint16_t)0x0013) +#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ + ((BASE) == TIM_DMABase_CR2) || \ + ((BASE) == TIM_DMABase_SMCR) || \ + ((BASE) == TIM_DMABase_DIER) || \ + ((BASE) == TIM_DMABase_SR) || \ + ((BASE) == TIM_DMABase_EGR) || \ + ((BASE) == TIM_DMABase_CCMR1) || \ + ((BASE) == TIM_DMABase_CCMR2) || \ + ((BASE) == TIM_DMABase_CCER) || \ + ((BASE) == TIM_DMABase_CNT) || \ + ((BASE) == TIM_DMABase_PSC) || \ + ((BASE) == TIM_DMABase_ARR) || \ + ((BASE) == TIM_DMABase_RCR) || \ + ((BASE) == TIM_DMABase_CCR1) || \ + ((BASE) == TIM_DMABase_CCR2) || \ + ((BASE) == TIM_DMABase_CCR3) || \ + ((BASE) == TIM_DMABase_CCR4) || \ + ((BASE) == TIM_DMABase_BDTR) || \ + ((BASE) == TIM_DMABase_DCR) || \ + ((BASE) == TIM_DMABase_OR)) +/** + * @} + */ + + +/** @defgroup TIM_DMA_Burst_Length + * @{ + */ + +#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) +#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ + ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_18Transfers)) +/** + * @} + */ + +/** @defgroup TIM_DMA_sources + * @{ + */ + +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) +#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) + +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Prescaler + * @{ + */ + +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) +#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_Internal_Trigger_Selection + * @{ + */ + +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) +#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3) || \ + ((SELECTION) == TIM_TS_TI1F_ED) || \ + ((SELECTION) == TIM_TS_TI1FP1) || \ + ((SELECTION) == TIM_TS_TI2FP2) || \ + ((SELECTION) == TIM_TS_ETRF)) +#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3)) +/** + * @} + */ + +/** @defgroup TIM_TIx_External_Clock_Source + * @{ + */ + +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) + +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Polarity + * @{ + */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) +#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ + ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) +/** + * @} + */ + +/** @defgroup TIM_Prescaler_Reload_Mode + * @{ + */ + +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) +#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ + ((RELOAD) == TIM_PSCReloadMode_Immediate)) +/** + * @} + */ + +/** @defgroup TIM_Forced_Action + * @{ + */ + +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) +#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ + ((ACTION) == TIM_ForcedAction_InActive)) +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode + * @{ + */ + +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) +#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ + ((MODE) == TIM_EncoderMode_TI2) || \ + ((MODE) == TIM_EncoderMode_TI12)) +/** + * @} + */ + + +/** @defgroup TIM_Event_Source + * @{ + */ + +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) +#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) + +/** + * @} + */ + +/** @defgroup TIM_Update_Source + * @{ + */ + +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow + or the setting of UG bit, or an update generation + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ +#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ + ((SOURCE) == TIM_UpdateSource_Regular)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Preload_State + * @{ + */ + +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) +#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ + ((STATE) == TIM_OCPreload_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Fast_State + * @{ + */ + +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) +#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ + ((STATE) == TIM_OCFast_Disable)) + +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Clear_State + * @{ + */ + +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) +#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ + ((STATE) == TIM_OCClear_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Trigger_Output_Source + * @{ + */ + +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) +#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ + ((SOURCE) == TIM_TRGOSource_Enable) || \ + ((SOURCE) == TIM_TRGOSource_Update) || \ + ((SOURCE) == TIM_TRGOSource_OC1) || \ + ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC4Ref)) +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode + * @{ + */ + +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) +#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ + ((MODE) == TIM_SlaveMode_Gated) || \ + ((MODE) == TIM_SlaveMode_Trigger) || \ + ((MODE) == TIM_SlaveMode_External1)) +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode + * @{ + */ + +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) +#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ + ((STATE) == TIM_MasterSlaveMode_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Flags + * @{ + */ + +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) +#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ + ((FLAG) == TIM_FLAG_CC1) || \ + ((FLAG) == TIM_FLAG_CC2) || \ + ((FLAG) == TIM_FLAG_CC3) || \ + ((FLAG) == TIM_FLAG_CC4) || \ + ((FLAG) == TIM_FLAG_COM) || \ + ((FLAG) == TIM_FLAG_Trigger) || \ + ((FLAG) == TIM_FLAG_Break) || \ + ((FLAG) == TIM_FLAG_CC1OF) || \ + ((FLAG) == TIM_FLAG_CC2OF) || \ + ((FLAG) == TIM_FLAG_CC3OF) || \ + ((FLAG) == TIM_FLAG_CC4OF)) + + +#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) +/** + * @} + */ + + +/** @defgroup TIM_Input_Capture_Filer_Value + * @{ + */ + +#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Filter + * @{ + */ + +#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup TIM_OCReferenceClear + * @{ + */ +#define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008) +#define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000) +#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \ + ((SOURCE) == TIM_OCReferenceClear_OCREFCLR)) + +/** + * @} + */ +/** @defgroup TIM_Remap + * @{ + */ +#define TIM14_GPIO ((uint16_t)0x0000) +#define TIM14_RTC_CLK ((uint16_t)0x0001) +#define TIM14_HSEDiv32 ((uint16_t)0x0002) +#define TIM14_MCO ((uint16_t)0x0003) + +#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM14_GPIO)|| \ + ((TIM_REMAP) == TIM14_RTC_CLK) || \ + ((TIM_REMAP) == TIM14_HSEDiv32) || \ + ((TIM_REMAP) == TIM14_MCO)) +/** + * @} + */ + +/** @defgroup TIM_Legacy + * @{ + */ + +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* TimeBase management ********************************************************/ +void TIM_DeInit(TIM_TypeDef* TIMx); +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); +void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter); +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload); +uint32_t TIM_GetCounter(TIM_TypeDef* TIMx); +uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); + +/* Advanced-control timers (TIM1) specific features*******************/ +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); + +/* Output Compare management **************************************************/ +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1); +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2); +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3); +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4); +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear); +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); + +/* Input Capture management ***************************************************/ +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx); +uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx); +uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx); +uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx); +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); + +/* Interrupts, DMA and flags management ***************************************/ +void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); +void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); + +/* Clocks management **********************************************************/ +void TIM_InternalClockConfig(TIM_TypeDef* TIMx); +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter); +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); + + +/* Synchronization management *************************************************/ +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); + +/* Specific interface management **********************************************/ +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); + +/* Specific remapping management **********************************************/ +void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap); + + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F0XX_TIM_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_usart.h b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_usart.h new file mode 100644 index 0000000..8d27ac4 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_usart.h @@ -0,0 +1,593 @@ +/** + ****************************************************************************** + * @file stm32f0xx_usart.h + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file contains all the functions prototypes for the USART + * firmware library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_USART_H +#define __STM32F0XX_USART_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup USART + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + + + +/** + * @brief USART Init Structure definition + */ + +typedef struct +{ + uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) + - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */ + + uint32_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_Word_Length */ + + uint32_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint32_t USART_Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint32_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode */ + + uint32_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref USART_Hardware_Flow_Control*/ +} USART_InitTypeDef; + +/** + * @brief USART Clock Init Structure definition + */ + +typedef struct +{ + uint32_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_Clock */ + + uint32_t USART_CPOL; /*!< Specifies the steady state of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity */ + + uint32_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase */ + + uint32_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit */ +} USART_ClockInitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup USART_Exported_Constants + * @{ + */ + +#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ + ((PERIPH) == USART2)) + +#define IS_USART_1_PERIPH(PERIPH) (((PERIPH) == USART1)) + +/** @defgroup USART_Word_Length + * @{ + */ + +#define USART_WordLength_8b ((uint32_t)0x00000000) +#define USART_WordLength_9b USART_CR1_M +#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ + ((LENGTH) == USART_WordLength_9b)) +/** + * @} + */ + +/** @defgroup USART_Stop_Bits + * @{ + */ + +#define USART_StopBits_1 ((uint32_t)0x00000000) +#define USART_StopBits_2 ((uint32_t)USART_CR2_STOP_1) +#define USART_StopBits_1_5 ((uint32_t)USART_CR2_STOP_0 | USART_CR2_STOP_1) +#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ + ((STOPBITS) == USART_StopBits_2) || \ + ((STOPBITS) == USART_StopBits_1_5)) +/** + * @} + */ + +/** @defgroup USART_Parity + * @{ + */ + +#define USART_Parity_No ((uint32_t)0x00000000) +#define USART_Parity_Even ((uint32_t)USART_CR1_PCE) +#define USART_Parity_Odd ((uint32_t)USART_CR1_PCE | USART_CR1_PS) +#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ + ((PARITY) == USART_Parity_Even) || \ + ((PARITY) == USART_Parity_Odd)) +/** + * @} + */ + +/** @defgroup USART_Mode + * @{ + */ + +#define USART_Mode_Rx USART_CR1_RE +#define USART_Mode_Tx USART_CR1_TE +#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFFFFFF3) == 0x00) && \ + ((MODE) != (uint32_t)0x00)) +/** + * @} + */ + +/** @defgroup USART_Hardware_Flow_Control + * @{ + */ + +#define USART_HardwareFlowControl_None ((uint32_t)0x00000000) +#define USART_HardwareFlowControl_RTS ((uint32_t)USART_CR3_RTSE) +#define USART_HardwareFlowControl_CTS ((uint32_t)USART_CR3_CTSE) +#define USART_HardwareFlowControl_RTS_CTS ((uint32_t)USART_CR3_RTSE | USART_CR3_CTSE) +#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ + (((CONTROL) == USART_HardwareFlowControl_None) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS) || \ + ((CONTROL) == USART_HardwareFlowControl_CTS) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) +/** + * @} + */ + +/** @defgroup USART_Clock + * @{ + */ + +#define USART_Clock_Disable ((uint32_t)0x00000000) +#define USART_Clock_Enable USART_CR2_CLKEN +#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ + ((CLOCK) == USART_Clock_Enable)) +/** + * @} + */ + +/** @defgroup USART_Clock_Polarity + * @{ + */ + +#define USART_CPOL_Low ((uint32_t)0x00000000) +#define USART_CPOL_High USART_CR2_CPOL +#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) + +/** + * @} + */ + +/** @defgroup USART_Clock_Phase + * @{ + */ + +#define USART_CPHA_1Edge ((uint32_t)0x00000000) +#define USART_CPHA_2Edge USART_CR2_CPHA +#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) + +/** + * @} + */ + +/** @defgroup USART_Last_Bit + * @{ + */ + +#define USART_LastBit_Disable ((uint32_t)0x00000000) +#define USART_LastBit_Enable USART_CR2_LBCL +#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ + ((LASTBIT) == USART_LastBit_Enable)) +/** + * @} + */ + +/** @defgroup USART_DMA_Requests + * @{ + */ + +#define USART_DMAReq_Tx USART_CR3_DMAT +#define USART_DMAReq_Rx USART_CR3_DMAR +#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint32_t)0xFFFFFF3F) == 0x00) && \ + ((DMAREQ) != (uint32_t)0x00)) + +/** + * @} + */ + +/** @defgroup USART_DMA_Recception_Error + * @{ + */ + +#define USART_DMAOnError_Enable ((uint32_t)0x00000000) +#define USART_DMAOnError_Disable USART_CR3_DDRE +#define IS_USART_DMAONERROR(DMAERROR) (((DMAERROR) == USART_DMAOnError_Disable)|| \ + ((DMAERROR) == USART_DMAOnError_Enable)) +/** + * @} + */ + +/** @defgroup USART_MuteMode_WakeUp_methods + * @{ + */ + +#define USART_WakeUp_IdleLine ((uint32_t)0x00000000) +#define USART_WakeUp_AddressMark USART_CR1_WAKE +#define IS_USART_MUTEMODE_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ + ((WAKEUP) == USART_WakeUp_AddressMark)) +/** + * @} + */ + +/** @defgroup USART_Address_Detection + * @{ + */ + +#define USART_AddressLength_4b ((uint32_t)0x00000000) +#define USART_AddressLength_7b USART_CR2_ADDM7 +#define IS_USART_ADDRESS_DETECTION(ADDRESS) (((ADDRESS) == USART_AddressLength_4b) || \ + ((ADDRESS) == USART_AddressLength_7b)) +/** + * @} + */ + +/** @defgroup USART_StopMode_WakeUp_methods + * @{ + */ + +#define USART_WakeUpSource_AddressMatch ((uint32_t)0x00000000) +#define USART_WakeUpSource_StartBit ((uint32_t)USART_CR3_WUS_1) +#define USART_WakeUpSource_RXNE ((uint32_t)USART_CR3_WUS_0 | USART_CR3_WUS_1) +#define IS_USART_STOPMODE_WAKEUPSOURCE(SOURCE) (((SOURCE) == USART_WakeUpSource_AddressMatch) || \ + ((SOURCE) == USART_WakeUpSource_StartBit) || \ + ((SOURCE) == USART_WakeUpSource_RXNE)) +/** + * @} + */ + +/** @defgroup USART_LIN_Break_Detection_Length + * @{ + */ + +#define USART_LINBreakDetectLength_10b ((uint32_t)0x00000000) +#define USART_LINBreakDetectLength_11b USART_CR2_LBDL +#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ + (((LENGTH) == USART_LINBreakDetectLength_10b) || \ + ((LENGTH) == USART_LINBreakDetectLength_11b)) +/** + * @} + */ + +/** @defgroup USART_IrDA_Low_Power + * @{ + */ + +#define USART_IrDAMode_LowPower USART_CR3_IRLP +#define USART_IrDAMode_Normal ((uint32_t)0x00000000) +#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ + ((MODE) == USART_IrDAMode_Normal)) +/** + * @} + */ + +/** @defgroup USART_DE_Polarity + * @{ + */ + +#define USART_DEPolarity_High ((uint32_t)0x00000000) +#define USART_DEPolarity_Low USART_CR3_DEP +#define IS_USART_DE_POLARITY(POLARITY) (((POLARITY) == USART_DEPolarity_Low) || \ + ((POLARITY) == USART_DEPolarity_High)) +/** + * @} + */ + +/** @defgroup USART_Inversion_Pins + * @{ + */ + +#define USART_InvPin_Tx USART_CR2_TXINV +#define USART_InvPin_Rx USART_CR2_RXINV +#define IS_USART_INVERSTION_PIN(PIN) ((((PIN) & (uint32_t)0xFFFCFFFF) == 0x00) && \ + ((PIN) != (uint32_t)0x00)) + +/** + * @} + */ + +/** @defgroup USART_AutoBaudRate_Mode + * @{ + */ + +#define USART_AutoBaudRate_StartBit ((uint32_t)0x00000000) +#define USART_AutoBaudRate_FallingEdge USART_CR2_ABRMODE_0 +#define IS_USART_AUTOBAUDRATE_MODE(MODE) (((MODE) == USART_AutoBaudRate_StartBit) || \ + ((MODE) == USART_AutoBaudRate_FallingEdge)) +/** + * @} + */ + +/** @defgroup USART_OVR_DETECTION + * @{ + */ + +#define USART_OVRDetection_Enable ((uint32_t)0x00000000) +#define USART_OVRDetection_Disable USART_CR3_OVRDIS +#define IS_USART_OVRDETECTION(OVR) (((OVR) == USART_OVRDetection_Enable)|| \ + ((OVR) == USART_OVRDetection_Disable)) +/** + * @} + */ +/** @defgroup USART_Request + * @{ + */ + +#define USART_Request_ABRRQ USART_RQR_ABRRQ +#define USART_Request_SBKRQ USART_RQR_SBKRQ +#define USART_Request_MMRQ USART_RQR_MMRQ +#define USART_Request_RXFRQ USART_RQR_RXFRQ +#define USART_Request_TXFRQ USART_RQR_TXFRQ + +#define IS_USART_REQUEST(REQUEST) (((REQUEST) == USART_Request_TXFRQ) || \ + ((REQUEST) == USART_Request_RXFRQ) || \ + ((REQUEST) == USART_Request_MMRQ) || \ + ((REQUEST) == USART_Request_SBKRQ) || \ + ((REQUEST) == USART_Request_ABRRQ)) +/** + * @} + */ + +/** @defgroup USART_Flags + * @{ + */ +#define USART_FLAG_REACK USART_ISR_REACK +#define USART_FLAG_TEACK USART_ISR_TEACK +#define USART_FLAG_WU USART_ISR_WUF +#define USART_FLAG_RWU USART_ISR_RWU +#define USART_FLAG_SBK USART_ISR_SBKF +#define USART_FLAG_CM USART_ISR_CMF +#define USART_FLAG_BUSY USART_ISR_BUSY +#define USART_FLAG_ABRF USART_ISR_ABRF +#define USART_FLAG_ABRE USART_ISR_ABRE +#define USART_FLAG_EOB USART_ISR_EOBF +#define USART_FLAG_RTO USART_ISR_RTOF +#define USART_FLAG_nCTSS USART_ISR_CTS +#define USART_FLAG_CTS USART_ISR_CTSIF +#define USART_FLAG_LBD USART_ISR_LBD +#define USART_FLAG_TXE USART_ISR_TXE +#define USART_FLAG_TC USART_ISR_TC +#define USART_FLAG_RXNE USART_ISR_RXNE +#define USART_FLAG_IDLE USART_ISR_IDLE +#define USART_FLAG_ORE USART_ISR_ORE +#define USART_FLAG_NE USART_ISR_NE +#define USART_FLAG_FE USART_ISR_FE +#define USART_FLAG_PE USART_ISR_PE +#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ + ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ + ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ + ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ + ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \ + ((FLAG) == USART_FLAG_nCTSS) || ((FLAG) == USART_FLAG_RTO) || \ + ((FLAG) == USART_FLAG_EOB) || ((FLAG) == USART_FLAG_ABRE) || \ + ((FLAG) == USART_FLAG_ABRF) || ((FLAG) == USART_FLAG_BUSY) || \ + ((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_SBK) || \ + ((FLAG) == USART_FLAG_RWU) || ((FLAG) == USART_FLAG_WU) || \ + ((FLAG) == USART_FLAG_TEACK)|| ((FLAG) == USART_FLAG_REACK)) + +#define IS_USART_CLEAR_FLAG(FLAG) (((FLAG) == USART_FLAG_WU) || ((FLAG) == USART_FLAG_TC) || \ + ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_ORE) || \ + ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \ + ((FLAG) == USART_FLAG_LBD) || ((FLAG) == USART_FLAG_CTS) || \ + ((FLAG) == USART_FLAG_RTO) || ((FLAG) == USART_FLAG_EOB) || \ + ((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_PE)) +/** + * @} + */ + +/** @defgroup USART_Interrupt_definition + * @brief USART Interrupt definition + * USART_IT possible values + * Elements values convention: 0xZZZZYYXX + * XX: Position of the corresponding Interrupt + * YY: Register index + * ZZZZ: Flag position + * @{ + */ + +#define USART_IT_WU ((uint32_t)0x00140316) +#define USART_IT_CM ((uint32_t)0x0011010E) +#define USART_IT_EOB ((uint32_t)0x000C011B) +#define USART_IT_RTO ((uint32_t)0x000B011A) +#define USART_IT_PE ((uint32_t)0x00000108) +#define USART_IT_TXE ((uint32_t)0x00070107) +#define USART_IT_TC ((uint32_t)0x00060106) +#define USART_IT_RXNE ((uint32_t)0x00050105) +#define USART_IT_IDLE ((uint32_t)0x00040104) +#define USART_IT_LBD ((uint32_t)0x00080206) +#define USART_IT_CTS ((uint32_t)0x0009030A) +#define USART_IT_ERR ((uint32_t)0x00000300) +#define USART_IT_ORE ((uint32_t)0x00030300) +#define USART_IT_NE ((uint32_t)0x00020300) +#define USART_IT_FE ((uint32_t)0x00010300) + +#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ + ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ + ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR) || \ + ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \ + ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU)) + +#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ + ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ + ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ + ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE) || \ + ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \ + ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU)) + +#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_PE) || \ + ((IT) == USART_IT_FE) || ((IT) == USART_IT_NE) || \ + ((IT) == USART_IT_ORE) || ((IT) == USART_IT_IDLE) || \ + ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS) || \ + ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \ + ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU)) +/** + * @} + */ + +/** @defgroup USART_Global_definition + * @{ + */ + +#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x005B8D81)) +#define IS_USART_DE_ASSERTION_DEASSERTION_TIME(TIME) ((TIME) <= 0x1F) +#define IS_USART_AUTO_RETRY_COUNTER(COUNTER) ((COUNTER) <= 0x7) +#define IS_USART_TIMEOUT(TIMEOUT) ((TIMEOUT) <= 0x00FFFFFF) +#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Initialization and Configuration functions *********************************/ +void USART_DeInit(USART_TypeDef* USARTx); +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); +void USART_StructInit(USART_InitTypeDef* USART_InitStruct); +void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState); +void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); +void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState); +void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut); + +/* STOP Mode functions ********************************************************/ +void USART_STOPModeCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUpSource); + +/* AutoBaudRate functions *****************************************************/ +void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate); +void USART_AutoBaudRateNewRequest(USART_TypeDef* USARTx); + +/* Data transfers functions ***************************************************/ +void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); +uint16_t USART_ReceiveData(USART_TypeDef* USARTx); + +/* Multi-Processor Communication functions ************************************/ +void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); +void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp); +void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength); +/* LIN mode functions *********************************************************/ +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint32_t USART_LINBreakDetectLength); +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); + +/* Half-duplex mode function **************************************************/ +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); + +/* Smartcard mode functions ***************************************************/ +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); +void USART_SetAutoRetryCount(USART_TypeDef* USARTx, uint8_t USART_AutoCount); +void USART_SetBlockLength(USART_TypeDef* USARTx, uint8_t USART_BlockLength); + +/* IrDA mode functions ********************************************************/ +void USART_IrDAConfig(USART_TypeDef* USARTx, uint32_t USART_IrDAMode); +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); + +/* RS485 mode functions *******************************************************/ +void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity); +void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime); +void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime); + +/* DMA transfers management functions *****************************************/ +void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState); +void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError); + +/* Interrupts and flags management functions **********************************/ +void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState); +void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState); +void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection); +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG); +void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG); +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT); +void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0XX_USART_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_wwdg.h b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_wwdg.h new file mode 100644 index 0000000..3dba97b --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/inc/stm32f0xx_wwdg.h @@ -0,0 +1,109 @@ +/** + ****************************************************************************** + * @file stm32f0xx_wwdg.h + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file contains all the functions prototypes for the WWDG + * firmware library. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_WWDG_H +#define __STM32F0XX_WWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup WWDG + * @{ + */ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup WWDG_Exported_Constants + * @{ + */ + +/** @defgroup WWDG_Prescaler + * @{ + */ + +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) +#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ + ((PRESCALER) == WWDG_Prescaler_2) || \ + ((PRESCALER) == WWDG_Prescaler_4) || \ + ((PRESCALER) == WWDG_Prescaler_8)) +#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) +#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +/* Function used to set the WWDG configuration to the default reset state ****/ +void WWDG_DeInit(void); + +/* Prescaler, Refresh window and Counter configuration functions **************/ +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); +void WWDG_SetWindowValue(uint8_t WindowValue); +void WWDG_EnableIT(void); +void WWDG_SetCounter(uint8_t Counter); + +/* WWDG activation functions **************************************************/ +void WWDG_Enable(uint8_t Counter); + +/* Interrupts and flags management functions **********************************/ +FlagStatus WWDG_GetFlagStatus(void); +void WWDG_ClearFlag(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0XX_WWDG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_adc.c b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_adc.c new file mode 100644 index 0000000..aab6069 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_adc.c @@ -0,0 +1,1218 @@ +/** + ****************************************************************************** + * @file stm32f0xx_adc.c + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Analog to Digital Convertor (ADC) peripheral: + * + Initialization and Configuration + * + Power saving + * + Analog Watchdog configuration + * + Temperature Sensor, Vrefint (Internal Reference Voltage) and + * Vbat (Voltage battery) management + * + ADC Channels Configuration + * + ADC Channels DMA Configuration + * + Interrupts and flags management + * + * @verbatim +================================================================================ + ##### How to use this driver ##### +================================================================================ + [..] + (#) Enable the ADC interface clock using + RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE); + (#) ADC pins configuration + (++) Enable the clock for the ADC GPIOs using the following function: + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOx, ENABLE); + (++) Configure these ADC pins in analog mode using GPIO_Init(); + (#) Configure the ADC conversion resolution, data alignment, external + trigger and edge, scan direction and Enable/Disable the continuous mode + using the ADC_Init() function. + (#) Activate the ADC peripheral using ADC_Cmd() function. + + *** ADC channels group configuration *** + ============================================ + [..] + (+) To configure the ADC channels features, use ADC_Init() and + ADC_ChannelConfig() functions. + (+) To activate the continuous mode, use the ADC_ContinuousModeCmd() + function. + (+) To activate the Discontinuous mode, use the ADC_DiscModeCmd() functions. + (+) To activate the overrun mode, use the ADC_OverrunModeCmd() functions. + (+) To activate the calibration mode, use the ADC_GetCalibrationFactor() functions. + (+) To read the ADC converted values, use the ADC_GetConversionValue() + function. + + *** DMA for ADC channels features configuration *** + ============================================================= + [..] + (+) To enable the DMA mode for ADC channels group, use the ADC_DMACmd() function. + (+) To configure the DMA transfer request, use ADC_DMARequestModeConfig() function. + + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_adc.h" +#include "stm32f0xx_rcc.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup ADC + * @brief ADC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ADC CFGR mask */ +#define CFGR1_CLEAR_MASK ((uint32_t)0xFFFFD203) + +/* Calibration time out */ +#define CALIBRATION_TIMEOUT ((uint32_t)0x0000F000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup ADC_Private_Functions + * @{ + */ + +/** @defgroup ADC_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the ADC Prescaler + (+) ADC Conversion Resolution (12bit..6bit) + (+) ADC Continuous Conversion Mode (Continuous or Single conversion) + (+) External trigger Edge and source + (+) Converted data alignment (left or right) + (+) The direction in which the channels will be scanned in the sequence + (+) Enable or disable the ADC peripheral + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes ADC1 peripheral registers to their default reset values. + * @param ADCx: where x can be 1 to select the ADC peripheral. + * @retval None + */ +void ADC_DeInit(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + if(ADCx == ADC1) + { + /* Enable ADC1 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); + + /* Release ADC1 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); + } +} + +/** + * @brief Initializes the ADCx peripheral according to the specified parameters + * in the ADC_InitStruct. + * @note This function is used to configure the global features of the ADC ( + * Resolution, Data Alignment, continuous mode activation, External + * trigger source and edge, Sequence Scan Direction). + * @param ADCx: where x can be 1 to select the ADC peripheral. + * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains + * the configuration information for the specified ADC peripheral. + * @retval None + */ +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); + assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge)); + assert_param(IS_ADC_EXTERNAL_TRIG_CONV(ADC_InitStruct->ADC_ExternalTrigConv)); + assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); + assert_param(IS_ADC_SCAN_DIRECTION(ADC_InitStruct->ADC_ScanDirection)); + + /* Get the ADCx CFGR value */ + tmpreg = ADCx->CFGR1; + + /* Clear SCANDIR, RES[1:0], ALIGN, EXTSEL[2:0], EXTEN[1:0] and CONT bits */ + tmpreg &= CFGR1_CLEAR_MASK; + + /*---------------------------- ADCx CFGR Configuration ---------------------*/ + + /* Set RES[1:0] bits according to ADC_Resolution value */ + /* Set CONT bit according to ADC_ContinuousConvMode value */ + /* Set EXTEN[1:0] bits according to ADC_ExternalTrigConvEdge value */ + /* Set EXTSEL[2:0] bits according to ADC_ExternalTrigConv value */ + /* Set ALIGN bit according to ADC_DataAlign value */ + /* Set SCANDIR bit according to ADC_ScanDirection value */ + + tmpreg |= (uint32_t)(ADC_InitStruct->ADC_Resolution | ((uint32_t)(ADC_InitStruct->ADC_ContinuousConvMode) << 13) | + ADC_InitStruct->ADC_ExternalTrigConvEdge | ADC_InitStruct->ADC_ExternalTrigConv | + ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ScanDirection); + + /* Write to ADCx CFGR */ + ADCx->CFGR1 = tmpreg; +} + +/** + * @brief Fills each ADC_InitStruct member with its default value. + * @note This function is used to initialize the global features of the ADC ( + * Resolution, Data Alignment, continuous mode activation, External + * trigger source and edge, Sequence Scan Direction). + * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) +{ + /* Reset ADC init structure parameters values */ + /* Initialize the ADC_Resolution member */ + ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b; + + /* Initialize the ADC_ContinuousConvMode member */ + ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; + + /* Initialize the ADC_ExternalTrigConvEdge member */ + ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None; + + /* Initialize the ADC_ExternalTrigConv member */ + ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_TRGO; + + /* Initialize the ADC_DataAlign member */ + ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; + + /* Initialize the ADC_ScanDirection member */ + ADC_InitStruct->ADC_ScanDirection = ADC_ScanDirection_Upward; +} + +/** + * @brief Enables or disables the specified ADC peripheral. + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @param NewState: new state of the ADCx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the ADEN bit to Enable the ADC peripheral */ + ADCx->CR |= (uint32_t)ADC_CR_ADEN; + } + else + { + /* Set the ADDIS to Disable the ADC peripheral */ + ADCx->CR |= (uint32_t)ADC_CR_ADDIS; + } +} + +/** + * @brief Enables or disables the jitter when the ADC is clocked by PCLK div2 + * or div4 + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @param ADC_JitterOff: This parameter can be : + * @arg ADC_JitterOff_PCLKDiv2: Remove jitter when ADC is clocked by PLCK divided by 2 + * @arg ADC_JitterOff_PCLKDiv4: Remove jitter when ADC is clocked by PLCK divided by 4 + * @param NewState: new state of the ADCx jitter. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_JitterCmd(ADC_TypeDef* ADCx, uint32_t ADC_JitterOff, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_JITTEROFF(ADC_JitterOff)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Disable Jitter */ + ADCx->CFGR2 |= (uint32_t)ADC_JitterOff; + } + else + { + /* Enable Jitter */ + ADCx->CFGR2 &= (uint32_t)(~ADC_JitterOff); + } +} + +/** + * @} + */ + +/** @defgroup ADC_Group2 Power saving functions + * @brief Power saving functions + * +@verbatim + =============================================================================== + ##### Power saving functions ##### + =============================================================================== + [..] This section provides functions allowing to reduce power consumption. + [..] The two function must be combined to get the maximal benefits: + When the ADC frequency is higher than the CPU one, it is recommended to + (#) Enable the Auto Delayed Conversion mode : + ==> using ADC_WaitModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); + (#) Enable the power off in Delay phases : + ==> using ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState); + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the ADC Power Off. + * @note ADC power-on and power-off can be managed by hardware to cut the + * consumption when the ADC is not converting. + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @note The ADC can be powered down: + * - During the Auto delay phase + * => The ADC is powered on again at the end of the delay (until the + * previous data is read from the ADC data register). + * - During the ADC is waiting for a trigger event + * => The ADC is powered up at the next trigger event (when the + * conversion is started). + * @param NewState: new state of the ADCx power Off. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the ADC Automatic Power-Off */ + ADCx->CFGR1 |= ADC_CFGR1_AUTOFF; + } + else + { + /* Disable the ADC Automatic Power-Off */ + ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_AUTOFF; + } +} + +/** + * @brief Enables or disables the Wait conversion mode. + * @note When the CPU clock is not fast enough to manage the data rate, a + * Hardware delay can be introduced between ADC conversions to reduce + * this data rate. + * @note The Hardware delay is inserted after : + * - after each conversions and until the previous data is read from the + * ADC data register + * @note This is a way to automatically adapt the speed of the ADC to the speed + * of the system which will read the data. + * @note Any hardware triggers wich occur while a conversion is on going or + * while the automatic Delay is applied are ignored + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @param NewState: new state of the ADCx Auto-Delay. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_WaitModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the ADC Automatic Delayed conversion */ + ADCx->CFGR1 |= ADC_CFGR1_WAIT; + } + else + { + /* Disable the ADC Automatic Delayed conversion */ + ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_WAIT; + } +} + +/** + * @} + */ + +/** @defgroup ADC_Group3 Analog Watchdog configuration functions + * @brief Analog Watchdog configuration functions + * +@verbatim + =============================================================================== + ##### Analog Watchdog configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to configure the Analog Watchdog + (AWD) feature in the ADC. + [..] A typical configuration Analog Watchdog is done following these steps : + (#) the ADC guarded channel(s) is (are) selected using the + ADC_AnalogWatchdogSingleChannelConfig() function. + (#) The Analog watchdog lower and higher threshold are configured using the + ADC_AnalogWatchdogThresholdsConfig() function. + (#) The Analog watchdog is enabled and configured to enable the check, on one + or more channels, using the ADC_AnalogWatchdogCmd() function. + (#) Enable the analog watchdog on the selected channel using + ADC_AnalogWatchdogSingleChannelCmd() function + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the analog watchdog + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @param NewState: new state of the ADCx Analog Watchdog. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the ADC Analog Watchdog */ + ADCx->CFGR1 |= ADC_CFGR1_AWDEN; + } + else + { + /* Disable the ADC Analog Watchdog */ + ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_AWDEN; + } +} + +/** + * @brief Configures the high and low thresholds of the analog watchdog. + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @param HighThreshold: the ADC analog watchdog High threshold value. + * This parameter must be a 12bit value. + * @param LowThreshold: the ADC analog watchdog Low threshold value. + * This parameter must be a 12bit value. + * @retval None + */ +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_THRESHOLD(HighThreshold)); + assert_param(IS_ADC_THRESHOLD(LowThreshold)); + + /* Set the ADCx high and low threshold */ + ADCx->TR = LowThreshold | ((uint32_t)HighThreshold << 16); + +} + +/** + * @brief Configures the analog watchdog guarded single channel + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @param ADC_AnalogWatchdog_Channel: the ADC channel to configure for the analog watchdog. + * This parameter can be one of the following values: + * @arg ADC_AnalogWatchdog_Channel_0: ADC Channel0 selected + * @arg ADC_AnalogWatchdog_Channel_1: ADC Channel1 selected + * @arg ADC_AnalogWatchdog_Channel_2: ADC Channel2 selected + * @arg ADC_AnalogWatchdog_Channel_3: ADC Channel3 selected + * @arg ADC_AnalogWatchdog_Channel_4: ADC Channel4 selected + * @arg ADC_AnalogWatchdog_Channel_5: ADC Channel5 selected + * @arg ADC_AnalogWatchdog_Channel_6: ADC Channel6 selected + * @arg ADC_AnalogWatchdog_Channel_7: ADC Channel7 selected + * @arg ADC_AnalogWatchdog_Channel_8: ADC Channel8 selected + * @arg ADC_AnalogWatchdog_Channel_9: ADC Channel9 selected + * @arg ADC_AnalogWatchdog_Channel_10: ADC Channel10 selected + * @arg ADC_AnalogWatchdog_Channel_11: ADC Channel11 selected + * @arg ADC_AnalogWatchdog_Channel_12: ADC Channel12 selected + * @arg ADC_AnalogWatchdog_Channel_13: ADC Channel13 selected + * @arg ADC_AnalogWatchdog_Channel_14: ADC Channel14 selected + * @arg ADC_AnalogWatchdog_Channel_15: ADC Channel15 selected + * @arg ADC_AnalogWatchdog_Channel_16: ADC Channel16 selected + * @arg ADC_AnalogWatchdog_Channel_17: ADC Channel17 selected + * @arg ADC_AnalogWatchdog_Channel_18: ADC Channel18 selected + * @note The channel selected on the AWDCH must be also set into the CHSELR + * register + * @retval None + */ +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog_Channel) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_ANALOG_WATCHDOG_CHANNEL(ADC_AnalogWatchdog_Channel)); + + /* Get the old register value */ + tmpreg = ADCx->CFGR1; + + /* Clear the Analog watchdog channel select bits */ + tmpreg &= ~ADC_CFGR1_AWDCH; + + /* Set the Analog watchdog channel */ + tmpreg |= ADC_AnalogWatchdog_Channel; + + /* Store the new register value */ + ADCx->CFGR1 = tmpreg; +} + +/** + * @brief Enables or disables the ADC Analog Watchdog Single Channel. + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @param NewState: new state of the ADCx ADC Analog Watchdog Single Channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_AnalogWatchdogSingleChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the ADC Analog Watchdog Single Channel */ + ADCx->CFGR1 |= ADC_CFGR1_AWDSGL; + } + else + { + /* Disable the ADC Analog Watchdog Single Channel */ + ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_AWDSGL; + } +} + +/** + * @} + */ + +/** @defgroup ADC_Group4 Temperature Sensor, Vrefint and Vbat management functions + * @brief Temperature Sensor, Vrefint and Vbat management functions + * +@verbatim + =============================================================================== + ##### Temperature Sensor, Vrefint and Vbat management function ##### + =============================================================================== + [..] This section provides a function allowing to enable/disable the internal + connections between the ADC and the Temperature Sensor, the Vrefint and + Vbat source. + + [..] A typical configuration to get the Temperature sensor, Vrefint and Vbat channels + voltages is done following these steps : + (#) Enable the internal connection of Temperature sensor, Vrefint or Vbat sources + with the ADC channels using ADC_TempSensorCmd(), ADC_VrefintCmd() or ADC_VbatCmd() + functions. + (#) select the ADC_Channel_16(Temperature sensor), ADC_Channel_17(Vrefint) + or ADC_Channel_18(Voltage battery) using ADC_ChannelConfig() function + (#) Get the voltage values, using ADC_GetConversionValue() function + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the temperature sensor channel. + * @param NewState: new state of the temperature sensor input channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_TempSensorCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the temperature sensor channel*/ + ADC->CCR |= (uint32_t)ADC_CCR_TSEN; + } + else + { + /* Disable the temperature sensor channel*/ + ADC->CCR &= (uint32_t)(~ADC_CCR_TSEN); + } +} + +/** + * @brief Enables or disables the Vrefint channel. + * @param NewState: new state of the Vref input channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_VrefintCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Vrefint channel*/ + ADC->CCR |= (uint32_t)ADC_CCR_VREFEN; + } + else + { + /* Disable the Vrefint channel*/ + ADC->CCR &= (uint32_t)(~ADC_CCR_VREFEN); + } +} + +/** + * @brief Enables or disables the Vbat channel. + * @param NewState: new state of the Vbat input channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_VbatCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Vbat channel*/ + ADC->CCR |= (uint32_t)ADC_CCR_VBATEN; + } + else + { + /* Disable the Vbat channel*/ + ADC->CCR &= (uint32_t)(~ADC_CCR_VBATEN); + } +} + +/** + * @} + */ + +/** @defgroup ADC_Group5 Channels Configuration functions + * @brief Channels Configuration functions + * +@verbatim + =============================================================================== + ##### Channels Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to manage the ADC channels, + it is composed of 3 sub sections : + (#) Configuration and management functions for ADC channels: This subsection + provides functions allowing to configure the ADC channels : + (++) Select the ADC channels + (++) Activate ADC Calibration + (++) Activate the Overrun Mode. + (++) Activate the Discontinuous Mode + (++) Activate the Continuous Mode. + (++) Configure the sampling time for each channel + (++) Select the conversion Trigger and Edge for ADC channels + (++) Select the scan direction. + -@@- Please Note that the following features for ADC channels are configurated + using the ADC_Init() function : + (+@@) Activate the Continuous Mode (can be also activated by ADC_OverrunModeCmd(). + (+@@) Select the conversion Trigger and Edge for ADC channels + (+@@) Select the scan direction. + (#) Control the ADC peripheral : This subsection permits to command the ADC: + (++) Stop or discard an on-going conversion (ADSTP command) + (++) Start the ADC conversion . + (#) Get the conversion data: This subsection provides an important function in + the ADC peripheral since it returns the converted data of the current + ADC channel. When the Conversion value is read, the EOC Flag is + automatically cleared. + +@endverbatim + * @{ + */ + +/** + * @brief Configures for the selected ADC and its sampling time. + * @param ADCx: where x can be 1 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure. + * This parameter can be any combination of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @arg ADC_Channel_18: ADC Channel18 selected + * @param ADC_SampleTime: The sample time value to be set for the selected + * channel. + * This parameter can be one of the following values: + * @arg ADC_SampleTime_1_5Cycles: Sample time equal to 1.5 cycles + * @arg ADC_SampleTime_7_5Cycles: Sample time equal to 7.5 cycles + * @arg ADC_SampleTime_13_5Cycles: Sample time equal to 13.5 cycles + * @arg ADC_SampleTime_28_5Cycles: Sample time equal to 28.5 cycles + * @arg ADC_SampleTime_41_5Cycles: Sample time equal to 41.5 cycles + * @arg ADC_SampleTime_55_5Cycles: Sample time equal to 55.5 cycles + * @arg ADC_SampleTime_71_5Cycles: Sample time equal to 71.5 cycles + * @arg ADC_SampleTime_239_5Cycles: Sample time equal to 239.5 cycles + * @retval None + */ +void ADC_ChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_Channel, uint32_t ADC_SampleTime) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); + + /* Configure the ADC Channel */ + ADCx->CHSELR |= (uint32_t)ADC_Channel; + + /* Clear the Sampling time Selection bits */ + tmpreg &= ~ADC_SMPR1_SMPR; + + /* Set the ADC Sampling Time register */ + tmpreg |= (uint32_t)ADC_SampleTime; + + /* Configure the ADC Sample time register */ + ADCx->SMPR = tmpreg ; +} + +/** + * @brief Enable the Continuous mode for the selected ADCx channels. + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @param NewState: new state of the Continuous mode. + * This parameter can be: ENABLE or DISABLE. + * @note It is not possible to have both discontinuous mode and continuous mode + * enabled. In this case (If DISCEN and CONT are Set), the ADC behaves + * as if continuous mode was disabled + * @retval None + */ +void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Continuous mode*/ + ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_CONT; + } + else + { + /* Disable the Continuous mode */ + ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_CONT); + } +} + +/** + * @brief Enable the discontinuous mode for the selected ADC channels. + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @param NewState: new state of the discontinuous mode. + * This parameter can be: ENABLE or DISABLE. + * @note It is not possible to have both discontinuous mode and continuous mode + * enabled. In this case (If DISCEN and CONT are Set), the ADC behaves + * as if continuous mode was disabled + * @retval None + */ +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Discontinuous mode */ + ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_DISCEN; + } + else + { + /* Disable the Discontinuous mode */ + ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_DISCEN); + } +} + +/** + * @brief Enable the Overrun mode for the selected ADC channels. + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @param NewState: new state of the Overrun mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_OverrunModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Overrun mode */ + ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_OVRMOD; + } + else + { + /* Disable the Overrun mode */ + ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_OVRMOD); + } +} + +/** + * @brief Active the Calibration operation for the selected ADC. + * @note The Calibration can be initiated only when ADC is still in the + * reset configuration (ADEN must be equal to 0). + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @retval ADC Calibration factor + */ +uint32_t ADC_GetCalibrationFactor(ADC_TypeDef* ADCx) +{ + uint32_t tmpreg = 0, calibrationcounter = 0, calibrationstatus = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /* Set the ADC calibartion */ + ADCx->CR |= (uint32_t)ADC_CR_ADCAL; + + /* Wait until no ADC calibration is completed */ + do + { + calibrationstatus = ADCx->CR & ADC_CR_ADCAL; + calibrationcounter++; + } while((calibrationcounter != CALIBRATION_TIMEOUT) && (calibrationstatus != 0x00)); + + if((uint32_t)(ADCx->CR & ADC_CR_ADCAL) == RESET) + { + /*Get the calibration factor from the ADC data register */ + tmpreg = ADCx->DR; + } + else + { + /* Error factor */ + tmpreg = 0x00000000; + } + return tmpreg; +} + +/** + * @brief Stop the on going conversions for the selected ADC. + * @note When ADSTP is set, any on going conversion is aborted, and the ADC + * data register is not updated with current conversion. + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @retval None + */ +void ADC_StopOfConversion(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + ADCx->CR |= (uint32_t)ADC_CR_ADSTP; +} + +/** + * @brief Start Conversion for the selected ADC channels. + * @note In continuous mode, ADSTART is not cleared by hardware with the + * assertion of EOSEQ because the sequence is automatic relaunched + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @retval None + */ +void ADC_StartOfConversion(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + ADCx->CR |= (uint32_t)ADC_CR_ADSTART; +} + +/** + * @brief Returns the last ADCx conversion result data for ADC channel. + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @retval The Data conversion value. + */ +uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /* Return the selected ADC conversion value */ + return (uint16_t) ADCx->DR; +} + +/** + * @} + */ + +/** @defgroup ADC_Group6 DMA Configuration functions + * @brief Regular Channels DMA Configuration functions + * +@verbatim + =============================================================================== + ##### DMA Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to configure the DMA for ADC hannels. + Since converted channel values are stored into a unique data register, + it is useful to use DMA for conversion of more than one channel. This + avoids the loss of the data already stored in the ADC Data register. + When the DMA mode is enabled (using the ADC_DMACmd() function), after each + conversion of a channel, a DMA request is generated. + + [..] Depending on the "DMA disable selection" configuration (using the + ADC_DMARequestModeConfig() function), at the end of the last DMA + transfer, two possibilities are allowed: + (+) No new DMA request is issued to the DMA controller (One Shot Mode) + (+) Requests can continue to be generated (Circular Mode). + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified ADC DMA request. + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @param NewState: new state of the selected ADC DMA transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC DMA request */ + ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_DMAEN; + } + else + { + /* Disable the selected ADC DMA request */ + ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_DMAEN); + } +} + +/** + * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode) + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @param ADC_DMARequestMode: the ADC channel to configure. + * This parameter can be one of the following values: + * @arg ADC_DMAMode_OneShot : DMA One Shot Mode + * @arg ADC_DMAMode_Circular : DMA Circular Mode + * @retval None + */ +void ADC_DMARequestModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMARequestMode) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_DMACFG; + ADCx->CFGR1 |= (uint32_t)ADC_DMARequestMode; +} + +/** + * @} + */ + +/** @defgroup ADC_Group7 Interrupts and flags management functions + * @brief Interrupts and flags management functions. + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + [..] This section provides functions allowing to configure the ADC Interrupts + and get the status and clear flags and Interrupts pending bits. + + [..] The ADC provide 6 Interrupts sources and 11 Flags which can be divided into + 3 groups: + + *** Flags for ADC status *** + ====================================================== + [..] + (+)Flags : + (##) ADC_FLAG_ADRDY : This flag is set after the ADC has been enabled (bit ADEN=1) + and when the ADC reaches a state where it is ready to accept conversion requests + (##) ADC_FLAG_ADEN : This flag is set by software to enable the ADC. + The ADC will be effectively ready to operate once the ADRDY flag has been set. + (##) ADC_FLAG_ADDIS : This flag is cleared once the ADC is effectively + disabled. + (##) ADC_FLAG_ADSTART : This flag is cleared after the execution of + ADC_StopOfConversion() function, at the same time as the ADSTP bit is + cleared by hardware + (##) ADC_FLAG_ADSTP : This flag is cleared by hardware when the conversion + is effectively discarded and the ADC is ready to accept a new start conversion + (##) ADC_FLAG_ADCAL : This flag is set once the calibration is complete. + + (+)Interrupts + (##) ADC_IT_ADRDY : specifies the interrupt source for ADC ready event. + + *** Flags and Interrupts for ADC channel conversion *** + ===================================================== + [..] + (+)Flags : + (##) ADC_FLAG_EOC : This flag is set by hardware at the end of each conversion + of a channel when a new data result is available in the data register + (##) ADC_FLAG_EOSEQ : This bit is set by hardware at the end of the conversion + of a sequence of channels selected by ADC_ChannelConfig() function. + (##) ADC_FLAG_EOSMP : This bit is set by hardware at the end of the sampling phase. + (##) ADC_FLAG_OVR : This flag is set by hardware when an overrun occurs, + meaning that a new conversion has complete while the EOC flag was already set. + + (+)Interrupts : + (##) ADC_IT_EOC : specifies the interrupt source for end of conversion event. + (##) ADC_IT_EOSEQ : specifies the interrupt source for end of sequence event. + (##) ADC_IT_EOSMP : specifies the interrupt source for end of sampling event. + (##) ADC_IT_OVR : specifies the interrupt source for Overrun detection + event. + + *** Flags and Interrupts for the Analog Watchdog *** + ================================================ + [..] + (+)Flags : + (##) ADC_FLAG_AWD: This flag is set by hardware when the converted + voltage crosses the values programmed thrsholds + + (+)Interrupts : + (##) ADC_IT_AWD : specifies the interrupt source for Analog watchdog + event. + + [..] The user should identify which mode will be used in his application to + manage the ADC controller events: Polling mode or Interrupt mode. + + [..] In the Polling Mode it is advised to use the following functions: + (+) ADC_GetFlagStatus() : to check if flags events occur. + (+) ADC_ClearFlag() : to clear the flags events. + + [..] In the Interrupt Mode it is advised to use the following functions: + (+) ADC_ITConfig() : to enable or disable the interrupt source. + (+) ADC_GetITStatus() : to check if Interrupt occurs. + (+) ADC_ClearITPendingBit() : to clear the Interrupt pending Bit + (corresponding Flag). + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified ADC interrupts. + * @param ADCx: where x can be 1 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg ADC_IT_ADRDY: ADC ready interrupt + * @arg ADC_IT_EOSMP: End of sampling interrupt + * @arg ADC_IT_EOC: End of conversion interrupt + * @arg ADC_IT_EOSEQ: End of sequence of conversion interrupt + * @arg ADC_IT_OVR: overrun interrupt + * @arg ADC_IT_AWD: Analog watchdog interrupt + * @param NewState: new state of the specified ADC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_ADC_CONFIG_IT(ADC_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC interrupts */ + ADCx->IER |= ADC_IT; + } + else + { + /* Disable the selected ADC interrupts */ + ADCx->IER &= (~(uint32_t)ADC_IT); + } +} + +/** + * @brief Checks whether the specified ADC flag is set or not. + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @param ADC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ADC_FLAG_AWD: Analog watchdog flag + * @arg ADC_FLAG_OVR: Overrun flag + * @arg ADC_FLAG_EOSEQ: End of Sequence flag + * @arg ADC_FLAG_EOC: End of conversion flag + * @arg ADC_FLAG_EOSMP: End of sampling flag + * @arg ADC_FLAG_ADRDY: ADC Ready flag + * @arg ADC_FLAG_ADEN: ADC enable flag + * @arg ADC_FLAG_ADDIS: ADC disable flag + * @arg ADC_FLAG_ADSTART: ADC start flag + * @arg ADC_FLAG_ADSTP: ADC stop flag + * @arg ADC_FLAG_ADCAL: ADC Calibration flag + * @retval The new state of ADC_FLAG (SET or RESET). + */ +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); + + if((uint32_t)(ADC_FLAG & 0x01000000)) + { + tmpreg = ADCx->CR & 0xFEFFFFFF; + } + else + { + tmpreg = ADCx->ISR; + } + + /* Check the status of the specified ADC flag */ + if ((tmpreg & ADC_FLAG) != (uint32_t)RESET) + { + /* ADC_FLAG is set */ + bitstatus = SET; + } + else + { + /* ADC_FLAG is reset */ + bitstatus = RESET; + } + /* Return the ADC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the ADCx's pending flags. + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @param ADC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_AWD: Analog watchdog flag + * @arg ADC_FLAG_EOC: End of conversion flag + * @arg ADC_FLAG_ADRDY: ADC Ready flag + * @arg ADC_FLAG_EOSMP: End of sampling flag + * @arg ADC_FLAG_EOSEQ: End of Sequence flag + * @arg ADC_FLAG_OVR: Overrun flag + * @retval None + */ +void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); + + /* Clear the selected ADC flags */ + ADCx->ISR = (uint32_t)ADC_FLAG; +} + +/** + * @brief Checks whether the specified ADC interrupt has occurred or not. + * @param ADCx: where x can be 1 to select the ADC1 peripheral + * @param ADC_IT: specifies the ADC interrupt source to check. + * This parameter can be one of the following values: + * @arg ADC_IT_ADRDY: ADC ready interrupt + * @arg ADC_IT_EOSMP: End of sampling interrupt + * @arg ADC_IT_EOC: End of conversion interrupt + * @arg ADC_IT_EOSEQ: End of sequence of conversion interrupt + * @arg ADC_IT_OVR: overrun interrupt + * @arg ADC_IT_AWD: Analog watchdog interrupt + * @retval The new state of ADC_IT (SET or RESET). + */ +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_GET_IT(ADC_IT)); + + /* Get the ADC_IT enable bit status */ + enablestatus = (uint32_t)(ADCx->IER & ADC_IT); + + /* Check the status of the specified ADC interrupt */ + if (((uint32_t)(ADCx->ISR & ADC_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + /* ADC_IT is set */ + bitstatus = SET; + } + else + { + /* ADC_IT is reset */ + bitstatus = RESET; + } + /* Return the ADC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the ADCx's interrupt pending bits. + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @param ADC_IT: specifies the ADC interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg ADC_IT_ADRDY: ADC ready interrupt + * @arg ADC_IT_EOSMP: End of sampling interrupt + * @arg ADC_IT_EOC: End of conversion interrupt + * @arg ADC_IT_EOSEQ: End of sequence of conversion interrupt + * @arg ADC_IT_OVR: overrun interrupt + * @arg ADC_IT_AWD: Analog watchdog interrupt + * @retval None + */ +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CLEAR_IT(ADC_IT)); + + /* Clear the selected ADC interrupt pending bits */ + ADCx->ISR = (uint32_t)ADC_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_cec.c b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_cec.c new file mode 100644 index 0000000..97ba5b9 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_cec.c @@ -0,0 +1,606 @@ +/** + ****************************************************************************** + * @file stm32f0xx_cec.c + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Consumer Electronics Control (CEC) peripheral: + * + Initialization and Configuration + * + Data transfers functions + * + Interrupts and flags management + * + * @verbatim + ============================================================================== + ##### CEC features ##### + ============================================================================== + [..] This device provides some features: + (#) Supports HDMI-CEC specification 1.4. + (#) Supports two source clocks(HSI/244 or LSE). + (#) Works in stop mode(without APB clock, but with CEC clock 32KHz). + It can genarate an interrupt in the CEC clock domain that the CPU + wakes up from the low power mode. + (#) Configurable Signal Free Time before of transmission start. The + number of nominal data bit periods waited before transmission can be + ruled by Hardware or Software. + (#) Configurable Peripheral Address (multi-addressing configuration). + (#) Supports listen mode.The CEC Messages addressed to different destination + can be received without interfering with CEC bus when Listen mode option is enabled. + (#) Configurable Rx-Tolerance(Standard and Extended tolerance margin). + (#) Error detection with configurable error bit generation. + (#) Arbitration lost error in the case of two CEC devices starting at the same time. + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure and program the CEC device, + follow steps below: + (#) The source clock can be configured using: + (++) RCC_CECCLKConfig(RCC_CECCLK_HSI_Div244) for HSI(Default) + (++) RCC_CECCLKConfig(RCC_CECCLK_LSE) for LSE. + (#) Enable CEC peripheral clock using RCC_APBPeriphClockCmd(RCC_APBPeriph_CEC, ENABLE). + (#) Peripherals alternate function. + (++) Connect the pin to the desired peripherals' Alternate Function (AF) using + GPIO_PinAFConfig() function. + (++) Configure the desired pin in alternate function by: + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF. + (++) Select the type open-drain and output speed via GPIO_OType + and GPIO_Speed members. + (++) Call GPIO_Init() function. + (#) Configure the Signal Free Time, Rx Tolerance, Stop reception generation + and Bit error generation using the CEC_Init() function. + The function CEC_Init() must be called when the CEC peripheral is disabled. + (#) Configure the CEC own address by calling the fuction CEC_OwnAddressConfig(). + (#) Optionally, you can configure the Listen mode using the function CEC_ListenModeCmd(). + (#) Enable the NVIC and the corresponding interrupt using the function + CEC_ITConfig() if you need to use interrupt mode. + CEC_ITConfig() must be called before enabling the CEC peripheral. + (#) Enable the CEC using the CEC_Cmd() function. + (#) Charge the first data byte in the TXDR register using CEC_SendDataByte(). + (#) Enable the transmission of the Byte of a CEC message using CEC_StartOfMessage() + (#) Transmit single data through the CEC peripheral using CEC_SendDataByte() + and Receive the last transmitted byte using CEC_ReceiveDataByte(). + (#) Enable the CEC_EndOfMessage() in order to indicate the last byte of the message. + [..] + (@) If the listen mode is enabled, Stop reception generation and Bit error generation + must be in reset state. + (@) If the CEC message consists of only 1 byte, the function CEC_EndOfMessage() + must be called before CEC_StartOfMessage(). + + @endverbatim + * + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_cec.h" +#include "stm32f0xx_rcc.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup CEC + * @brief CEC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define BROADCAST_ADDRESS ((uint32_t)0x0000F) +#define CFGR_CLEAR_MASK ((uint32_t)0x7000FE00) /* CFGR register Mask */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup CEC_Private_Functions + * @{ + */ + +/** @defgroup CEC_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to initialize: + (+) CEC own addresses + (+) CEC Signal Free Time + (+) CEC Rx Tolerance + (+) CEC Stop Reception + (+) CEC Bit Rising Error + (+) CEC Long Bit Period Error + [..] This section provides also a function to configure the CEC peripheral in Listen Mode. + Messages addressed to different destination can be received when Listen mode is + enabled without interfering with CEC bus. +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the CEC peripheral registers to their default reset values. + * @param None + * @retval None + */ +void CEC_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE); +} + +/** + * @brief Initializes the CEC peripheral according to the specified parameters + * in the CEC_InitStruct. + * @note The CEC parameters must be configured before enabling the CEC peripheral. + * @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that contains + * the configuration information for the specified CEC peripheral. + * @retval None + */ +void CEC_Init(CEC_InitTypeDef* CEC_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_CEC_SIGNAL_FREE_TIME(CEC_InitStruct->CEC_SignalFreeTime)); + assert_param(IS_CEC_RX_TOLERANCE(CEC_InitStruct->CEC_RxTolerance)); + assert_param(IS_CEC_STOP_RECEPTION(CEC_InitStruct->CEC_StopReception)); + assert_param(IS_CEC_BIT_RISING_ERROR(CEC_InitStruct->CEC_BitRisingError)); + assert_param(IS_CEC_LONG_BIT_PERIOD_ERROR(CEC_InitStruct->CEC_LongBitPeriodError)); + assert_param(IS_CEC_BDR_NO_GEN_ERROR(CEC_InitStruct->CEC_BRDNoGen)); + assert_param(IS_CEC_SFT_OPTION(CEC_InitStruct->CEC_SFTOption)); + + /* Get the CEC CFGR value */ + tmpreg = CEC->CFGR; + + /* Clear CFGR bits */ + tmpreg &= CFGR_CLEAR_MASK; + + /* Configure the CEC peripheral */ + tmpreg |= (CEC_InitStruct->CEC_SignalFreeTime | CEC_InitStruct->CEC_RxTolerance | + CEC_InitStruct->CEC_StopReception | CEC_InitStruct->CEC_BitRisingError | + CEC_InitStruct->CEC_LongBitPeriodError| CEC_InitStruct->CEC_BRDNoGen | + CEC_InitStruct->CEC_SFTOption); + + /* Write to CEC CFGR register */ + CEC->CFGR = tmpreg; +} + +/** + * @brief Fills each CEC_InitStruct member with its default value. + * @param CEC_InitStruct: pointer to a CEC_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void CEC_StructInit(CEC_InitTypeDef* CEC_InitStruct) +{ + CEC_InitStruct->CEC_SignalFreeTime = CEC_SignalFreeTime_Standard; + CEC_InitStruct->CEC_RxTolerance = CEC_RxTolerance_Standard; + CEC_InitStruct->CEC_StopReception = CEC_StopReception_Off; + CEC_InitStruct->CEC_BitRisingError = CEC_BitRisingError_Off; + CEC_InitStruct->CEC_LongBitPeriodError = CEC_LongBitPeriodError_Off; + CEC_InitStruct->CEC_BRDNoGen = CEC_BRDNoGen_Off; + CEC_InitStruct->CEC_SFTOption = CEC_SFTOption_Off; +} + +/** + * @brief Enables or disables the CEC peripheral. + * @param NewState: new state of the CEC peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CEC_Cmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the CEC peripheral */ + CEC->CR |= CEC_CR_CECEN; + } + else + { + /* Disable the CEC peripheral */ + CEC->CR &= ~CEC_CR_CECEN; + } +} + +/** + * @brief Enables or disables the CEC Listen Mode. + * @param NewState: new state of the Listen Mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CEC_ListenModeCmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Listen Mode */ + CEC->CFGR |= CEC_CFGR_LSTN; + } + else + { + /* Disable the Listen Mode */ + CEC->CFGR &= ~CEC_CFGR_LSTN; + } +} + +/** + * @brief Defines the Own Address of the CEC device. + * @param CEC_OwnAddress: The CEC own address. + * @retval None + */ +void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress) +{ + uint32_t tmp =0x00; + /* Check the parameters */ + assert_param(IS_CEC_ADDRESS(CEC_OwnAddress)); + tmp = 1 <<(CEC_OwnAddress + 16); + /* Set the CEC own address */ + CEC->CFGR |= tmp; +} + +/** + * @brief Clears the Own Address of the CEC device. + * @param CEC_OwnAddress: The CEC own address. + * @retval None + */ +void CEC_OwnAddressClear(void) +{ + /* Set the CEC own address */ + CEC->CFGR = 0x0; +} + +/** + * @} + */ + +/** @defgroup CEC_Group2 Data transfers functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### Data transfers functions ##### + =============================================================================== + [..] This section provides functions allowing the CEC data transfers.The read + access of the CEC_RXDR register can be done using the CEC_ReceiveData()function + and returns the Rx buffered value. Whereas a write access to the CEC_TXDR can be + done using CEC_SendData() function. +@endverbatim + * @{ + */ + +/** + * @brief Transmits single data through the CEC peripheral. + * @param Data: the data to transmit. + * @retval None + */ +void CEC_SendData(uint8_t Data) +{ + /* Transmit Data */ + CEC->TXDR = Data; +} + +/** + * @brief Returns the most recent received data by the CEC peripheral. + * @param None + * @retval The received data. + */ +uint8_t CEC_ReceiveData(void) +{ + /* Receive Data */ + return (uint8_t)(CEC->RXDR); +} + +/** + * @brief Starts a new message. + * @param None + * @retval None + */ +void CEC_StartOfMessage(void) +{ + /* Starts of new message */ + CEC->CR |= CEC_CR_TXSOM; +} + +/** + * @brief Transmits message with an EOM bit. + * @param None. + * @retval None + */ +void CEC_EndOfMessage(void) +{ + /* The data byte will be transmitted with an EOM bit */ + CEC->CR |= CEC_CR_TXEOM; +} + +/** + * @} + */ + +/** @defgroup CEC_Group3 Interrupts and flags management functions + * @brief Interrupts and flags management functions +* +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + [..] This section provides functions allowing to configure the CEC Interrupts + sources and check or clear the flags or pending bits status. + [..] The user should identify which mode will be used in his application to manage + the communication: Polling mode or Interrupt mode. + + [..] In polling mode, the CEC can be managed by the following flags: + (+) CEC_FLAG_TXACKE : to indicate a missing acknowledge in transmission mode. + (+) CEC_FLAG_TXERR : to indicate an error occurs during transmission mode. + The initiator detects low impedance in the CEC line. + (+) CEC_FLAG_TXUDR : to indicate if an underrun error occurs in transmission mode. + The transmission is enabled while the software has not yet + loaded any value into the TXDR register. + (+) CEC_FLAG_TXEND : to indicate the end of successful transmission. + (+) CEC_FLAG_TXBR : to indicate the next transmission data has to be written to TXDR. + (+) CEC_FLAG_ARBLST : to indicate arbitration lost in the case of two CEC devices + starting at the same time. + (+) CEC_FLAG_RXACKE : to indicate a missing acknowledge in receive mode. + (+) CEC_FLAG_LBPE : to indicate a long bit period error generated during receive mode. + (+) CEC_FLAG_SBPE : to indicate a short bit period error generated during receive mode. + (+) CEC_FLAG_BRE : to indicate a bit rising error generated during receive mode. + (+) CEC_FLAG_RXOVR : to indicate if an overrun error occur while receiving a CEC message. + A byte is not yet received while a new byte is stored in the RXDR register. + (+) CEC_FLAG_RXEND : to indicate the end Of reception + (+) CEC_FLAG_RXBR : to indicate a new byte has been received from the CEC line and + stored into the RXDR buffer. + [..] + (@)In this Mode, it is advised to use the following functions: + FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG); + void CEC_ClearFlag(uint16_t CEC_FLAG); + + [..] In Interrupt mode, the CEC can be managed by the following interrupt sources: + (+) CEC_IT_TXACKE : to indicate a TX Missing acknowledge + (+) CEC_IT_TXACKE : to indicate a missing acknowledge in transmission mode. + (+) CEC_IT_TXERR : to indicate an error occurs during transmission mode. + The initiator detects low impedance in the CEC line. + (+) CEC_IT_TXUDR : to indicate if an underrun error occurs in transmission mode. + The transmission is enabled while the software has not yet + loaded any value into the TXDR register. + (+) CEC_IT_TXEND : to indicate the end of successful transmission. + (+) CEC_IT_TXBR : to indicate the next transmission data has to be written to TXDR register. + (+) CEC_IT_ARBLST : to indicate arbitration lost in the case of two CEC devices + starting at the same time. + (+) CEC_IT_RXACKE : to indicate a missing acknowledge in receive mode. + (+) CEC_IT_LBPE : to indicate a long bit period error generated during receive mode. + (+) CEC_IT_SBPE : to indicate a short bit period error generated during receive mode. + (+) CEC_IT_BRE : to indicate a bit rising error generated during receive mode. + (+) CEC_IT_RXOVR : to indicate if an overrun error occur while receiving a CEC message. + A byte is not yet received while a new byte is stored in the RXDR register. + (+) CEC_IT_RXEND : to indicate the end Of reception + (+) CEC_IT_RXBR : to indicate a new byte has been received from the CEC line and + stored into the RXDR buffer. + [..] + (@)In this Mode it is advised to use the following functions: + void CEC_ITConfig( uint16_t CEC_IT, FunctionalState NewState); + ITStatus CEC_GetITStatus(uint16_t CEC_IT); + void CEC_ClearITPendingBit(uint16_t CEC_IT); + + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the selected CEC interrupts. + * @param CEC_IT: specifies the CEC interrupt source to be enabled. + * This parameter can be any combination of the following values: + * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error + * @arg CEC_IT_TXERR: Tx Error. + * @arg CEC_IT_TXUDR: Tx-Buffer Underrun. + * @arg CEC_IT_TXEND: End of Transmission (successful transmission of the last byte). + * @arg CEC_IT_TXBR: Tx-Byte Request. + * @arg CEC_IT_ARBLST: Arbitration Lost + * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge + * @arg CEC_IT_LBPE: Rx Long period Error + * @arg CEC_IT_SBPE: Rx Short period Error + * @arg CEC_IT_BRE: Rx Bit Rising Error + * @arg CEC_IT_RXOVR: Rx Overrun. + * @arg CEC_IT_RXEND: End Of Reception + * @arg CEC_IT_RXBR: Rx-Byte Received + * @param NewState: new state of the selected CEC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CEC_ITConfig(uint16_t CEC_IT, FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_CEC_IT(CEC_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected CEC interrupt */ + CEC->IER |= CEC_IT; + } + else + { + CEC_IT =~CEC_IT; + /* Disable the selected CEC interrupt */ + CEC->IER &= CEC_IT; + } +} + +/** + * @brief Gets the CEC flag status. + * @param CEC_FLAG: specifies the CEC flag to check. + * This parameter can be one of the following values: + * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error + * @arg CEC_FLAG_TXERR: Tx Error. + * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun. + * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte). + * @arg CEC_FLAG_TXBR: Tx-Byte Request. + * @arg CEC_FLAG_ARBLST: Arbitration Lost + * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge + * @arg CEC_FLAG_LBPE: Rx Long period Error + * @arg CEC_FLAG_SBPE: Rx Short period Error + * @arg CEC_FLAG_BRE: Rx Bit Rissing Error + * @arg CEC_FLAG_RXOVR: Rx Overrun. + * @arg CEC_FLAG_RXEND: End Of Reception. + * @arg CEC_FLAG_RXBR: Rx-Byte Received. + * @retval The new state of CEC_FLAG (SET or RESET) + */ +FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG) +{ + FlagStatus bitstatus = RESET; + + assert_param(IS_CEC_GET_FLAG(CEC_FLAG)); + + /* Check the status of the specified CEC flag */ + if ((CEC->ISR & CEC_FLAG) != (uint16_t)RESET) + { + /* CEC flag is set */ + bitstatus = SET; + } + else + { + /* CEC flag is reset */ + bitstatus = RESET; + } + + /* Return the CEC flag status */ + return bitstatus; +} + +/** + * @brief Clears the CEC's pending flags. + * @param CEC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error + * @arg CEC_FLAG_TXERR: Tx Error + * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun + * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte). + * @arg CEC_FLAG_TXBR: Tx-Byte Request + * @arg CEC_FLAG_ARBLST: Arbitration Lost + * @arg CEC_FLAG_RXACKE: Rx Missing Acknowledge + * @arg CEC_FLAG_LBPE: Rx Long period Error + * @arg CEC_FLAG_SBPE: Rx Short period Error + * @arg CEC_FLAG_BRE: Rx Bit Rising Error + * @arg CEC_FLAG_RXOVR: Rx Overrun + * @arg CEC_FLAG_RXEND: End Of Reception + * @arg CEC_FLAG_RXBR: Rx-Byte Received + * @retval None + */ +void CEC_ClearFlag(uint32_t CEC_FLAG) +{ + assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG)); + + /* Clear the selected CEC flag */ + CEC->ISR = CEC_FLAG; +} + +/** + * @brief Checks whether the specified CEC interrupt has occurred or not. + * @param CEC_IT: specifies the CEC interrupt source to check. + * This parameter can be one of the following values: + * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error + * @arg CEC_IT_TXERR: Tx Error. + * @arg CEC_IT_TXUDR: Tx-Buffer Underrun. + * @arg CEC_IT_TXEND: End of transmission (successful transmission of the last byte). + * @arg CEC_IT_TXBR: Tx-Byte Request. + * @arg CEC_IT_ARBLST: Arbitration Lost. + * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge. + * @arg CEC_IT_LBPE: Rx Long period Error. + * @arg CEC_IT_SBPE: Rx Short period Error. + * @arg CEC_IT_BRE: Rx Bit Rising Error. + * @arg CEC_IT_RXOVR: Rx Overrun. + * @arg CEC_IT_RXEND: End Of Reception. + * @arg CEC_IT_RXBR: Rx-Byte Received + * @retval The new state of CEC_IT (SET or RESET). + */ +ITStatus CEC_GetITStatus(uint16_t CEC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_CEC_GET_IT(CEC_IT)); + + /* Get the CEC IT enable bit status */ + enablestatus = (CEC->IER & CEC_IT); + + /* Check the status of the specified CEC interrupt */ + if (((CEC->ISR & CEC_IT) != (uint32_t)RESET) && enablestatus) + { + /* CEC interrupt is set */ + bitstatus = SET; + } + else + { + /* CEC interrupt is reset */ + bitstatus = RESET; + } + + /* Return the CEC interrupt status */ + return bitstatus; +} + +/** + * @brief Clears the CEC's interrupt pending bits. + * @param CEC_IT: specifies the CEC interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error + * @arg CEC_IT_TXERR: Tx Error + * @arg CEC_IT_TXUDR: Tx-Buffer Underrun + * @arg CEC_IT_TXEND: End of Transmission + * @arg CEC_IT_TXBR: Tx-Byte Request + * @arg CEC_IT_ARBLST: Arbitration Lost + * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge + * @arg CEC_IT_LBPE: Rx Long period Error + * @arg CEC_IT_SBPE: Rx Short period Error + * @arg CEC_IT_BRE: Rx Bit Rising Error + * @arg CEC_IT_RXOVR: Rx Overrun + * @arg CEC_IT_RXEND: End Of Reception + * @arg CEC_IT_RXBR: Rx-Byte Received + * @retval None + */ +void CEC_ClearITPendingBit(uint16_t CEC_IT) +{ + assert_param(IS_CEC_IT(CEC_IT)); + + /* Clear the selected CEC interrupt pending bits */ + CEC->ISR = CEC_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_comp.c b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_comp.c new file mode 100644 index 0000000..9eee44c --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_comp.c @@ -0,0 +1,409 @@ +/** + ****************************************************************************** + * @file stm32f0xx_comp.c + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the comparators (COMP1 and COMP2) peripheral: + * + Comparators configuration + * + Window mode control + * + * @verbatim + * + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + + The device integrates two analog comparators COMP1 and COMP2: + (+) The non inverting input is set to PA1 for COMP1 and to PA3 + for COMP2. + + (+) The inverting input can be selected among: DAC_OUT1, + 1/4 VREFINT, 1/2 VERFINT, 3/4 VREFINT, VREFINT, + I/O (PA0 for COMP1 and PA2 for COMP2) + + (+) The COMP output is internally is available using COMP_GetOutputLevel() + and can be set on GPIO pins: PA0, PA6, PA11 for COMP1 + and PA2, PA7, PA12 for COMP2 + + (+) The COMP output can be redirected to embedded timers (TIM1, TIM2 + and TIM3) + + (+) The two comparators COMP1 and COMP2 can be combined in window + mode and only COMP1 non inverting (PA1) can be used as non- + inverting input. + + (+) The two comparators COMP1 and COMP2 have interrupt capability + with wake-up from Sleep and Stop modes (through the EXTI controller). + COMP1 and COMP2 outputs are internally connected to EXTI Line 21 + and EXTI Line 22 respectively. + + + ##### How to configure the comparator ##### + =============================================================================== + [..] + This driver provides functions to configure and program the Comparators + of all STM32F0xx devices. + + [..] To use the comparator, perform the following steps: + + (#) Enable the SYSCFG APB clock to get write access to comparator + register using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); + + (#) Configure the comparator input in analog mode using GPIO_Init() + + (#) Configure the comparator output in alternate function mode + using GPIO_Init() and use GPIO_PinAFConfig() function to map the + comparator output to the GPIO pin + + (#) Configure the comparator using COMP_Init() function: + (++) Select the inverting input + (++) Select the output polarity + (++) Select the output redirection + (++) Select the hysteresis level + (++) Select the power mode + + (#) Enable the comparator using COMP_Cmd() function + + (#) If required enable the COMP interrupt by configuring and enabling + EXTI line in Interrupt mode and selecting the desired sensitivity + level using EXTI_Init() function. After that enable the comparator + interrupt vector using NVIC_Init() function. + + @endverbatim + * + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_comp.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup COMP + * @brief COMP driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* CSR register Mask */ +#define COMP_CSR_CLEAR_MASK ((uint32_t)0x00003FFE) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup COMP_Private_Functions + * @{ + */ + +/** @defgroup COMP_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes COMP peripheral registers to their default reset values. + * @note Deinitialization can't be performed if the COMP configuration is locked. + * To unlock the configuration, perform a system reset. + * @param None + * @retval None + */ +void COMP_DeInit(void) +{ + COMP->CSR = ((uint32_t)0x00000000); /*!< Set COMP_CSR register to reset value */ +} + +/** + * @brief Initializes the COMP peripheral according to the specified parameters + * in COMP_InitStruct + * @note If the selected comparator is locked, initialization can't be performed. + * To unlock the configuration, perform a system reset. + * @note By default, PA1 is selected as COMP1 non inverting input. + * To use PA4 as COMP1 non inverting input call COMP_SwitchCmd() after COMP_Init() + * @param COMP_Selection: the selected comparator. + * This parameter can be one of the following values: + * @arg COMP_Selection_COMP1: COMP1 selected + * @arg COMP_Selection_COMP2: COMP2 selected + * @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure that contains + * the configuration information for the specified COMP peripheral. + * + * @retval None + */ +void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_COMP_ALL_PERIPH(COMP_Selection)); + assert_param(IS_COMP_INVERTING_INPUT(COMP_InitStruct->COMP_InvertingInput)); + assert_param(IS_COMP_OUTPUT(COMP_InitStruct->COMP_Output)); + assert_param(IS_COMP_OUTPUT_POL(COMP_InitStruct->COMP_OutputPol)); + assert_param(IS_COMP_HYSTERESIS(COMP_InitStruct->COMP_Hysteresis)); + assert_param(IS_COMP_MODE(COMP_InitStruct->COMP_Mode)); + + /*!< Get the COMP_CSR register value */ + tmpreg = COMP->CSR; + + /*!< Clear the COMP1SW1, COMPx_IN_SEL, COMPx_OUT_TIM_SEL, COMPx_POL, COMPx_HYST and COMPx_PWR_MODE bits */ + tmpreg &= (uint32_t) ~(COMP_CSR_CLEAR_MASK<COMP_InvertingInput value */ + /*!< Set COMPxOUTSEL bits according to COMP_InitStruct->COMP_Output value */ + /*!< Set COMPxPOL bit according to COMP_InitStruct->COMP_OutputPol value */ + /*!< Set COMPxHYST bits according to COMP_InitStruct->COMP_Hysteresis value */ + /*!< Set COMPxMODE bits according to COMP_InitStruct->COMP_Mode value */ + tmpreg |= (uint32_t)((COMP_InitStruct->COMP_InvertingInput | COMP_InitStruct->COMP_Output | + COMP_InitStruct->COMP_OutputPol | COMP_InitStruct->COMP_Hysteresis | + COMP_InitStruct->COMP_Mode)<CSR = tmpreg; +} + +/** + * @brief Fills each COMP_InitStruct member with its default value. + * @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct) +{ + COMP_InitStruct->COMP_InvertingInput = COMP_InvertingInput_1_4VREFINT; + COMP_InitStruct->COMP_Output = COMP_Output_None; + COMP_InitStruct->COMP_OutputPol = COMP_OutputPol_NonInverted; + COMP_InitStruct->COMP_Hysteresis = COMP_Hysteresis_No; + COMP_InitStruct->COMP_Mode = COMP_Mode_UltraLowPower; +} + +/** + * @brief Enable or disable the COMP peripheral. + * @note If the selected comparator is locked, enable/disable can't be performed. + * To unlock the configuration, perform a system reset. + * @param COMP_Selection: the selected comparator. + * This parameter can be one of the following values: + * @arg COMP_Selection_COMP1: COMP1 selected + * @arg COMP_Selection_COMP2: COMP2 selected + * @param NewState: new state of the COMP peripheral. + * This parameter can be: ENABLE or DISABLE. + * @note When enabled, the comparator compares the non inverting input with + * the inverting input and the comparison result is available + * on comparator output. + * @note When disabled, the comparator doesn't perform comparison and the + * output level is low. + * @retval None + */ +void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_COMP_ALL_PERIPH(COMP_Selection)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected COMP peripheral */ + COMP->CSR |= (uint32_t) (1<CSR &= (uint32_t)(~((uint32_t)1<CSR |= (uint32_t) (COMP_CSR_COMP1SW1); + } + else + { + /* Open SW1 switch */ + COMP->CSR &= (uint32_t)(~COMP_CSR_COMP1SW1); + } +} + +/** + * @brief Return the output level (high or low) of the selected comparator. + * @note The output level depends on the selected polarity. + * If the polarity is not inverted: + * @note -Comparator output is low when the non-inverting input is at a lower + * voltage than the inverting input + * @note -Comparator output is high when the non-inverting input is at a higher + * voltage than the inverting input + * @note If the polarity is inverted: + * @note -Comparator output is high when the non-inverting input is at a lower + * voltage than the inverting input + * @note -Comparator output is low when the non-inverting input is at a higher + * voltage than the inverting input + * @param COMP_Selection: the selected comparator. + * This parameter can be one of the following values: + * @arg COMP_Selection_COMP1: COMP1 selected + * @arg COMP_Selection_COMP2: COMP2 selected + * @retval Returns the selected comparator output level: low or high. + * + */ +uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection) +{ + uint32_t compout = 0x0; + + /* Check the parameters */ + assert_param(IS_COMP_ALL_PERIPH(COMP_Selection)); + + /* Check if selected comparator output is high */ + if ((COMP->CSR & (COMP_CSR_COMP1OUT<CSR |= (uint32_t) COMP_CSR_WNDWEN; + } + else + { + /* Disable the window mode */ + COMP->CSR &= (uint32_t)(~COMP_CSR_WNDWEN); + } +} + +/** + * @} + */ + +/** @defgroup COMP_Group3 COMP configuration locking function + * @brief COMP1 and COMP2 configuration locking function + * COMP1 and COMP2 configuration can be locked each separately. + * Unlocking is performed by system reset. + * +@verbatim + =============================================================================== + ##### Configuration Lock function ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Lock the selected comparator (COMP1/COMP2) configuration. + * @note Locking the configuration means that all control bits are read-only. + * To unlock the comparator configuration, perform a system reset. + * @param COMP_Selection: selects the comparator to be locked + * This parameter can be a value of the following values: + * @arg COMP_Selection_COMP1: COMP1 configuration is locked. + * @arg COMP_Selection_COMP2: COMP2 configuration is locked. + * @retval None + */ +void COMP_LockConfig(uint32_t COMP_Selection) +{ + /* Check the parameter */ + assert_param(IS_COMP_ALL_PERIPH(COMP_Selection)); + + /* Set the lock bit corresponding to selected comparator */ + COMP->CSR |= (uint32_t) (COMP_CSR_COMP1LOCK<
    © COPYRIGHT 2012 STMicroelectronics
    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_crc.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup CRC + * @brief CRC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup CRC_Private_Functions + * @{ + */ + +/** @defgroup CRC_Group1 Configuration of the CRC computation unit functions + * @brief Configuration of the CRC computation unit functions + * +@verbatim + =============================================================================== + ##### CRC configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes CRC peripheral registers to their default reset values. + * @param None + * @retval None + */ +void CRC_DeInit(void) +{ + /* Set DR register to reset value */ + CRC->DR = 0xFFFFFFFF; + /* Reset IDR register */ + CRC->IDR = 0x00; + /* Set INIT register to reset value */ + CRC->INIT = 0xFFFFFFFF; + /* Reset the CRC calculation unit */ + CRC->CR = CRC_CR_RESET; +} + +/** + * @brief Resets the CRC calculation unit and sets INIT register content in DR register. + * @param None + * @retval None + */ +void CRC_ResetDR(void) +{ + /* Reset CRC generator */ + CRC->CR = CRC_CR_RESET; +} + +/** + * @brief Selects the reverse operation to be performed on input data. + * @param CRC_ReverseInputData: Specifies the reverse operation on input data. + * This parameter can be: + * @arg CRC_ReverseInputData_No: No reverse operation is performed + * @arg CRC_ReverseInputData_8bits: reverse operation performed on 8 bits + * @arg CRC_ReverseInputData_16bits: reverse operation performed on 16 bits + * @arg CRC_ReverseInputData_32bits: reverse operation performed on 32 bits + * @retval None + */ +void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData) +{ + uint32_t tmpcr = 0; + + /* Check the parameter */ + assert_param(IS_CRC_REVERSE_INPUT_DATA(CRC_ReverseInputData)); + + /* Get CR register value */ + tmpcr = CRC->CR; + + /* Reset REV_IN bits */ + tmpcr &= (uint32_t)~((uint32_t)CRC_CR_REV_IN); + /* Set the reverse operation */ + tmpcr |= (uint32_t)CRC_ReverseInputData; + + /* Write to CR register */ + CRC->CR = (uint32_t)tmpcr; +} + +/** + * @brief Enables or disable the reverse operation on output data. + * The reverse operation on output data is performed on 32-bit. + * @param NewState: new state of the reverse operation on output data. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CRC_ReverseOutputDataCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable reverse operation on output data */ + CRC->CR |= CRC_CR_REV_OUT; + } + else + { + /* Disable reverse operation on output data */ + CRC->CR &= (uint32_t)~((uint32_t)CRC_CR_REV_OUT); + } +} + +/** + * @brief Initializes the INIT register. + * @note After resetting CRC calculation unit, CRC_InitValue is stored in DR register + * @param CRC_InitValue: Programmable initial CRC value + * @retval None + */ +void CRC_SetInitRegister(uint32_t CRC_InitValue) +{ + CRC->INIT = CRC_InitValue; +} + +/** + * @} + */ + +/** @defgroup CRC_Group2 CRC computation of one/many 32-bit data functions + * @brief CRC computation of one/many 32-bit data functions + * +@verbatim + =============================================================================== + ##### CRC computation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Computes the 32-bit CRC of a given data word(32-bit). + * @param CRC_Data: data word(32-bit) to compute its CRC + * @retval 32-bit CRC + */ +uint32_t CRC_CalcCRC(uint32_t CRC_Data) +{ + CRC->DR = CRC_Data; + + return (CRC->DR); +} + +/** + * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). + * @param pBuffer: pointer to the buffer containing the data to be computed + * @param BufferLength: length of the buffer to be computed + * @retval 32-bit CRC + */ +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; + + for(index = 0; index < BufferLength; index++) + { + CRC->DR = pBuffer[index]; + } + return (CRC->DR); +} + +/** + * @brief Returns the current CRC value. + * @param None + * @retval 32-bit CRC + */ +uint32_t CRC_GetCRC(void) +{ + return (CRC->DR); +} + +/** + * @} + */ + +/** @defgroup CRC_Group3 CRC Independent Register (IDR) access functions + * @brief CRC Independent Register (IDR) access (write/read) functions + * +@verbatim + =============================================================================== + ##### CRC Independent Register (IDR) access functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Stores an 8-bit data in the Independent Data(ID) register. + * @param CRC_IDValue: 8-bit value to be stored in the ID register + * @retval None + */ +void CRC_SetIDRegister(uint8_t CRC_IDValue) +{ + CRC->IDR = CRC_IDValue; +} + +/** + * @brief Returns the 8-bit data stored in the Independent Data(ID) register + * @param None + * @retval 8-bit value of the ID register + */ +uint8_t CRC_GetIDRegister(void) +{ + return (CRC->IDR); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_dac.c b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_dac.c new file mode 100644 index 0000000..01a4f00 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_dac.c @@ -0,0 +1,537 @@ +/** + ****************************************************************************** + * @file stm32f0xx_dac.c + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Digital-to-Analog Converter (DAC) peripheral: + * + DAC channel configuration: trigger, output buffer, data format + * + DMA management + * + Interrupts and flags management + * + * @verbatim + * + =============================================================================== + ##### DAC Peripheral features ##### + =============================================================================== + [..] The device integrates one 12-bit Digital Analog Converters refered as + DAC channel1 with DAC_OUT1 (PA4) as output + + [..] Digital to Analog conversion can be non-triggered using DAC_Trigger_None + and DAC_OUT1 is available once writing to DHRx register using + DAC_SetChannel1Data(). + + [..] Digital to Analog conversion can be triggered by: + (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9. + The used pin (GPIOx_Pin9) must be configured in input mode. + + (#) Timers TRGO: TIM2, TIM3, TIM6 and TIM15 + (DAC_Trigger_T2_TRGO, DAC_Trigger_T3_TRGO...) + The timer TRGO event should be selected using TIM_SelectOutputTrigger() + + (#) Software using DAC_Trigger_Software + + [..] The DAC channel 1 integrates an output buffer that can be used to + reduce the output impedance, and to drive external loads directly + without having to add an external operational amplifier. + To enable the output buffer use + DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable; + + [..] Refer to the device datasheet for more details about output impedance + value with and without output buffer. + + [..] The DAC data format can be: + (#) 8-bit right alignment using DAC_Align_8b_R + (#) 12-bit left alignment using DAC_Align_12b_L + (#) 12-bit right alignment using DAC_Align_12b_R + + [..] The analog output voltage on each DAC channel pin is determined + by the following equation: DAC_OUTx = VREF+ * DOR / 4095 + with DOR is the Data Output Register + VEF+ is the input voltage reference (refer to the device datasheet) + e.g. To set DAC_OUT1 to 0.7V, use + DAC_SetChannel1Data(DAC_Align_12b_R, 868); + Assuming that VREF+ = 3.3, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V + + [..] A DMA1 request can be generated when an external trigger (but not + a software trigger) occurs if DMA1 requests are enabled using + DAC_DMACmd() + DMA1 requests are mapped as following: + (+) DAC channel1 is mapped on DMA1 channel3 which must be already + configured + + ##### How to use this driver ##### + =============================================================================== + [..] + (+) Enable DAC APB1 clock to get write access to DAC registers + using RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE) + + (+) Configure DAC_OUT1 (DAC_OUT1: PA4) in analog mode + using GPIO_Init() function + + (+) Configure the DAC channel using DAC_Init() + + (+) Enable the DAC channel using DAC_Cmd() + + @endverbatim + * + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_dac.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup DAC + * @brief DAC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* CR register Mask */ +#define CR_CLEAR_MASK ((uint32_t)0x0000003E) + +/* DHR registers offsets */ +#define DHR12R1_OFFSET ((uint32_t)0x00000008) + +/* DOR register offset */ +#define DOR_OFFSET ((uint32_t)0x0000002C) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup DAC_Private_Functions + * @{ + */ + +/** @defgroup DAC_Group1 DAC channels configuration + * @brief DAC channels configuration: trigger, output buffer, data format + * +@verbatim + =============================================================================== + ##### DAC channels configuration: trigger, output buffer, data format ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the DAC peripheral registers to their default reset values. + * @param None + * @retval None + */ +void DAC_DeInit(void) +{ + /* Enable DAC reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); + /* Release DAC from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); +} + +/** + * @brief Initializes the DAC peripheral according to the specified + * parameters in the DAC_InitStruct. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that + * contains the configuration information for the specified DAC channel. + * + * @retval None + */ +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + + /* Check the DAC parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger)); + assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer)); + + /*---------------------------- DAC CR Configuration ------------------------*/ + /* Get the DAC CR value */ + tmpreg1 = DAC->CR; + + /* Clear BOFFx, TENx, TSELx bits */ + tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel); + + /* Configure for the selected DAC channel: buffer output, trigger */ + /* Set TSELx and TENx bits according to DAC_Trigger value */ + /* Set BOFFx bit according to DAC_OutputBuffer value */ + tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_OutputBuffer); + + /* Calculate CR register value depending on DAC_Channel */ + tmpreg1 |= tmpreg2 << DAC_Channel; + + /* Write to DAC CR */ + DAC->CR = tmpreg1; +} + +/** + * @brief Fills each DAC_InitStruct member with its default value. + * @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) +{ +/*--------------- Reset DAC init structure parameters values -----------------*/ + /* Initialize the DAC_Trigger member */ + DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; + /* Initialize the DAC_OutputBuffer member */ + DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; +} + +/** + * @brief Enables or disables the specified DAC channel. + * @param DAC_Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @param NewState: new state of the DAC channel. + * This parameter can be: ENABLE or DISABLE. + * @note When the DAC channel is enabled the trigger source can no more + * be modified. + * @retval None + */ +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DAC channel */ + DAC->CR |= (DAC_CR_EN1 << DAC_Channel); + } + else + { + /* Disable the selected DAC channel */ + DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel)); + } +} + +/** + * @brief Enables or disables the selected DAC channel software trigger. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @param NewState: new state of the selected DAC channel software trigger. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable software trigger for the selected DAC channel */ + DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4); + } + else + { + /* Disable software trigger for the selected DAC channel */ + DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4)); + } +} + +/** + * @brief Set the specified data holding register value for DAC channel1. + * @param DAC_Align: Specifies the data alignment for DAC channel1. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignment selected + * @arg DAC_Align_12b_L: 12bit left data alignment selected + * @arg DAC_Align_12b_R: 12bit right data alignment selected + * @param Data : Data to be loaded in the selected data holding register. + * @retval None + */ +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12R1_OFFSET + DAC_Align; + + /* Set the DAC channel1 selected data holding register */ + *(__IO uint32_t *) tmp = Data; +} + +/** + * @brief Returns the last data output value of the selected DAC channel. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @retval The selected DAC channel data output value. + */ +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + + tmp = (uint32_t) DAC_BASE ; + tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2); + + /* Returns the DAC channel data output register value */ + return (uint16_t) (*(__IO uint32_t*) tmp); +} + +/** + * @} + */ + +/** @defgroup DAC_Group2 DMA management functions + * @brief DMA management functions + * +@verbatim + =============================================================================== + ##### DMA management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified DAC channel DMA request. + * When enabled DMA1 is generated when an external trigger (EXTI Line9, + * TIM2, TIM3, TIM6 or TIM15 but not a software trigger) occurs + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @param NewState: new state of the selected DAC channel DMA request. + * This parameter can be: ENABLE or DISABLE. + * The DAC channel1 is mapped on DMA1 channel3 which must be already configured. + * @retval None + */ +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DAC channel DMA request */ + DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel); + } + else + { + /* Disable the selected DAC channel DMA request */ + DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel)); + } +} + +/** + * @} + */ + +/** @defgroup DAC_Group3 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified DAC interrupts. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @note The DMA underrun occurs when a second external trigger arrives before + * the acknowledgement for the first external trigger is received (first request). + * @param NewState: new state of the specified DAC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_DAC_IT(DAC_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected DAC interrupts */ + DAC->CR |= (DAC_IT << DAC_Channel); + } + else + { + /* Disable the selected DAC interrupts */ + DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel)); + } +} + +/** + * @brief Checks whether the specified DAC flag is set or not. + * @param DAC_Channel: thee selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @param DAC_FLAG: specifies the flag to check. + * This parameter can be only of the following value: + * @arg DAC_FLAG_DMAUDR: DMA underrun flag + * @note The DMA underrun occurs when a second external trigger arrives before + * the acknowledgement for the first external trigger is received (first request). + * @retval The new state of DAC_FLAG (SET or RESET). + */ +FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_FLAG(DAC_FLAG)); + + /* Check the status of the specified DAC flag */ + if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET) + { + /* DAC_FLAG is set */ + bitstatus = SET; + } + else + { + /* DAC_FLAG is reset */ + bitstatus = RESET; + } + /* Return the DAC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the DAC channel's pending flags. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @param DAC_FLAG: specifies the flag to clear. + * This parameter can be of the following value: + * @arg DAC_FLAG_DMAUDR: DMA underrun flag + * @retval None + */ +void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_FLAG(DAC_FLAG)); + + /* Clear the selected DAC flags */ + DAC->SR = (DAC_FLAG << DAC_Channel); +} + +/** + * @brief Checks whether the specified DAC interrupt has occurred or not. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @param DAC_IT: specifies the DAC interrupt source to check. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @note The DMA underrun occurs when a second external trigger arrives before + * the acknowledgement for the first external trigger is received (first request). + * @retval The new state of DAC_IT (SET or RESET). + */ +ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_IT(DAC_IT)); + + /* Get the DAC_IT enable bit status */ + enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ; + + /* Check the status of the specified DAC interrupt */ + if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus) + { + /* DAC_IT is set */ + bitstatus = SET; + } + else + { + /* DAC_IT is reset */ + bitstatus = RESET; + } + /* Return the DAC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the DAC channel's interrupt pending bits. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @param DAC_IT: specifies the DAC interrupt pending bit to clear. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @retval None + */ +void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_IT(DAC_IT)); + + /* Clear the selected DAC interrupt pending bits */ + DAC->SR = (DAC_IT << DAC_Channel); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_dbgmcu.c b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_dbgmcu.c new file mode 100644 index 0000000..1685de9 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_dbgmcu.c @@ -0,0 +1,213 @@ +/** + ****************************************************************************** + * @file stm32f0xx_dbgmcu.c + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Debug MCU (DBGMCU) peripheral: + * + Device and Revision ID management + * + Peripherals Configuration + * @verbatim + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_dbgmcu.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup DBGMCU + * @brief DBGMCU driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup DBGMCU_Private_Functions + * @{ + */ + + +/** @defgroup DBGMCU_Group1 Device and Revision ID management functions + * @brief Device and Revision ID management functions + * +@verbatim + ============================================================================== + ##### Device and Revision ID management functions ##### + ============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Returns the device revision identifier. + * @param None + * @retval Device revision identifier + */ +uint32_t DBGMCU_GetREVID(void) +{ + return(DBGMCU->IDCODE >> 16); +} + +/** + * @brief Returns the device identifier. + * @param None + * @retval Device identifier + */ +uint32_t DBGMCU_GetDEVID(void) +{ + return(DBGMCU->IDCODE & IDCODE_DEVID_MASK); +} + +/** + * @} + */ + +/** @defgroup DBGMCU_Group2 Peripherals Configuration functions + * @brief Peripherals Configuration + * +@verbatim + ============================================================================== + ##### Peripherals Configuration functions ##### + ============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures low power mode behavior when the MCU is in Debug mode. + * @param DBGMCU_Periph: specifies the low power mode. + * This parameter can be any combination of the following values: + * @arg DBGMCU_STOP: Keep debugger connection during STOP mode + * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode + * @param NewState: new state of the specified low power mode in Debug mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + DBGMCU->CR |= DBGMCU_Periph; + } + else + { + DBGMCU->CR &= ~DBGMCU_Periph; + } +} + + +/** + * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode. + * @param DBGMCU_Periph: specifies the APB1 peripheral. + * This parameter can be any combination of the following values: + * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted + * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted + * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted + * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted + * @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter stopped + * when Core is halted. + * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted + * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted + * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped + * when Core is halted + * @param NewState: new state of the specified APB1 peripheral in Debug mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + DBGMCU->APB1FZ |= DBGMCU_Periph; + } + else + { + DBGMCU->APB1FZ &= ~DBGMCU_Periph; + } +} + +/** + * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode. + * @param DBGMCU_Periph: specifies the APB2 peripheral. + * This parameter can be any combination of the following values: + * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted + * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted + * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted + * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted + * @param NewState: new state of the specified APB2 peripheral in Debug mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + DBGMCU->APB2FZ |= DBGMCU_Periph; + } + else + { + DBGMCU->APB2FZ &= ~DBGMCU_Periph; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_dma.c b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_dma.c new file mode 100644 index 0000000..33da6ec --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_dma.c @@ -0,0 +1,660 @@ +/** + ****************************************************************************** + * @file stm32f0xx_dma.c + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access controller (DMA): + * + Initialization and Configuration + * + Data Counter + * + Interrupts and flags management + * + * @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable The DMA controller clock using + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE) function for DMA1. + (#) Enable and configure the peripheral to be connected to the DMA channel + (except for internal SRAM / FLASH memories: no initialization is necessary). + (#) For a given Channel, program the Source and Destination addresses, + the transfer Direction, the Buffer Size, the Peripheral and Memory + Incrementation mode and Data Size, the Circular or Normal mode, + the channel transfer Priority and the Memory-to-Memory transfer + mode (if needed) using the DMA_Init() function. + (#) Enable the NVIC and the corresponding interrupt(s) using the function + DMA_ITConfig() if you need to use DMA interrupts. + (#) Enable the DMA channel using the DMA_Cmd() function. + (#) Activate the needed channel Request using PPP_DMACmd() function for + any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...) + The function allowing this operation is provided in each PPP peripheral + driver (ie. SPI_DMACmd for SPI peripheral). + (#) Optionally, you can configure the number of data to be transferred + when the channel is disabled (ie. after each Transfer Complete event + or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter(). + And you can get the number of remaining data to be transferred using + the function DMA_GetCurrDataCounter() at run time (when the DMA channel is + enabled and running). + (#) To control DMA events you can use one of the following two methods: + (##) Check on DMA channel flags using the function DMA_GetFlagStatus(). + (##) Use DMA interrupts through the function DMA_ITConfig() at initialization + phase and DMA_GetITStatus() function into interrupt routines in + communication phase. + After checking on a flag you should clear it using DMA_ClearFlag() + function. And after checking on an interrupt event you should + clear it using DMA_ClearITPendingBit() function. + @endverbatim + * + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_dma.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup DMA + * @brief DMA driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define CCR_CLEAR_MASK ((uint32_t)0xFFFF800F) /* DMA Channel config registers Masks */ + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1)) +#define DMA1_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2)) +#define DMA1_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3)) +#define DMA1_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4)) +#define DMA1_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5)) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup DMA_Private_Functions + * @{ + */ + +/** @defgroup DMA_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This subsection provides functions allowing to initialize the DMA channel + source and destination addresses, incrementation and data sizes, transfer + direction, buffer size, circular/normal mode selection, memory-to-memory + mode selection and channel priority value. + [..] The DMA_Init() function follows the DMA configuration procedures as described + in reference manual (RM0091). +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the DMAy Channelx registers to their default reset + * values. + * @param DMAy_Channelx: where y can be 1 to select the DMA and + * x can be 1 to 5 for DMA1 to select the DMA Channel. + * @retval None + */ +void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + + /* Disable the selected DMAy Channelx */ + DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN); + + /* Reset DMAy Channelx control register */ + DMAy_Channelx->CCR = 0; + + /* Reset DMAy Channelx remaining bytes register */ + DMAy_Channelx->CNDTR = 0; + + /* Reset DMAy Channelx peripheral address register */ + DMAy_Channelx->CPAR = 0; + + /* Reset DMAy Channelx memory address register */ + DMAy_Channelx->CMAR = 0; + + if (DMAy_Channelx == DMA1_Channel1) + { + /* Reset interrupt pending bits for DMA1 Channel1 */ + DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK; + } + else if (DMAy_Channelx == DMA1_Channel2) + { + /* Reset interrupt pending bits for DMA1 Channel2 */ + DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK; + } + else if (DMAy_Channelx == DMA1_Channel3) + { + /* Reset interrupt pending bits for DMA1 Channel3 */ + DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK; + } + else if (DMAy_Channelx == DMA1_Channel4) + { + /* Reset interrupt pending bits for DMA1 Channel4 */ + DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK; + } + else + { + if (DMAy_Channelx == DMA1_Channel5) + { + /* Reset interrupt pending bits for DMA1 Channel5 */ + DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK; + } + } +} + +/** + * @brief Initializes the DMAy Channelx according to the specified parameters + * in the DMA_InitStruct. + * @param DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 5 + * for DMA1 to select the DMA Channel. + * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval None + */ +void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR)); + assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); + assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); + assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); + assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M)); + +/*--------------------------- DMAy Channelx CCR Configuration ----------------*/ + /* Get the DMAy_Channelx CCR value */ + tmpreg = DMAy_Channelx->CCR; + + /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ + tmpreg &= CCR_CLEAR_MASK; + + /* Configure DMAy Channelx: data transfer, data size, priority level and mode */ + /* Set DIR bit according to DMA_DIR value */ + /* Set CIRC bit according to DMA_Mode value */ + /* Set PINC bit according to DMA_PeripheralInc value */ + /* Set MINC bit according to DMA_MemoryInc value */ + /* Set PSIZE bits according to DMA_PeripheralDataSize value */ + /* Set MSIZE bits according to DMA_MemoryDataSize value */ + /* Set PL bits according to DMA_Priority value */ + /* Set the MEM2MEM bit according to DMA_M2M value */ + tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | + DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | + DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | + DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; + + /* Write to DMAy Channelx CCR */ + DMAy_Channelx->CCR = tmpreg; + +/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/ + /* Write to DMAy Channelx CNDTR */ + DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize; + +/*--------------------------- DMAy Channelx CPAR Configuration ---------------*/ + /* Write to DMAy Channelx CPAR */ + DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr; + +/*--------------------------- DMAy Channelx CMAR Configuration ---------------*/ + /* Write to DMAy Channelx CMAR */ + DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr; +} + +/** + * @brief Fills each DMA_InitStruct member with its default value. + * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) +{ +/*-------------- Reset DMA init structure parameters values ------------------*/ + /* Initialize the DMA_PeripheralBaseAddr member */ + DMA_InitStruct->DMA_PeripheralBaseAddr = 0; + /* Initialize the DMA_MemoryBaseAddr member */ + DMA_InitStruct->DMA_MemoryBaseAddr = 0; + /* Initialize the DMA_DIR member */ + DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; + /* Initialize the DMA_BufferSize member */ + DMA_InitStruct->DMA_BufferSize = 0; + /* Initialize the DMA_PeripheralInc member */ + DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + /* Initialize the DMA_MemoryInc member */ + DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; + /* Initialize the DMA_PeripheralDataSize member */ + DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + /* Initialize the DMA_MemoryDataSize member */ + DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + /* Initialize the DMA_Mode member */ + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + /* Initialize the DMA_Priority member */ + DMA_InitStruct->DMA_Priority = DMA_Priority_Low; + /* Initialize the DMA_M2M member */ + DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; +} + +/** + * @brief Enables or disables the specified DMAy Channelx. + * @param DMAy_Channelx: where y can be 1 to select the DMA and + * x can be 1 to 5 for DMA1 to select the DMA Channel. + * @param NewState: new state of the DMAy Channelx. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMAy Channelx */ + DMAy_Channelx->CCR |= DMA_CCR_EN; + } + else + { + /* Disable the selected DMAy Channelx */ + DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN); + } +} + +/** + * @} + */ + +/** @defgroup DMA_Group2 Data Counter functions + * @brief Data Counter functions + * +@verbatim + =============================================================================== + ##### Data Counter functions ##### + =============================================================================== + [..] This subsection provides function allowing to configure and read the buffer + size (number of data to be transferred).The DMA data counter can be written + only when the DMA channel is disabled (ie. after transfer complete event). + [..] The following function can be used to write the Channel data counter value: + (+) void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t + DataNumber). + -@- It is advised to use this function rather than DMA_Init() in situations + where only the Data buffer needs to be reloaded. + [..] The DMA data counter can be read to indicate the number of remaining transfers + for the relative DMA channel. This counter is decremented at the end of each + data transfer and when the transfer is complete: + (+) If Normal mode is selected: the counter is set to 0. + (+) If Circular mode is selected: the counter is reloaded with the initial + value(configured before enabling the DMA channel). + [..] The following function can be used to read the Channel data counter value: + (+) uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx). + +@endverbatim + * @{ + */ + +/** + * @brief Sets the number of data units in the current DMAy Channelx transfer. + * @param DMAy_Channelx: where y can be 1 to select the DMA and x can be + * 1 to 5 for DMA1 to select the DMA Channel. + * @param DataNumber: The number of data units in the current DMAy Channelx + * transfer. + * @note This function can only be used when the DMAy_Channelx is disabled. + * @retval None. + */ +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + +/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/ + /* Write to DMAy Channelx CNDTR */ + DMAy_Channelx->CNDTR = DataNumber; +} + +/** + * @brief Returns the number of remaining data units in the current + * DMAy Channelx transfer. + * @param DMAy_Channelx: where y can be 1 to select the DMA and + * x can be 1 to 5 for DMA1 to select the DMA Channel. + * @retval The number of remaining data units in the current DMAy Channelx + * transfer. + */ +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + /* Return the number of remaining data units for DMAy Channelx */ + return ((uint16_t)(DMAy_Channelx->CNDTR)); +} + +/** + * @} + */ + +/** @defgroup DMA_Group3 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + [..] This subsection provides functions allowing to configure the DMA Interrupts + sources and check or clear the flags or pending bits status. + The user should identify which mode will be used in his application to manage + the DMA controller events: Polling mode or Interrupt mode. + *** Polling Mode *** + ==================== + [..] Each DMA channel can be managed through 4 event Flags:(y : DMA Controller + number x : DMA channel number ). + (#) DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred. + (#) DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occurred. + (#) DMAy_FLAG_TEx : to indicate that a Transfer Error occurred. + (#) DMAy_FLAG_GLx : to indicate that at least one of the events described + above occurred. + -@- Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the + same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx). + [..]In this Mode it is advised to use the following functions: + (+) FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG); + (+) void DMA_ClearFlag(uint32_t DMA_FLAG); + + *** Interrupt Mode *** + ====================== + [..] Each DMA channel can be managed through 4 Interrupts: + (+) Interrupt Source + (##) DMA_IT_TC: specifies the interrupt source for the Transfer Complete + event. + (##) DMA_IT_HT : specifies the interrupt source for the Half-transfer Complete + event. + (##) DMA_IT_TE : specifies the interrupt source for the transfer errors event. + (##) DMA_IT_GL : to indicate that at least one of the interrupts described + above occurred. + -@@- Clearing DMA_IT_GL interrupt results in clearing all other interrupts of + the same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE). + [..]In this Mode it is advised to use the following functions: + (+) void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, + FunctionalState NewState); + (+) ITStatus DMA_GetITStatus(uint32_t DMA_IT); + (+) void DMA_ClearITPendingBit(uint32_t DMA_IT); + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified DMAy Channelx interrupts. + * @param DMAy_Channelx: where y can be 1 to select the DMA and + * x can be 1 to 5 for DMA1 to select the DMA Channel. + * @param DMA_IT: specifies the DMA interrupts sources to be enabled + * or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @param NewState: new state of the specified DMA interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_DMA_CONFIG_IT(DMA_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA interrupts */ + DMAy_Channelx->CCR |= DMA_IT; + } + else + { + /* Disable the selected DMA interrupts */ + DMAy_Channelx->CCR &= ~DMA_IT; + } +} + +/** + * @brief Checks whether the specified DMAy Channelx flag is set or not. + * @param DMA_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. + * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. + * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. + * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. + * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. + * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. + * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. + * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. + * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. + * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. + * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. + * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. + * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. + * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. + * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. + * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. + * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. + * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. + * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. + * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. + * + * @note + * The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags + * relative to the same channel is set (Transfer Complete, Half-transfer + * Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or + * DMAy_FLAG_TEx). + * + * @retval The new state of DMA_FLAG (SET or RESET). + */ +FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_DMA_GET_FLAG(DMA_FLAG)); + + /* Check the status of the specified DMA flag */ + if ((DMA1->ISR & DMA_FLAG) != (uint32_t)RESET) + { + /* DMA_FLAG is set */ + bitstatus = SET; + } + else + { + /* DMA_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the DMA_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the DMAy Channelx's pending flags. + * @param DMA_FLAG: specifies the flag to clear. + * This parameter can be any combination (for the same DMA) of the following values: + * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. + * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. + * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. + * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. + * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. + * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. + * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. + * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. + * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. + * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. + * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. + * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. + * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. + * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. + * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. + * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. + * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. + * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. + * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. + * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. + * + * @note + * Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags + * relative to the same channel (Transfer Complete, Half-transfer Complete and + * Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx). + * + * @retval None + */ +void DMA_ClearFlag(uint32_t DMA_FLAG) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG)); + + /* Clear the selected DMA flags */ + DMA1->IFCR = DMA_FLAG; +} + +/** + * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not. + * @param DMA_IT: specifies the DMA interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. + * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. + * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. + * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. + * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. + * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. + * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. + * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. + * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. + * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. + * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. + * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. + * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. + * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. + * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. + * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. + * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. + * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. + * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. + * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. + * + * @note + * The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other + * interrupts relative to the same channel is set (Transfer Complete, + * Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx, + * DMAy_IT_HTx or DMAy_IT_TEx). + * + * @retval The new state of DMA_IT (SET or RESET). + */ +ITStatus DMA_GetITStatus(uint32_t DMA_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_DMA_GET_IT(DMA_IT)); + + /* Check the status of the specified DMA interrupt */ + if ((DMA1->ISR & DMA_IT) != (uint32_t)RESET) + { + /* DMA_IT is set */ + bitstatus = SET; + } + else + { + /* DMA_IT is reset */ + bitstatus = RESET; + } + /* Return the DMA_IT status */ + return bitstatus; +} + +/** + * @brief Clears the DMAy Channelx's interrupt pending bits. + * @param DMA_IT: specifies the DMA interrupt pending bit to clear. + * This parameter can be any combination (for the same DMA) of the following values: + * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. + * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. + * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. + * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. + * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. + * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. + * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. + * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. + * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. + * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. + * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. + * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. + * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. + * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. + * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. + * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. + * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. + * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. + * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. + * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. + * + * @note + * Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other + * interrupts relative to the same channel (Transfer Complete, Half-transfer + * Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and + * DMAy_IT_TEx). + * + * @retval None + */ +void DMA_ClearITPendingBit(uint32_t DMA_IT) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLEAR_IT(DMA_IT)); + + /* Clear the selected DMA interrupt pending bits */ + DMA1->IFCR = DMA_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_exti.c b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_exti.c new file mode 100644 index 0000000..d6a5bcf --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_exti.c @@ -0,0 +1,319 @@ +/** + ****************************************************************************** + * @file stm32f0xx_exti.c + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the EXTI peripheral: + * + Initialization and Configuration + * + Interrupts and flags management + * + * @verbatim + ============================================================================== + ##### EXTI features ##### + ============================================================================== + [..] External interrupt/event lines are mapped as following: + (#) All available GPIO pins are connected to the 16 external + interrupt/event lines from EXTI0 to EXTI15. + (#) EXTI line 16 is connected to the PVD output. + (#) EXTI line 17 is connected to the RTC Alarm event. + (#) EXTI line 19 is connected to the RTC Tamper and TimeStamp events + (#) EXTI line 21 is connected to the Comparator 1 wakeup event + (#) EXTI line 22 is connected to the Comparator 2 wakeup event + (#) EXTI line 23 is connected to the I2C1 wakeup event + (#) EXTI line 25 is connected to the USART1 wakeup event + (#) EXTI line 27 is connected to the CEC wakeup event + + ##### How to use this driver ##### + ============================================================================== + [..] In order to use an I/O pin as an external interrupt source, follow + steps below: + (#) Configure the I/O in input mode using GPIO_Init() + (#) Select the input source pin for the EXTI line using + SYSCFG_EXTILineConfig(). + (#) Select the mode(interrupt, event) and configure the trigger selection + (Rising, falling or both) using EXTI_Init(). For the internal interrupt, + the trigger selection is not needed( the active edge is always the rising one). + (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init(). + (#) Optionally, you can generate a software interrupt using the function EXTI_GenerateSWInterrupt(). + [..] + (@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx + registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); + @endverbatim + * + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_exti.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup EXTI + * @brief EXTI driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup EXTI_Private_Functions + * @{ + */ + +/** @defgroup EXTI_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and Configuration functions ##### + ============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the EXTI peripheral registers to their default reset + * values. + * @param None + * @retval None + */ +void EXTI_DeInit(void) +{ + EXTI->IMR = 0x0F940000; + EXTI->EMR = 0x00000000; + EXTI->RTSR = 0x00000000; + EXTI->FTSR = 0x00000000; + EXTI->PR = 0x006BFFFF; +} + +/** + * @brief Initializes the EXTI peripheral according to the specified + * parameters in the EXTI_InitStruct. + * EXTI_Line specifies the EXTI line (EXTI0....EXTI27). + * EXTI_Mode specifies which EXTI line is used as interrupt or an event. + * EXTI_Trigger selects the trigger. When the trigger occurs, interrupt + * pending bit will be set. + * EXTI_LineCmd controls (Enable/Disable) the EXTI line. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure that + * contains the configuration information for the EXTI peripheral. + * @retval None + */ +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) +{ + uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); + assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); + assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); + assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); + + tmp = (uint32_t)EXTI_BASE; + + if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + /* Clear EXTI line configuration */ + EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; + + tmp += EXTI_InitStruct->EXTI_Mode; + + *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; + + /* Select the trigger for the selected interrupts */ + if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + /* Rising Falling edge */ + EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; + EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; + } + else + { + tmp = (uint32_t)EXTI_BASE; + tmp += EXTI_InitStruct->EXTI_Trigger; + + *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; + } + } + else + { + tmp += EXTI_InitStruct->EXTI_Mode; + + /* Disable the selected external lines */ + *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; + } +} + +/** + * @brief Fills each EXTI_InitStruct member with its reset value. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/** + * @brief Generates a Software interrupt on selected EXTI line. + * @param EXTI_Line: specifies the EXTI line on which the software interrupt + * will be generated. + * This parameter can be any combination of EXTI_Linex where x can be (0..19) + * @retval None + */ +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->SWIER |= EXTI_Line; +} + +/** + * @} + */ + +/** @defgroup EXTI_Group2 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + ============================================================================== + ##### Interrupts and flags management functions ##### + ============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param EXTI_Line: specifies the EXTI line flag to check. + * This parameter can be: + * EXTI_Linex: External interrupt line x where x(0..19). + * @retval The new state of EXTI_Line (SET or RESET). + */ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the EXTI's line pending flags. + * @param EXTI_Line: specifies the EXTI lines flags to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..19) + * @retval None + */ +void EXTI_ClearFlag(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/** + * @brief Checks whether the specified EXTI line is asserted or not. + * @param EXTI_Line: specifies the EXTI line to check. + * This parameter can be: + * EXTI_Linex: External interrupt line x where x(0..19). + * @retval The new state of EXTI_Line (SET or RESET). + */ +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + enablestatus = EXTI->IMR & EXTI_Line; + if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; + +} + +/** + * @brief Clears the EXTI's line pending bits. + * @param EXTI_Line: specifies the EXTI lines to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..19). + * @retval None + */ +void EXTI_ClearITPendingBit(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_flash.c b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_flash.c new file mode 100644 index 0000000..f2dc9f4 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_flash.c @@ -0,0 +1,1170 @@ +/** + ****************************************************************************** + * @file stm32f0xx_flash.c + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the FLASH peripheral: + * - FLASH Interface configuration + * - FLASH Memory Programming + * - Option Bytes Programming + * - Interrupts and flags management + * + * @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] This driver provides functions to configure and program the Flash + memory of all STM32F0xx devices. These functions are split in 4 groups + (#) FLASH Interface configuration functions: this group includes the + management of following features: + (++) Set the latency + (++) Enable/Disable the prefetch buffer + + (#) FLASH Memory Programming functions: this group includes all needed + functions to erase and program the main memory: + (++) Lock and Unlock the Flash interface. + (++) Erase function: Erase Page, erase all pages. + (++) Program functions: Half Word and Word write. + + (#) FLASH Option Bytes Programming functions: this group includes all + needed functions to: + (++) Lock and Unlock the Flash Option bytes. + (++) Launch the Option Bytes loader + (++) Erase the Option Bytes + (++)Set/Reset the write protection + (++) Set the Read protection Level + (++) Program the user option Bytes + (++) Set/Reset the BOOT1 bit + (++) Enable/Disable the VDDA Analog Monitoring + (++) Get the user option bytes + (++) Get the Write protection + (++) Get the read protection status + + (#) FLASH Interrupts and flag management functions: this group includes + all needed functions to: + (++) Enable/Disable the flash interrupt sources + (++) Get flags status + (++) Clear flags + (++) Get Flash operation status + (++) Wait for last flash operation + + @endverbatim + + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_flash.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup FLASH + * @brief FLASH driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + /* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup FLASH_Private_Functions + * @{ + */ + +/** @defgroup FLASH_Group1 FLASH Interface configuration functions + * @brief FLASH Interface configuration functions + * +@verbatim + =============================================================================== + ##### FLASH Interface configuration functions ##### + =============================================================================== + + [..] FLASH_Interface configuration_Functions, includes the following functions: + (+) void FLASH_SetLatency(uint32_t FLASH_Latency): + [..] To correctly read data from Flash memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock (HCLK) + [..] + +--------------------------------------------- + + | Wait states | HCLK clock frequency (MHz) | + |---------------|------------------------------| + |0WS(1CPU cycle)| 0 < HCLK <= 24 | + |---------------|------------------------------| + |1WS(2CPU cycle)| 24 < HCLK <= 48 | + +----------------------------------------------+ + [..] + (+) void FLASH_PrefetchBufferCmd(FunctionalState NewState); + [..] + All these functions don't need the unlock sequence. + +@endverbatim + * @{ + */ + +/** + * @brief Sets the code latency value. + * @param FLASH_Latency: specifies the FLASH Latency value. + * This parameter can be one of the following values: + * @arg FLASH_Latency_0: FLASH Zero Latency cycle + * @arg FLASH_Latency_1: FLASH One Latency cycle + * @retval None + */ +void FLASH_SetLatency(uint32_t FLASH_Latency) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_FLASH_LATENCY(FLASH_Latency)); + + /* Read the ACR register */ + tmpreg = FLASH->ACR; + + /* Sets the Latency value */ + tmpreg &= (uint32_t) (~((uint32_t)FLASH_ACR_LATENCY)); + tmpreg |= FLASH_Latency; + + /* Write the ACR register */ + FLASH->ACR = tmpreg; +} + +/** + * @brief Enables or disables the Prefetch Buffer. + * @param NewState: new state of the FLASH prefetch buffer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FLASH_PrefetchBufferCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if(NewState != DISABLE) + { + FLASH->ACR |= FLASH_ACR_PRFTBE; + } + else + { + FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_PRFTBE)); + } +} + +/** + * @brief Checks whether the FLASH Prefetch Buffer status is set or not. + * @param None + * @retval FLASH Prefetch Buffer Status (SET or RESET). + */ +FlagStatus FLASH_GetPrefetchBufferStatus(void) +{ + FlagStatus bitstatus = RESET; + + if ((FLASH->ACR & FLASH_ACR_PRFTBS) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */ + return bitstatus; +} + +/** + * @} + */ + +/** @defgroup FLASH_Group2 FLASH Memory Programming functions + * @brief FLASH Memory Programming functions + * +@verbatim + =============================================================================== + ##### FLASH Memory Programming functions ##### + =============================================================================== + + [..] The FLASH Memory Programming functions, includes the following functions: + (+) void FLASH_Unlock(void); + (+) void FLASH_Lock(void); + (+) FLASH_Status FLASH_ErasePage(uint32_t Page_Address); + (+) FLASH_Status FLASH_EraseAllPages(void); + (+) FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); + (+) FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); + + [..] Any operation of erase or program should follow these steps: + + (#) Call the FLASH_Unlock() function to enable the flash control register and + program memory access + (#) Call the desired function to erase page or program data + (#) Call the FLASH_Lock() to disable the flash program memory access + (recommended to protect the FLASH memory against possible unwanted operation) + +@endverbatim + * @{ + */ + +/** + * @brief Unlocks the FLASH control register and program memory access. + * @param None + * @retval None + */ +void FLASH_Unlock(void) +{ + if((FLASH->CR & FLASH_CR_LOCK) != RESET) + { + /* Unlocking the program memory access */ + FLASH->KEYR = FLASH_FKEY1; + FLASH->KEYR = FLASH_FKEY2; + } +} + +/** + * @brief Locks the Program memory access. + * @param None + * @retval None + */ +void FLASH_Lock(void) +{ + /* Set the LOCK Bit to lock the FLASH control register and program memory access */ + FLASH->CR |= FLASH_CR_LOCK; +} + +/** + * @brief Erases a specified page in program memory. + * @note To correctly run this function, the FLASH_Unlock() function + * must be called before. + * Call the FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation) + * @param Page_Address: The page address in program memory to be erased. + * @note A Page is erased in the Program memory only if the address to load + * is the start address of a page (multiple of 1024 bytes). + * @retval FLASH Status: The returned value can be: + * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ErasePage(uint32_t Page_Address) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(Page_Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status == FLASH_COMPLETE) + { + /* If the previous operation is completed, proceed to erase the page */ + FLASH->CR |= FLASH_CR_PER; + FLASH->AR = Page_Address; + FLASH->CR |= FLASH_CR_STRT; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + /* Disable the PER Bit */ + FLASH->CR &= ~FLASH_CR_PER; + } + + /* Return the Erase Status */ + return status; +} + +/** + * @brief Erases all FLASH pages. + * @note To correctly run this function, the FLASH_Unlock() function + * must be called before. + * Call the FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation) + * @param None + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllPages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CR |= FLASH_CR_MER; + FLASH->CR |= FLASH_CR_STRT; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + /* Disable the MER Bit */ + FLASH->CR &= ~FLASH_CR_MER; + } + + /* Return the Erase Status */ + return status; +} + +/** + * @brief Programs a word at a specified address. + * @note To correctly run this function, the FLASH_Unlock() function + * must be called before. + * Call the FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation) + * @param Address: specifies the address to be programmed. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status == FLASH_COMPLETE) + { + /* If the previous operation is completed, proceed to program the new first + half word */ + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint16_t*)Address = (uint16_t)Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status == FLASH_COMPLETE) + { + /* If the previous operation is completed, proceed to program the new second + half word */ + tmp = Address + 2; + + *(__IO uint16_t*) tmp = Data >> 16; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + /* Disable the PG Bit */ + FLASH->CR &= ~FLASH_CR_PG; + } + else + { + /* Disable the PG Bit */ + FLASH->CR &= ~FLASH_CR_PG; + } + } + + /* Return the Program Status */ + return status; +} + +/** + * @brief Programs a half word at a specified address. + * @note To correctly run this function, the FLASH_Unlock() function + * must be called before. + * Call the FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation) + * @param Address: specifies the address to be programmed. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status == FLASH_COMPLETE) + { + /* If the previous operation is completed, proceed to program the new data */ + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint16_t*)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + /* Disable the PG Bit */ + FLASH->CR &= ~FLASH_CR_PG; + } + + /* Return the Program Status */ + return status; +} + +/** + * @} + */ + +/** @defgroup FLASH_Group3 Option Bytes Programming functions + * @brief Option Bytes Programming functions + * +@verbatim + =============================================================================== + ##### Option Bytes Programming functions ##### + =============================================================================== + + [..] The FLASH_Option Bytes Programming_functions, includes the following functions: + (+) void FLASH_OB_Unlock(void); + (+) void FLASH_OB_Lock(void); + (+) void FLASH_OB_Launch(void); + (+) FLASH_Status FLASH_OB_Erase(void); + (+) FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState); + (+) FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP); + (+) FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); + (+) FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1); + (+) FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG); + (+) FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER); + (+) FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); + (+) uint8_t FLASH_OB_GetUser(void); + (+) uint32_t FLASH_OB_GetWRP(void); + (+) FlagStatus FLASH_OB_GetRDP(void); + + [..] Any operation of erase or program should follow these steps: + + (#) Call the FLASH_OB_Unlock() function to enable the Option Bytes registers access + + (#) Call one or several functions to program the desired option bytes + (++) FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read Protection Level + (++) FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) + => to Enable/Disable the desired sector write protection + (++) FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) + => to configure the user option Bytes: IWDG, STOP and the Standby. + (++) FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1) + => to set or reset BOOT1 + (++) FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG) + => to enable or disable the VDDA Analog Monitoring + (++) You can write all User Options bytes at once using a single function + by calling FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER) + (++) FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data) to program the + two half word in the option bytes + + (#) Once all needed option bytes to be programmed are correctly written, call the + FLASH_OB_Launch(void) function to launch the Option Bytes programming process. + + (#) Call the FLASH_OB_Lock() to disable the Option Bytes registers access (recommended + to protect the option Bytes against possible unwanted operations) + +@endverbatim + * @{ + */ + +/** + * @brief Unlocks the option bytes block access. + * @param None + * @retval None + */ +void FLASH_OB_Unlock(void) +{ + if((FLASH->CR & FLASH_CR_OPTWRE) == RESET) + { + /* Unlocking the option bytes block access */ + FLASH->OPTKEYR = FLASH_OPTKEY1; + FLASH->OPTKEYR = FLASH_OPTKEY2; + } +} + +/** + * @brief Locks the option bytes block access. + * @param None + * @retval None + */ +void FLASH_OB_Lock(void) +{ + /* Set the OPTWREN Bit to lock the option bytes block access */ + FLASH->CR &= ~FLASH_CR_OPTWRE; +} + +/** + * @brief Launch the option byte loading. + * @param None + * @retval None + */ +void FLASH_OB_Launch(void) +{ + /* Set the OBL_Launch bit to launch the option byte loading */ + FLASH->CR |= FLASH_CR_OBL_LAUNCH; +} + +/** + * @brief Erases the FLASH option bytes. + * @note To correctly run this function, the FLASH_OB_Unlock() function + * must be called before. + * Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes + * (recommended to protect the FLASH memory against possible unwanted operation) + * @note This functions erases all option bytes except the Read protection (RDP). + * @param None + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_OB_Erase(void) +{ + uint16_t rdptmp = OB_RDP_Level_0; + + FLASH_Status status = FLASH_COMPLETE; + + /* Get the actual read protection Option Byte value */ + if(FLASH_OB_GetRDP() != RESET) + { + rdptmp = 0x00; + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status == FLASH_COMPLETE) + { + /* If the previous operation is completed, proceed to erase the option bytes */ + FLASH->CR |= FLASH_CR_OPTER; + FLASH->CR |= FLASH_CR_STRT; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status == FLASH_COMPLETE) + { + /* If the erase operation is completed, disable the OPTER Bit */ + FLASH->CR &= ~FLASH_CR_OPTER; + + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= FLASH_CR_OPTPG; + + /* Restore the last read protection Option Byte value */ + OB->RDP = (uint16_t)rdptmp; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= ~FLASH_CR_OPTPG; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the OPTPG Bit */ + FLASH->CR &= ~FLASH_CR_OPTPG; + } + } + } + /* Return the erase status */ + return status; +} + +/** + * @brief Write protects the desired pages + * @note To correctly run this function, the FLASH_OB_Unlock() function + * must be called before. + * Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes + * (recommended to protect the FLASH memory against possible unwanted operation) + * @param OB_WRP: specifies the address of the pages to be write protected. + * This parameter can be: + * @arg OB_WRP_Pages0to3..OB_WRP_Pages60to63 + * @arg OB_WRP_AllPages + * @retval FLASH Status: The returned value can be: + * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP) +{ + uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF; + + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_WRP(OB_WRP)); + + OB_WRP = (uint32_t)(~OB_WRP); + WRP0_Data = (uint16_t)(OB_WRP & OB_WRP0_WRP0); + WRP1_Data = (uint16_t)((OB_WRP & OB_WRP0_nWRP0) >> 8); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status == FLASH_COMPLETE) + { + FLASH->CR |= FLASH_CR_OPTPG; + + if(WRP0_Data != 0xFF) + { + OB->WRP0 = WRP0_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + } + if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF)) + { + OB->WRP1 = WRP1_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + } + + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= ~FLASH_CR_OPTPG; + } + } + /* Return the write protection operation Status */ + return status; +} + +/** + * @brief Enables or disables the read out protection. + * @note To correctly run this function, the FLASH_OB_Unlock() function + * must be called before. + * Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes + * (recommended to protect the FLASH memory against possible unwanted operation) + * @param FLASH_ReadProtection_Level: specifies the read protection level. + * This parameter can be: + * @arg OB_RDP_Level_0: No protection + * @arg OB_RDP_Level_1: Read protection of the memory + * @arg OB_RDP_Level_2: Chip protection + * @retval FLASH Status: The returned value can be: + * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_RDP(OB_RDP)); + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status == FLASH_COMPLETE) + { + FLASH->CR |= FLASH_CR_OPTER; + FLASH->CR |= FLASH_CR_STRT; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status == FLASH_COMPLETE) + { + /* If the erase operation is completed, disable the OPTER Bit */ + FLASH->CR &= ~FLASH_CR_OPTER; + + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= FLASH_CR_OPTPG; + + OB->RDP = OB_RDP; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= ~FLASH_CR_OPTPG; + } + } + else + { + if(status != FLASH_TIMEOUT) + { + /* Disable the OPTER Bit */ + FLASH->CR &= ~FLASH_CR_OPTER; + } + } + } + /* Return the protection operation Status */ + return status; +} + +/** + * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + * @note To correctly run this function, the FLASH_OB_Unlock() function + * must be called before. + * Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes + * (recommended to protect the FLASH memory against possible unwanted operation) + * @param OB_IWDG: Selects the WDG mode + * This parameter can be one of the following values: + * @arg OB_IWDG_SW: Software WDG selected + * @arg OB_IWDG_HW: Hardware WDG selected + * @param OB_STOP: Reset event when entering STOP mode. + * This parameter can be one of the following values: + * @arg OB_STOP_NoRST: No reset generated when entering in STOP + * @arg OB_STOP_RST: Reset generated when entering in STOP + * @param OB_STDBY: Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY + * @arg OB_STDBY_RST: Reset generated when entering in STANDBY + * @retval FLASH Status: The returned value can be: + * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); + assert_param(IS_OB_STOP_SOURCE(OB_STOP)); + assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status == FLASH_COMPLETE) + { + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= FLASH_CR_OPTPG; + + OB->USER = (uint16_t)((uint16_t)(OB_IWDG | OB_STOP) | (uint16_t)(OB_STDBY | 0xF8)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status != FLASH_TIMEOUT) + { + /* If the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= ~FLASH_CR_OPTPG; + } + } + /* Return the Option Byte program Status */ + return status; +} + +/** + * @brief Sets or resets the BOOT1. + * @param OB_BOOT1: Set or Reset the BOOT1. + * This parameter can be one of the following values: + * @arg OB_BOOT1_RESET: BOOT1 Reset + * @arg OB_BOOT1_SET: BOOT1 Set + * @retval None + */ +FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_BOOT1(OB_BOOT1)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status == FLASH_COMPLETE) + { + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= FLASH_CR_OPTPG; + + OB->USER = OB_BOOT1 | 0xEF; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status != FLASH_TIMEOUT) + { + /* If the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= ~FLASH_CR_OPTPG; + } + } + /* Return the Option Byte program Status */ + return status; +} + +/** + * @brief Sets or resets the analogue monitoring on VDDA Power source. + * @param OB_VDDA_ANALOG: Selects the analog monitoring on VDDA Power source. + * This parameter can be one of the following values: + * @arg OB_VDDA_ANALOG_ON: Analog monitoring on VDDA Power source ON + * @arg OB_VDDA_ANALOG_OFF: Analog monitoring on VDDA Power source OFF + * @retval None + */ +FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_VDDA_ANALOG(OB_VDDA_ANALOG)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status == FLASH_COMPLETE) + { + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= FLASH_CR_OPTPG; + + OB->USER = OB_VDDA_ANALOG | 0xDF; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= ~FLASH_CR_OPTPG; + } + } + /* Return the Option Byte program Status */ + return status; +} + +/** + * @brief Sets or resets the SRAM parity. + * @param OB_SRAM_Parity: Set or Reset the SRAM parity enable bit. + * This parameter can be one of the following values: + * @arg OB_SRAM_PARITY_SET: Set SRAM parity. + * @arg OB_SRAM_PARITY_RESET: Reset SRAM parity. + * @retval None + */ +FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_SRAM_PARITY(OB_SRAM_Parity)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status == FLASH_COMPLETE) + { + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= FLASH_CR_OPTPG; + + OB->USER = OB_SRAM_Parity | 0xBF; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= ~FLASH_CR_OPTPG; + } + } + /* Return the Option Byte program Status */ + return status; +} + +/** + * @brief Programs the FLASH User Option Byte: IWDG_SW, RST_STOP, RST_STDBY, + * BOOT1 and VDDA ANALOG monitoring. + * @note To correctly run this function, the FLASH_OB_Unlock() function + * must be called before. + * Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes + * (recommended to protect the FLASH memory against possible unwanted operation) + * @param OB_USER: Selects all user option bytes + * This parameter is a combination of the following values: + * @arg OB_IWDG_SW / OB_IWDG_HW: Software / Hardware WDG selected + * @arg OB_STOP_NoRST / OB_STOP_RST: No reset / Reset generated when entering in STOP + * @arg OB_STDBY_NoRST / OB_STDBY_RST: No reset / Reset generated when entering in STANDBY + * @arg OB_BOOT1_RESET / OB_BOOT1_SET: BOOT1 Reset / Set + * @arg OB_VDDA_ANALOG_ON / OB_VDDA_ANALOG_OFF: Analog monitoring on VDDA Power source ON / OFF + * @arg OB_SRAM_PARITY_SET / OB_SRAM_PARITY_RESET: SRAM Parity SET / RESET + * @retval FLASH Status: The returned value can be: + * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status == FLASH_COMPLETE) + { + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= FLASH_CR_OPTPG; + + OB->USER = OB_USER | 0x88; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status != FLASH_TIMEOUT) + { + /* If the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= ~FLASH_CR_OPTPG; + } + } + /* Return the Option Byte program Status */ + return status; + +} + +/** + * @brief Programs a half word at a specified Option Byte Data address. + * @note To correctly run this function, the FLASH_OB_Unlock() function + * must be called before. + * Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes + * (recommended to protect the FLASH memory against possible unwanted operation) + * @param Address: specifies the address to be programmed. + * This parameter can be 0x1FFFF804 or 0x1FFFF806. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_OB_DATA_ADDRESS(Address)); + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status == FLASH_COMPLETE) + { + /* Enables the Option Bytes Programming operation */ + FLASH->CR |= FLASH_CR_OPTPG; + *(__IO uint16_t*)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if(status != FLASH_TIMEOUT) + { + /* If the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= ~FLASH_CR_OPTPG; + } + } + /* Return the Option Byte Data Program Status */ + return status; +} + +/** + * @brief Returns the FLASH User Option Bytes values. + * @param None + * @retval The FLASH User Option Bytes . + */ +uint8_t FLASH_OB_GetUser(void) +{ + /* Return the User Option Byte */ + return (uint8_t)(FLASH->OBR >> 8); +} + +/** + * @brief Returns the FLASH Write Protection Option Bytes value. + * @param None + * @retval The FLASH Write Protection Option Bytes value + */ +uint32_t FLASH_OB_GetWRP(void) +{ + /* Return the FLASH write protection Register value */ + return (uint32_t)(FLASH->WRPR); +} + +/** + * @brief Checks whether the FLASH Read out Protection Status is set or not. + * @param None + * @retval FLASH ReadOut Protection Status(SET or RESET) + */ +FlagStatus FLASH_OB_GetRDP(void) +{ + FlagStatus readstatus = RESET; + + if ((uint8_t)(FLASH->OBR & (FLASH_OBR_RDPRT1 | FLASH_OBR_RDPRT2)) != RESET) + { + readstatus = SET; + } + else + { + readstatus = RESET; + } + return readstatus; +} + +/** + * @} + */ + +/** @defgroup FLASH_Group4 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified FLASH interrupts. + * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or + * disabled. + * This parameter can be any combination of the following values: + * @arg FLASH_IT_EOP: FLASH end of programming Interrupt + * @arg FLASH_IT_ERR: FLASH Error Interrupt + * @retval None + */ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FLASH_IT(FLASH_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if(NewState != DISABLE) + { + /* Enable the interrupt sources */ + FLASH->CR |= FLASH_IT; + } + else + { + /* Disable the interrupt sources */ + FLASH->CR &= ~(uint32_t)FLASH_IT; + } +} + +/** + * @brief Checks whether the specified FLASH flag is set or not. + * @param FLASH_FLAG: specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag + * @arg FLASH_FLAG_PGERR: FLASH Programming error flag flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_EOP: FLASH End of Programming flag + * @retval The new state of FLASH_FLAG (SET or RESET). + */ +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)); + + if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the new state of FLASH_FLAG (SET or RESET) */ + return bitstatus; +} + +/** + * @brief Clears the FLASH's pending flags. + * @param FLASH_FLAG: specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg FLASH_FLAG_PGERR: FLASH Programming error flag flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_EOP: FLASH End of Programming flag + * @retval None + */ +void FLASH_ClearFlag(uint32_t FLASH_FLAG) +{ + /* Check the parameters */ + assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)); + + /* Clear the flags */ + FLASH->SR = FLASH_FLAG; +} + +/** + * @brief Returns the FLASH Status. + * @param None + * @retval FLASH Status: The returned value can be: + * FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_GetStatus(void) +{ + FLASH_Status FLASHstatus = FLASH_COMPLETE; + + if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) + { + FLASHstatus = FLASH_BUSY; + } + else + { + if((FLASH->SR & (uint32_t)FLASH_FLAG_WRPERR)!= (uint32_t)0x00) + { + FLASHstatus = FLASH_ERROR_WRP; + } + else + { + if((FLASH->SR & (uint32_t)(FLASH_SR_PGERR)) != (uint32_t)0x00) + { + FLASHstatus = FLASH_ERROR_PROGRAM; + } + else + { + FLASHstatus = FLASH_COMPLETE; + } + } + } + /* Return the FLASH Status */ + return FLASHstatus; +} + + +/** + * @brief Waits for a FLASH operation to complete or a TIMEOUT to occur. + * @param Timeout: FLASH programming Timeout + * @retval FLASH Status: The returned value can be: FLASH_BUSY, + * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check for the FLASH Status */ + status = FLASH_GetStatus(); + + /* Wait for a FLASH operation to complete or a TIMEOUT to occur */ + while((status == FLASH_BUSY) && (Timeout != 0x00)) + { + status = FLASH_GetStatus(); + Timeout--; + } + + if(Timeout == 0x00 ) + { + status = FLASH_TIMEOUT; + } + /* Return the operation status */ + return status; +} + +/** + * @} + */ + +/** + * @} + */ + + /** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_gpio.c b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_gpio.c new file mode 100644 index 0000000..d0075d6 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_gpio.c @@ -0,0 +1,504 @@ +/** + ****************************************************************************** + * @file stm32f0xx_gpio.c + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the GPIO peripheral: + * + Initialization and Configuration functions + * + GPIO Read and Write functions + * + GPIO Alternate functions configuration functions + * + * @verbatim + * + * + =========================================================================== + ##### How to use this driver ##### + =========================================================================== + [..] + (#) Enable the GPIO AHB clock using RCC_AHBPeriphClockCmd() + (#) Configure the GPIO pin(s) using GPIO_Init() + Four possible configuration are available for each pin: + (++) Input: Floating, Pull-up, Pull-down. + (++) Output: Push-Pull (Pull-up, Pull-down or no Pull) + Open Drain (Pull-up, Pull-down or no Pull). + In output mode, the speed is configurable: Low, Medium, Fast or High. + (++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull) + Open Drain (Pull-up, Pull-down or no Pull). + (++) Analog: required mode when a pin is to be used as ADC channel, + DAC output or comparator input. + (#) Peripherals alternate function: + (++) For ADC, DAC and comparators, configure the desired pin in analog + mode using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN + (++) For other peripherals (TIM, USART...): + (+++) Connect the pin to the desired peripherals' Alternate + Function (AF) using GPIO_PinAFConfig() function. For PortC, + PortD and PortF, no configuration is needed. + (+++) Configure the desired pin in alternate function mode using + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF + (+++) Select the type, pull-up/pull-down and output speed via + GPIO_PuPd, GPIO_OType and GPIO_Speed members + (+++) Call GPIO_Init() function + (#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit() + (#) To set/reset the level of a pin configured in output mode use + GPIO_SetBits()/GPIO_ResetBits() + (#) During and just after reset, the alternate functions are not active and + the GPIO pins are configured in input floating mode (except JTAG pins). + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as + general-purpose (PC14 and PC15, respectively) when the LSE oscillator + is off. The LSE has priority over the GPIO function. + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose + PD0 and PD1, respectively, when the HSE oscillator is off. The HSE has + priority over the GPIO function. + @endverbatim + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_gpio.h" +#include "stm32f0xx_rcc.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup GPIO + * @brief GPIO driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup GPIO_Private_Functions + * @{ + */ + +/** @defgroup GPIO_Group1 Initialization and Configuration + * @brief Initialization and Configuration + * +@verbatim + =============================================================================== + ##### Initialization and Configuration ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the GPIOx peripheral registers to their default reset + * values. + * @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral. + * @retval None + */ +void GPIO_DeInit(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + if(GPIOx == GPIOA) + { + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE); + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE); + } + else if(GPIOx == GPIOB) + { + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE); + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE); + } + else if(GPIOx == GPIOC) + { + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE); + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE); + } + else if(GPIOx == GPIOD) + { + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE); + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE); + } + else + { + if(GPIOx == GPIOF) + { + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, ENABLE); + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, DISABLE); + } + } +} + +/** + * @brief Initializes the GPIOx peripheral according to the specified + * parameters in the GPIO_InitStruct. + * @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral. + * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @note The configured pins can be: GPIO_Pin_0 -> GPIO_Pin_15 for GPIOA, GPIOB and GPIOC, + * GPIO_Pin_0 -> GPIO_Pin_2 for GPIOD, GPIO_Pin_0 -> GPIO_Pin_3 for GPIOF. + * @retval None + */ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) +{ + uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); + assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); + assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd)); + + /*-------------------------- Configure the port pins -----------------------*/ + /*-- GPIO Mode Configuration --*/ + for (pinpos = 0x00; pinpos < 0x10; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + + /* Get the port pins position */ + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + + if (currentpin == pos) + { + if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF)) + { + /* Check Speed mode parameters */ + assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); + + /* Speed mode configuration */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2)); + GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2)); + + /* Check Output mode parameters */ + assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType)); + + /* Output mode configuration */ + GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)); + GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos)); + } + + GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2)); + + GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2)); + + /* Pull-up Pull down resistor configuration */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2)); + GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2)); + } + } +} + +/** + * @brief Fills each GPIO_InitStruct member with its default value. + * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_Level_2; + GPIO_InitStruct->GPIO_OType = GPIO_OType_PP; + GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL; +} + +/** + * @brief Locks GPIO Pins configuration registers. + * The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + * @note The configuration of the locked GPIO pins can no longer be modified + * until the next reset. + * @param GPIOx: where x can be (A or B) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = 0x00010000; + + /* Check the parameters */ + assert_param(IS_GPIO_LIST_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + tmp |= GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Reset LCKK bit */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Read LCKK bit */ + tmp = GPIOx->LCKR; + /* Read LCKK bit */ + tmp = GPIOx->LCKR; +} + +/** + * @} + */ + +/** @defgroup GPIO_Group2 GPIO Read and Write + * @brief GPIO Read and Write + * +@verbatim + =============================================================================== + ##### GPIO Read and Write ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Reads the specified input port pin. + * @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to read. + * @note This parameter can be GPIO_Pin_x where x can be:(0..15) for GPIOA, + * GPIOB or GPIOC,(0..2) for GPIOD and(0..3) for GPIOF. + * @retval The input port pin value. + */ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified input port pin. + * @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral. + * @retval The input port pin value. + */ +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->IDR); +} + +/** + * @brief Reads the specified output data port bit. + * @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral. + * @param GPIO_Pin: Specifies the port bit to read. + * @note This parameter can be GPIO_Pin_x where x can be:(0..15) for GPIOA, + * GPIOB or GPIOC,(0..2) for GPIOD and(0..3) for GPIOF. + * @retval The output port pin value. + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO output data port. + * @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral. + * @retval GPIO output data port value. + */ +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->ODR); +} + +/** + * @brief Sets the selected data port bits. + * @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bits to be written. + * @note This parameter can be GPIO_Pin_x where x can be:(0..15) for GPIOA, + * GPIOB or GPIOC,(0..2) for GPIOD and(0..3) for GPIOF. + * @retval None + */ +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BSRR = GPIO_Pin; +} + +/** + * @brief Clears the selected data port bits. + * @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bits to be written. + * @note This parameter can be GPIO_Pin_x where x can be: (0..15) for GPIOA, + * GPIOB or GPIOC,(0..2) for GPIOD and(0..3) for GPIOF. + * @retval None + */ +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BRR = GPIO_Pin; +} + +/** + * @brief Sets or clears the selected data port bit. + * @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to be written. + * @param BitVal: specifies the value to be written to the selected bit. + * This parameter can be one of the BitAction enumeration values: + * @arg Bit_RESET: to clear the port pin + * @arg Bit_SET: to set the port pin + * @note The GPIO_Pin parameter can be GPIO_Pin_x where x can be: (0..15) for GPIOA, + * GPIOB or GPIOC,(0..2) for GPIOD and(0..3) for GPIOF. + * @retval None + */ +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_BIT_ACTION(BitVal)); + + if (BitVal != Bit_RESET) + { + GPIOx->BSRR = GPIO_Pin; + } + else + { + GPIOx->BRR = GPIO_Pin ; + } +} + +/** + * @brief Writes data to the specified GPIO data port. + * @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral. + * @param PortVal: specifies the value to be written to the port output data + * register. + * @retval None + */ +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + GPIOx->ODR = PortVal; +} + +/** + * @} + */ + +/** @defgroup GPIO_Group3 GPIO Alternate functions configuration functions + * @brief GPIO Alternate functions configuration functions + * +@verbatim + =============================================================================== + ##### GPIO Alternate functions configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Writes data to the specified GPIO data port. + * @param GPIOx: where x can be (A or B) to select the GPIO peripheral. + * @param GPIO_PinSource: specifies the pin for the Alternate function. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * @param GPIO_AF: selects the pin to used as Alternate function. + * This parameter can be one of the following value: + * @arg GPIO_AF_0:WKUP, EVENTOUT, TIM15, SPI1, TIM17,MCO, SWDAT, SWCLK, TIM14, + * BOOT,USART1, CEC, IR_OUT, SPI2 + * @arg GPIO_AF_1:USART2, CEC, Tim3, USART1, USART2,EVENTOUT, I2C1, I2C2, TIM15 + * @arg GPIO_AF_2:TIM2, TIM1, EVENTOUT, TIM16, TIM17. + * @arg GPIO_AF_3:TS, I2C1, TIM15, EVENTOUT + * @arg GPIO_AF_4:TIM14. + * @arg GPIO_AF_5:TIM16, TIM17. + * @arg GPIO_AF_6:EVENTOUT. + * @arg GPIO_AF_7:COMP1 OUT, COMP2 OUT + * @note The pin should already been configured in Alternate Function mode(AF) + * using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF + * @note Refer to the Alternate function mapping table in the device datasheet + * for the detailed mapping of the system and peripherals'alternate + * function I/O pins. + * @retval None + */ +void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF) +{ + uint32_t temp = 0x00; + uint32_t temp_2 = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_LIST_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); + assert_param(IS_GPIO_AF(GPIO_AF)); + + temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)); + GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)); + temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp; + GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_i2c.c b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_i2c.c new file mode 100644 index 0000000..4a48024 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_i2c.c @@ -0,0 +1,1565 @@ +/** + ****************************************************************************** + * @file stm32f0xx_i2c.c + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Inter-Integrated circuit (I2C): + * + Initialization and Configuration + * + Communications handling + * + SMBUS management + * + I2C registers management + * + Data transfers management + * + DMA transfers management + * + Interrupts and flags management + * + * @verbatim + ============================================================================ + ##### How to use this driver ##### + ============================================================================ + [..] + (#) Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE) + function for I2C1 or I2C2. + (#) Enable SDA, SCL and SMBA (when used) GPIO clocks using + RCC_AHBPeriphClockCmd() function. + (#) Peripherals alternate function: + (++) Connect the pin to the desired peripherals' Alternate + Function (AF) using GPIO_PinAFConfig() function. + (++) Configure the desired pin in alternate function by: + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF + (++) Select the type, OpenDrain and speed via + GPIO_PuPd, GPIO_OType and GPIO_Speed members + (++) Call GPIO_Init() function. + (#) Program the Mode, Timing , Own address, Ack and Acknowledged Address + using the I2C_Init() function. + (#) Optionally you can enable/configure the following parameters without + re-initialization (i.e there is no need to call again I2C_Init() function): + (++) Enable the acknowledge feature using I2C_AcknowledgeConfig() function. + (++) Enable the dual addressing mode using I2C_DualAddressCmd() function. + (++) Enable the general call using the I2C_GeneralCallCmd() function. + (++) Enable the clock stretching using I2C_StretchClockCmd() function. + (++) Enable the PEC Calculation using I2C_CalculatePEC() function. + (++) For SMBus Mode: + (+++) Enable the SMBusAlert pin using I2C_SMBusAlertCmd() function. + (#) Enable the NVIC and the corresponding interrupt using the function + I2C_ITConfig() if you need to use interrupt mode. + (#) When using the DMA mode + (++) Configure the DMA using DMA_Init() function. + (++) Active the needed channel Request using I2C_DMACmd() function. + (#) Enable the I2C using the I2C_Cmd() function. + (#) Enable the DMA using the DMA_Cmd() function when using DMA mode in the + transfers. + [..] + (@) When using I2C in Fast Mode Plus, SCL and SDA pin 20mA current drive capability + must be enabled by setting the driving capability control bit in SYSCFG. + + @endverbatim + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_i2c.h" +#include "stm32f0xx_rcc.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup I2C + * @brief I2C driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +#define CR1_CLEAR_MASK ((uint32_t)0x00CFE0FF) /*I2C_AnalogFilter)); + assert_param(IS_I2C_DIGITAL_FILTER(I2C_InitStruct->I2C_DigitalFilter)); + assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); + assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); + assert_param(IS_I2C_ACK(I2C_InitStruct->I2C_Ack)); + assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress)); + + /* Disable I2Cx Peripheral */ + I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE); + + /*---------------------------- I2Cx FILTERS Configuration ------------------*/ + /* Get the I2Cx CR1 value */ + tmpreg = I2Cx->CR1; + /* Clear I2Cx CR1 register */ + tmpreg &= CR1_CLEAR_MASK; + /* Configure I2Cx: analog and digital filter */ + /* Set ANFOFF bit according to I2C_AnalogFilter value */ + /* Set DFN bits according to I2C_DigitalFilter value */ + tmpreg |= (uint32_t)I2C_InitStruct->I2C_AnalogFilter |(I2C_InitStruct->I2C_DigitalFilter << 8); + + /* Write to I2Cx CR1 */ + I2Cx->CR1 = tmpreg; + + /*---------------------------- I2Cx TIMING Configuration -------------------*/ + /* Configure I2Cx: Timing */ + /* Set TIMINGR bits according to I2C_Timing */ + /* Write to I2Cx TIMING */ + I2Cx->TIMINGR = I2C_InitStruct->I2C_Timing & TIMING_CLEAR_MASK; + + /* Enable I2Cx Peripheral */ + I2Cx->CR1 |= I2C_CR1_PE; + + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + /* Clear tmpreg local variable */ + tmpreg = 0; + /* Clear OAR1 register */ + I2Cx->OAR1 = (uint32_t)tmpreg; + /* Clear OAR2 register */ + I2Cx->OAR2 = (uint32_t)tmpreg; + /* Configure I2Cx: Own Address1 and acknowledged address */ + /* Set OA1MODE bit according to I2C_AcknowledgedAddress value */ + /* Set OA1 bits according to I2C_OwnAddress1 value */ + tmpreg = (uint32_t)((uint32_t)I2C_InitStruct->I2C_AcknowledgedAddress | \ + (uint32_t)I2C_InitStruct->I2C_OwnAddress1); + /* Write to I2Cx OAR1 */ + I2Cx->OAR1 = tmpreg; + /* Enable Own Address1 acknowledgement */ + I2Cx->OAR1 |= I2C_OAR1_OA1EN; + + /*---------------------------- I2Cx MODE Configuration ---------------------*/ + /* Configure I2Cx: mode */ + /* Set SMBDEN and SMBHEN bits according to I2C_Mode value */ + tmpreg = I2C_InitStruct->I2C_Mode; + /* Write to I2Cx CR1 */ + I2Cx->CR1 |= tmpreg; + + /*---------------------------- I2Cx ACK Configuration ----------------------*/ + /* Get the I2Cx CR2 value */ + tmpreg = I2Cx->CR2; + /* Clear I2Cx CR2 register */ + tmpreg &= CR2_CLEAR_MASK; + /* Configure I2Cx: acknowledgement */ + /* Set NACK bit according to I2C_Ack value */ + tmpreg |= I2C_InitStruct->I2C_Ack; + /* Write to I2Cx CR2 */ + I2Cx->CR2 = tmpreg; +} + +/** + * @brief Fills each I2C_InitStruct member with its default value. + * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized. + * @retval None + */ +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) +{ + /*---------------- Reset I2C init structure parameters values --------------*/ + /* Initialize the I2C_Timing member */ + I2C_InitStruct->I2C_Timing = 0; + /* Initialize the I2C_AnalogFilter member */ + I2C_InitStruct->I2C_AnalogFilter = I2C_AnalogFilter_Enable; + /* Initialize the I2C_DigitalFilter member */ + I2C_InitStruct->I2C_DigitalFilter = 0; + /* Initialize the I2C_Mode member */ + I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; + /* Initialize the I2C_OwnAddress1 member */ + I2C_InitStruct->I2C_OwnAddress1 = 0; + /* Initialize the I2C_Ack member */ + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; + /* Initialize the I2C_AcknowledgedAddress member */ + I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +} + +/** + * @brief Enables or disables the specified I2C peripheral. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2Cx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C peripheral */ + I2Cx->CR1 |= I2C_CR1_PE; + } + else + { + /* Disable the selected I2C peripheral */ + I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE); + } +} + +/** + * @brief Enables or disables the specified I2C software reset. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C software reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Peripheral under reset */ + I2Cx->CR1 |= I2C_CR1_SWRST; + } + else + { + /* Peripheral not under reset */ + I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_SWRST); + } +} + +/** + * @brief Enables or disables the specified I2C interrupts. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2C_IT_ERRI: Error interrupt mask + * @arg I2C_IT_TCI: Transfer Complete interrupt mask + * @arg I2C_IT_STOPI: Stop Detection interrupt mask + * @arg I2C_IT_NACKI: Not Acknowledge received interrupt mask + * @arg I2C_IT_ADDRI: Address Match interrupt mask + * @arg I2C_IT_RXI: RX interrupt mask + * @arg I2C_IT_TXI: TX interrupt mask + * @param NewState: new state of the specified I2C interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_I2C_CONFIG_IT(I2C_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected I2C interrupts */ + I2Cx->CR1 |= I2C_IT; + } + else + { + /* Disable the selected I2C interrupts */ + I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_IT); + } +} + +/** + * @brief Enables or disables the I2C Clock stretching. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2Cx Clock stretching. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable clock stretching */ + I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_NOSTRETCH); + } + else + { + /* Disable clock stretching */ + I2Cx->CR1 |= I2C_CR1_NOSTRETCH; + } +} + +/** + * @brief Enables or disables I2C wakeup from stop mode. + * @param I2Cx: where x can be 1 to select the I2C peripheral. + * @param NewState: new state of the I2Cx stop mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_StopModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_1_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable wakeup from stop mode */ + I2Cx->CR1 |= I2C_CR1_WUPEN; + } + else + { + /* Disable wakeup from stop mode */ + I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_WUPEN); + } +} + +/** + * @brief Enables or disables the I2C own address 2. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C own address 2. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable own address 2 */ + I2Cx->OAR2 |= I2C_OAR2_OA2EN; + } + else + { + /* Disable own address 2 */ + I2Cx->OAR2 &= (uint32_t)~((uint32_t)I2C_OAR2_OA2EN); + } +} + +/** + * @brief Configures the I2C slave own address 2 and mask. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param Address: specifies the slave address to be programmed. + * @param Mask: specifies own address 2 mask to be programmed. + * This parameter can be one of the following values: + * @arg I2C_OA2_NoMask: no mask. + * @arg I2C_OA2_Mask01: OA2[1] is masked and don't care. + * @arg I2C_OA2_Mask02: OA2[2:1] are masked and don't care. + * @arg I2C_OA2_Mask03: OA2[3:1] are masked and don't care. + * @arg I2C_OA2_Mask04: OA2[4:1] are masked and don't care. + * @arg I2C_OA2_Mask05: OA2[5:1] are masked and don't care. + * @arg I2C_OA2_Mask06: OA2[6:1] are masked and don't care. + * @arg I2C_OA2_Mask07: OA2[7:1] are masked and don't care. + * @retval None + */ +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_OWN_ADDRESS2(Address)); + assert_param(IS_I2C_OWN_ADDRESS2_MASK(Mask)); + + /* Get the old register value */ + tmpreg = I2Cx->OAR2; + + /* Reset I2Cx OA2 bit [7:1] and OA2MSK bit [1:0] */ + tmpreg &= (uint32_t)~((uint32_t)(I2C_OAR2_OA2 | I2C_OAR2_OA2MSK)); + + /* Set I2Cx SADD */ + tmpreg |= (uint32_t)(((uint32_t)Address & I2C_OAR2_OA2) | \ + (((uint32_t)Mask << 8) & I2C_OAR2_OA2MSK)) ; + + /* Store the new register value */ + I2Cx->OAR2 = tmpreg; +} + +/** + * @brief Enables or disables the I2C general call mode. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C general call mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable general call mode */ + I2Cx->CR1 |= I2C_CR1_GCEN; + } + else + { + /* Disable general call mode */ + I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_GCEN); + } +} + +/** + * @brief Enables or disables the I2C slave byte control. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C slave byte control. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable slave byte control */ + I2Cx->CR1 |= I2C_CR1_SBC; + } + else + { + /* Disable slave byte control */ + I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_SBC); + } +} + +/** + * @brief Configures the slave address to be transmitted after start generation. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param Address: specifies the slave address to be programmed. + * @note This function should be called before generating start condition. + * @retval None + */ +void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_SLAVE_ADDRESS(Address)); + + /* Get the old register value */ + tmpreg = I2Cx->CR2; + + /* Reset I2Cx SADD bit [9:0] */ + tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_SADD); + + /* Set I2Cx SADD */ + tmpreg |= (uint32_t)((uint32_t)Address & I2C_CR2_SADD); + + /* Store the new register value */ + I2Cx->CR2 = tmpreg; +} + +/** + * @brief Enables or disables the I2C 10-bit addressing mode for the master. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C 10-bit addressing mode. + * This parameter can be: ENABLE or DISABLE. + * @note This function should be called before generating start condition. + * @retval None + */ +void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable 10-bit addressing mode */ + I2Cx->CR2 |= I2C_CR2_ADD10; + } + else + { + /* Disable 10-bit addressing mode */ + I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_ADD10); + } +} + +/** + * @} + */ + + +/** @defgroup I2C_Group2 Communications handling functions + * @brief Communications handling functions + * +@verbatim + =============================================================================== + ##### Communications handling functions ##### + =============================================================================== + [..] This section provides a set of functions that handles I2C communication. + + [..] Automatic End mode is enabled using I2C_AutoEndCmd() function. When Reload + mode is enabled via I2C_ReloadCmd() AutoEnd bit has no effect. + + [..] I2C_NumberOfBytesConfig() function set the number of bytes to be transferred, + this configuration should be done before generating start condition in master + mode. + + [..] When switching from master write operation to read operation in 10Bit addressing + mode, master can only sends the 1st 7 bits of the 10 bit address, followed by + Read direction by enabling HEADR bit using I2C_10BitAddressHeader() function. + + [..] In master mode, when transferring more than 255 bytes Reload mode should be used + to handle communication. In the first phase of transfer, Nbytes should be set to + 255. After transferring these bytes TCR flag is set and I2C_TransferHandling() + function should be called to handle remaining communication. + + [..] In master mode, when software end mode is selected when all data is transferred + TC flag is set I2C_TransferHandling() function should be called to generate STOP + or generate ReStart. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the I2C automatic end mode (stop condition is + * automatically sent when nbytes data are transferred). + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C automatic end mode. + * This parameter can be: ENABLE or DISABLE. + * @note This function has effect if Reload mode is disabled. + * @retval None + */ +void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable Auto end mode */ + I2Cx->CR2 |= I2C_CR2_AUTOEND; + } + else + { + /* Disable Auto end mode */ + I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_AUTOEND); + } +} + +/** + * @brief Enables or disables the I2C nbytes reload mode. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the nbytes reload mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable Auto Reload mode */ + I2Cx->CR2 |= I2C_CR2_RELOAD; + } + else + { + /* Disable Auto Reload mode */ + I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RELOAD); + } +} + +/** + * @brief Configures the number of bytes to be transmitted/received. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param Number_Bytes: specifies the number of bytes to be programmed. + * @retval None + */ +void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Get the old register value */ + tmpreg = I2Cx->CR2; + + /* Reset I2Cx Nbytes bit [7:0] */ + tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_NBYTES); + + /* Set I2Cx Nbytes */ + tmpreg |= (uint32_t)(((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES); + + /* Store the new register value */ + I2Cx->CR2 = tmpreg; +} + +/** + * @brief Configures the type of transfer request for the master. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_Direction: specifies the transfer request direction to be programmed. + * This parameter can be one of the following values: + * @arg I2C_Direction_Transmitter: Master request a write transfer + * @arg I2C_Direction_Receiver: Master request a read transfer + * @retval None + */ +void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction) +{ +/* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_DIRECTION(I2C_Direction)); + + /* Test on the direction to set/reset the read/write bit */ + if (I2C_Direction == I2C_Direction_Transmitter) + { + /* Request a write Transfer */ + I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RD_WRN); + } + else + { + /* Request a read Transfer */ + I2Cx->CR2 |= I2C_CR2_RD_WRN; + } +} + +/** + * @brief Generates I2Cx communication START condition. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C START condition generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Generate a START condition */ + I2Cx->CR2 |= I2C_CR2_START; + } + else + { + /* Disable the START condition generation */ + I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_START); + } +} + +/** + * @brief Generates I2Cx communication STOP condition. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C STOP condition generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Generate a STOP condition */ + I2Cx->CR2 |= I2C_CR2_STOP; + } + else + { + /* Disable the STOP condition generation */ + I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_STOP); + } +} + +/** + * @brief Enables or disables the I2C 10-bit header only mode with read direction. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C 10-bit header only mode. + * This parameter can be: ENABLE or DISABLE. + * @note This mode can be used only when switching from master transmitter mode + * to master receiver mode. + * @retval None + */ +void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable 10-bit header only mode */ + I2Cx->CR2 |= I2C_CR2_HEAD10R; + } + else + { + /* Disable 10-bit header only mode */ + I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_HEAD10R); + } +} + +/** + * @brief Generates I2C communication Acknowledge. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the Acknowledge. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable ACK generation */ + I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_NACK); + } + else + { + /* Enable NACK generation */ + I2Cx->CR2 |= I2C_CR2_NACK; + } +} + +/** + * @brief Returns the I2C slave matched address . + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @retval The value of the slave matched address . + */ +uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Return the slave matched address in the SR1 register */ + return (uint8_t)(((uint32_t)I2Cx->ISR & I2C_ISR_ADDCODE) >> 16) ; +} + +/** + * @brief Returns the I2C slave received request. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @retval The value of the received request. + */ +uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx) +{ + uint32_t tmpreg = 0; + uint16_t direction = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Return the slave matched address in the SR1 register */ + tmpreg = (uint32_t)(I2Cx->ISR & I2C_ISR_DIR); + + /* If write transfer is requested */ + if (tmpreg == 0) + { + /* write transfer is requested */ + direction = I2C_Direction_Transmitter; + } + else + { + /* Read transfer is requested */ + direction = I2C_Direction_Receiver; + } + return direction; +} + +/** + * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param Address: specifies the slave address to be programmed. + * @param Number_Bytes: specifies the number of bytes to be programmed. + * This parameter must be a value between 0 and 255. + * @param ReloadEndMode: new state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg I2C_Reload_Mode: Enable Reload mode . + * @arg I2C_AutoEnd_Mode: Enable Automatic end mode. + * @arg I2C_SoftEnd_Mode: Enable Software end mode. + * @param StartStopMode: new state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg I2C_No_StartStop: Don't Generate stop and start condition. + * @arg I2C_Generate_Stop: Generate stop condition (Number_Bytes should be set to 0). + * @arg I2C_Generate_Start_Read: Generate Restart for read request. + * @arg I2C_Generate_Start_Write: Generate Restart for write request. + * @retval None + */ +void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_SLAVE_ADDRESS(Address)); + assert_param(IS_RELOAD_END_MODE(ReloadEndMode)); + assert_param(IS_START_STOP_MODE(StartStopMode)); + + /* Get the CR2 register value */ + tmpreg = I2Cx->CR2; + + /* clear tmpreg specific bits */ + tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP)); + + /* update tmpreg */ + tmpreg |= (uint32_t)(((uint32_t)Address & I2C_CR2_SADD) | (((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES) | \ + (uint32_t)ReloadEndMode | (uint32_t)StartStopMode); + + /* update CR2 register */ + I2Cx->CR2 = tmpreg; +} + +/** + * @} + */ + + +/** @defgroup I2C_Group3 SMBUS management functions + * @brief SMBUS management functions + * +@verbatim + =============================================================================== + ##### SMBUS management functions ##### + =============================================================================== + [..] This section provides a set of functions that handles SMBus communication + and timeouts detection. + + [..] The SMBus Device default address (0b1100 001) is enabled by calling I2C_Init() + function and setting I2C_Mode member of I2C_InitTypeDef() structure to + I2C_Mode_SMBusDevice. + + [..] The SMBus Host address (0b0001 000) is enabled by calling I2C_Init() + function and setting I2C_Mode member of I2C_InitTypeDef() structure to + I2C_Mode_SMBusHost. + + [..] The Alert Response Address (0b0001 100) is enabled using I2C_SMBusAlertCmd() + function. + + [..] To detect cumulative SCL stretch in master and slave mode, TIMEOUTB should be + configured (in accordance to SMBus specification) using I2C_TimeoutBConfig() + function then I2C_ExtendedClockTimeoutCmd() function should be called to enable + the detection. + + [..] SCL low timeout is detected by configuring TIMEOUTB using I2C_TimeoutBConfig() + function followed by the call of I2C_ClockTimeoutCmd(). When adding to this + procedure the call of I2C_IdleClockTimeoutCmd() function, Bus Idle condition + (both SCL and SDA high) is detected also. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables I2C SMBus alert. + * @param I2Cx: where x can be 1 to select the I2C peripheral. + * @param NewState: new state of the I2Cx SMBus alert. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_1_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable SMBus alert */ + I2Cx->CR1 |= I2C_CR1_ALERTEN; + } + else + { + /* Disable SMBus alert */ + I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_ALERTEN); + } +} + +/** + * @brief Enables or disables I2C Clock Timeout (SCL Timeout detection). + * @param I2Cx: where x can be 1 to select the I2C peripheral. + * @param NewState: new state of the I2Cx clock Timeout. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_1_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable Clock Timeout */ + I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIMOUTEN; + } + else + { + /* Disable Clock Timeout */ + I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMOUTEN); + } +} + +/** + * @brief Enables or disables I2C Extended Clock Timeout (SCL cumulative Timeout detection). + * @param I2Cx: where x can be 1 to select the I2C peripheral. + * @param NewState: new state of the I2Cx Extended clock Timeout. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_1_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable Clock Timeout */ + I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TEXTEN; + } + else + { + /* Disable Clock Timeout */ + I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TEXTEN); + } +} + +/** + * @brief Enables or disables I2C Idle Clock Timeout (Bus idle SCL and SDA + * high detection). + * @param I2Cx: where x can be 1 to select the I2C peripheral. + * @param NewState: new state of the I2Cx Idle clock Timeout. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_1_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable Clock Timeout */ + I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIDLE; + } + else + { + /* Disable Clock Timeout */ + I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIDLE); + } +} + +/** + * @brief Configures the I2C Bus Timeout A (SCL Timeout when TIDLE = 0 or Bus + * idle SCL and SDA high when TIDLE = 1). + * @param I2Cx: where x can be 1 to select the I2C peripheral. + * @param Timeout: specifies the TimeoutA to be programmed. + * @retval None + */ +void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_1_PERIPH(I2Cx)); + assert_param(IS_I2C_TIMEOUT(Timeout)); + + /* Get the old register value */ + tmpreg = I2Cx->TIMEOUTR; + + /* Reset I2Cx TIMEOUTA bit [11:0] */ + tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTA); + + /* Set I2Cx TIMEOUTA */ + tmpreg |= (uint32_t)((uint32_t)Timeout & I2C_TIMEOUTR_TIMEOUTA) ; + + /* Store the new register value */ + I2Cx->TIMEOUTR = tmpreg; +} + +/** + * @brief Configures the I2C Bus Timeout B (SCL cumulative Timeout). + * @param I2Cx: where x can be 1 to select the I2C peripheral. + * @param Timeout: specifies the TimeoutB to be programmed. + * @retval None + */ +void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_1_PERIPH(I2Cx)); + assert_param(IS_I2C_TIMEOUT(Timeout)); + + /* Get the old register value */ + tmpreg = I2Cx->TIMEOUTR; + + /* Reset I2Cx TIMEOUTB bit [11:0] */ + tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTB); + + /* Set I2Cx TIMEOUTB */ + tmpreg |= (uint32_t)(((uint32_t)Timeout << 16) & I2C_TIMEOUTR_TIMEOUTB) ; + + /* Store the new register value */ + I2Cx->TIMEOUTR = tmpreg; +} + +/** + * @brief Enables or disables I2C PEC calculation. + * @param I2Cx: where x can be 1 to select the I2C peripheral. + * @param NewState: new state of the I2Cx PEC calculation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_1_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable PEC calculation */ + I2Cx->CR1 |= I2C_CR1_PECEN; + } + else + { + /* Disable PEC calculation */ + I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PECEN); + } +} + +/** + * @brief Enables or disables I2C PEC transmission/reception request. + * @param I2Cx: where x can be 1 to select the I2C peripheral. + * @param NewState: new state of the I2Cx PEC request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_1_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable PEC transmission/reception request */ + I2Cx->CR1 |= I2C_CR2_PECBYTE; + } + else + { + /* Disable PEC transmission/reception request */ + I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR2_PECBYTE); + } +} + +/** + * @brief Returns the I2C PEC. + * @param I2Cx: where x can be 1 to select the I2C peripheral. + * @retval The value of the PEC . + */ +uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_1_PERIPH(I2Cx)); + + /* Return the slave matched address in the SR1 register */ + return (uint8_t)((uint32_t)I2Cx->PECR & I2C_PECR_PEC); +} + +/** + * @} + */ + + +/** @defgroup I2C_Group4 I2C registers management functions + * @brief I2C registers management functions + * +@verbatim + =============================================================================== + ##### I2C registers management functions ##### + =============================================================================== + [..] This section provides a functions that allow user the management of + I2C registers. + +@endverbatim + * @{ + */ + + /** + * @brief Reads the specified I2C register and returns its value. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_Register: specifies the register to read. + * This parameter can be one of the following values: + * @arg I2C_Register_CR1: CR1 register. + * @arg I2C_Register_CR2: CR2 register. + * @arg I2C_Register_OAR1: OAR1 register. + * @arg I2C_Register_OAR2: OAR2 register. + * @arg I2C_Register_TIMINGR: TIMING register. + * @arg I2C_Register_TIMEOUTR: TIMEOUTR register. + * @arg I2C_Register_ISR: ISR register. + * @arg I2C_Register_ICR: ICR register. + * @arg I2C_Register_PECR: PECR register. + * @arg I2C_Register_RXDR: RXDR register. + * @arg I2C_Register_TXDR: TXDR register. + * @retval The value of the read register. + */ +uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_REGISTER(I2C_Register)); + + tmp = (uint32_t)I2Cx; + tmp += I2C_Register; + + /* Return the selected register value */ + return (*(__IO uint32_t *) tmp); +} + +/** + * @} + */ + +/** @defgroup I2C_Group5 Data transfers management functions + * @brief Data transfers management functions + * +@verbatim + =============================================================================== + ##### Data transfers management functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage + the I2C data transfers. + + [..] The read access of the I2C_RXDR register can be done using + the I2C_ReceiveData() function and returns the received value. + Whereas a write access to the I2C_TXDR can be done using I2C_SendData() + function and stores the written data into TXDR. +@endverbatim + * @{ + */ + +/** + * @brief Sends a data byte through the I2Cx peripheral. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param Data: Byte to be transmitted.. + * @retval None + */ +void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Write in the DR register the data to be sent */ + I2Cx->TXDR = (uint8_t)Data; +} + +/** + * @brief Returns the most recent received data by the I2Cx peripheral. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @retval The value of the received data. + */ +uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Return the data in the DR register */ + return (uint8_t)I2Cx->RXDR; +} + +/** + * @} + */ + + +/** @defgroup I2C_Group6 DMA transfers management functions + * @brief DMA transfers management functions + * +@verbatim + =============================================================================== + ##### DMA transfers management functions ##### + =============================================================================== + [..] This section provides two functions that can be used only in DMA mode. + [..] In DMA Mode, the I2C communication can be managed by 2 DMA Channel + requests: + (#) I2C_DMAReq_Tx: specifies the Tx buffer DMA transfer request. + (#) I2C_DMAReq_Rx: specifies the Rx buffer DMA transfer request. + [..] In this Mode it is advised to use the following function: + (+) I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState); +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the I2C DMA interface. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_DMAReq: specifies the I2C DMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2C_DMAReq_Tx: Tx DMA transfer request + * @arg I2C_DMAReq_Rx: Rx DMA transfer request + * @param NewState: new state of the selected I2C DMA transfer request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_I2C_DMA_REQ(I2C_DMAReq)); + + if (NewState != DISABLE) + { + /* Enable the selected I2C DMA requests */ + I2Cx->CR1 |= I2C_DMAReq; + } + else + { + /* Disable the selected I2C DMA requests */ + I2Cx->CR1 &= (uint32_t)~I2C_DMAReq; + } +} +/** + * @} + */ + + +/** @defgroup I2C_Group7 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + [..] This section provides functions allowing to configure the I2C Interrupts + sources and check or clear the flags or pending bits status. + The user should identify which mode will be used in his application to manage + the communication: Polling mode, Interrupt mode or DMA mode(refer I2C_Group6). + + *** Polling Mode *** + ==================== + [..] In Polling Mode, the I2C communication can be managed by 15 flags: + (#) I2C_FLAG_TXE: to indicate the status of Transmit data register empty flag. + (#) I2C_FLAG_TXIS: to indicate the status of Transmit interrupt status flag . + (#) I2C_FLAG_RXNE: to indicate the status of Receive data register not empty flag. + (#) I2C_FLAG_ADDR: to indicate the status of Address matched flag (slave mode). + (#) I2C_FLAG_NACKF: to indicate the status of NACK received flag. + (#) I2C_FLAG_STOPF: to indicate the status of STOP detection flag. + (#) I2C_FLAG_TC: to indicate the status of Transfer complete flag(master mode). + (#) I2C_FLAG_TCR: to indicate the status of Transfer complete reload flag. + (#) I2C_FLAG_BERR: to indicate the status of Bus error flag. + (#) I2C_FLAG_ARLO: to indicate the status of Arbitration lost flag. + (#) I2C_FLAG_OVR: to indicate the status of Overrun/Underrun flag. + (#) I2C_FLAG_PECERR: to indicate the status of PEC error in reception flag. + (#) I2C_FLAG_TIMEOUT: to indicate the status of Timeout or Tlow detection flag. + (#) I2C_FLAG_ALERT: to indicate the status of SMBus Alert flag. + (#) I2C_FLAG_BUSY: to indicate the status of Bus busy flag. + + [..] In this Mode it is advised to use the following functions: + (+) FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); + (+) void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); + + [..] + (@)Do not use the BUSY flag to handle each data transmission or reception.It is + better to use the TXIS and RXNE flags instead. + + *** Interrupt Mode *** + ====================== + [..] In Interrupt Mode, the I2C communication can be managed by 7 interrupt sources + and 15 pending bits: + [..] Interrupt Source: + (#) I2C_IT_ERRI: specifies the interrupt source for the Error interrupt. + (#) I2C_IT_TCI: specifies the interrupt source for the Transfer Complete interrupt. + (#) I2C_IT_STOPI: specifies the interrupt source for the Stop Detection interrupt. + (#) I2C_IT_NACKI: specifies the interrupt source for the Not Acknowledge received interrupt. + (#) I2C_IT_ADDRI: specifies the interrupt source for the Address Match interrupt. + (#) I2C_IT_RXI: specifies the interrupt source for the RX interrupt. + (#) I2C_IT_TXI: specifies the interrupt source for the TX interrupt. + + [..] Pending Bits: + (#) I2C_IT_TXIS: to indicate the status of Transmit interrupt status flag. + (#) I2C_IT_RXNE: to indicate the status of Receive data register not empty flag. + (#) I2C_IT_ADDR: to indicate the status of Address matched flag (slave mode). + (#) I2C_IT_NACKF: to indicate the status of NACK received flag. + (#) I2C_IT_STOPF: to indicate the status of STOP detection flag. + (#) I2C_IT_TC: to indicate the status of Transfer complete flag (master mode). + (#) I2C_IT_TCR: to indicate the status of Transfer complete reload flag. + (#) I2C_IT_BERR: to indicate the status of Bus error flag. + (#) I2C_IT_ARLO: to indicate the status of Arbitration lost flag. + (#) I2C_IT_OVR: to indicate the status of Overrun/Underrun flag. + (#) I2C_IT_PECERR: to indicate the status of PEC error in reception flag. + (#) I2C_IT_TIMEOUT: to indicate the status of Timeout or Tlow detection flag. + (#) I2C_IT_ALERT: to indicate the status of SMBus Alert flag. + + [..] In this Mode it is advised to use the following functions: + (+) void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); + (+) ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); + +@endverbatim + * @{ + */ + +/** + * @brief Checks whether the specified I2C flag is set or not. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2C_FLAG_TXE: Transmit data register empty + * @arg I2C_FLAG_TXIS: Transmit interrupt status + * @arg I2C_FLAG_RXNE: Receive data register not empty + * @arg I2C_FLAG_ADDR: Address matched (slave mode) + * @arg I2C_FLAG_NACKF: NACK received flag + * @arg I2C_FLAG_STOPF: STOP detection flag + * @arg I2C_FLAG_TC: Transfer complete (master mode) + * @arg I2C_FLAG_TCR: Transfer complete reload + * @arg I2C_FLAG_BERR: Bus error + * @arg I2C_FLAG_ARLO: Arbitration lost + * @arg I2C_FLAG_OVR: Overrun/Underrun + * @arg I2C_FLAG_PECERR: PEC error in reception + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag + * @arg I2C_FLAG_ALERT: SMBus Alert + * @arg I2C_FLAG_BUSY: Bus busy + * @retval The new state of I2C_FLAG (SET or RESET). + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) +{ + uint32_t tmpreg = 0; + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); + + /* Get the ISR register value */ + tmpreg = I2Cx->ISR; + + /* Get flag status */ + tmpreg &= I2C_FLAG; + + if(tmpreg != 0) + { + /* I2C_FLAG is set */ + bitstatus = SET; + } + else + { + /* I2C_FLAG is reset */ + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the I2Cx's pending flags. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg I2C_FLAG_ADDR: Address matched (slave mode) + * @arg I2C_FLAG_NACKF: NACK received flag + * @arg I2C_FLAG_STOPF: STOP detection flag + * @arg I2C_FLAG_BERR: Bus error + * @arg I2C_FLAG_ARLO: Arbitration lost + * @arg I2C_FLAG_OVR: Overrun/Underrun + * @arg I2C_FLAG_PECERR: PEC error in reception + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag + * @arg I2C_FLAG_ALERT: SMBus Alert + * @retval The new state of I2C_FLAG (SET or RESET). + */ +void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); + + /* Clear the selected flag */ + I2Cx->ICR = I2C_FLAG; + } + +/** + * @brief Checks whether the specified I2C interrupt has occurred or not. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT: specifies the interrupt source to check. + * This parameter can be one of the following values: + * @arg I2C_IT_TXIS: Transmit interrupt status + * @arg I2C_IT_RXNE: Receive data register not empty + * @arg I2C_IT_ADDR: Address matched (slave mode) + * @arg I2C_IT_NACKF: NACK received flag + * @arg I2C_IT_STOPF: STOP detection flag + * @arg I2C_IT_TC: Transfer complete (master mode) + * @arg I2C_IT_TCR: Transfer complete reload + * @arg I2C_IT_BERR: Bus error + * @arg I2C_IT_ARLO: Arbitration lost + * @arg I2C_IT_OVR: Overrun/Underrun + * @arg I2C_IT_PECERR: PEC error in reception + * @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag + * @arg I2C_IT_ALERT: SMBus Alert + * @retval The new state of I2C_IT (SET or RESET). + */ +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT) +{ + uint32_t tmpreg = 0; + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_IT(I2C_IT)); + + /* Get the ISR register value */ + tmpreg = I2Cx->ISR; + + /* Get flag status */ + tmpreg &= I2C_IT; + + if(tmpreg != 0) + { + /* I2C_IT is set */ + bitstatus = SET; + } + else + { + /* I2C_IT is reset */ + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the I2Cx's interrupt pending bits. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg I2C_IT_ADDR: Address matched (slave mode) + * @arg I2C_IT_NACKF: NACK received flag + * @arg I2C_IT_STOPF: STOP detection flag + * @arg I2C_IT_BERR: Bus error + * @arg I2C_IT_ARLO: Arbitration lost + * @arg I2C_IT_OVR: Overrun/Underrun + * @arg I2C_IT_PECERR: PEC error in reception + * @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag + * @arg I2C_IT_ALERT: SMBus Alert + * @retval The new state of I2C_IT (SET or RESET). + */ +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLEAR_IT(I2C_IT)); + + /* Clear the selected flag */ + I2Cx->ICR = I2C_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_iwdg.c b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_iwdg.c new file mode 100644 index 0000000..1da7fdf --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_iwdg.c @@ -0,0 +1,293 @@ +/** + ****************************************************************************** + * @file stm32f0xx_iwdg.c + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Independent watchdog (IWDG) peripheral: + * + Prescaler and Counter configuration + * + IWDG activation + * + Flag management + * + * @verbatim + * + ============================================================================== + ##### IWDG features ##### + ============================================================================== + [..] The IWDG can be started by either software or hardware (configurable + through option byte). + + [..] The IWDG is clocked by its own dedicated low-speed clock (LSI) and + thus stays active even if the main clock fails. + Once the IWDG is started, the LSI is forced ON and cannot be disabled + (LSI cannot be disabled too), and the counter starts counting down from + the reset value of 0xFFF. When it reaches the end of count value (0x000) + a system reset is generated. + The IWDG counter should be reloaded at regular intervals to prevent + an MCU reset. + + [..] The IWDG is implemented in the VDD voltage domain that is still functional + in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). + + [..] IWDGRST flag in RCC_CSR register can be used to inform when a IWDG + reset occurs. + + [..] Min-max timeout value @40KHz (LSI): ~0.1ms / ~28.3s + The IWDG timeout may vary due to LSI frequency dispersion. STM32F0xx + devices provide the capability to measure the LSI frequency (LSI clock + should be seleted as RTC clock which is internally connected to TIM10 CH1 + input capture). The measured value can be used to have an IWDG timeout with + an acceptable accuracy. + For more information, please refer to the STM32F0xx Reference manual. + + ##### How to use this driver ##### + ============================================================================== + [..] This driver allows to use IWDG peripheral with either window option enabled + or disabled. To do so follow one of the two procedures below. + (#) Window option is enabled: + (++) Start the IWDG using IWDG_Enable() function, when the IWDG is used + in software mode (no need to enable the LSI, it will be enabled + by hardware). + (++) Enable write access to IWDG_PR and IWDG_RLR registers using + IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function. + (++) Configure the IWDG prescaler using IWDG_SetPrescaler() function. + (++) Configure the IWDG counter value using IWDG_SetReload() function. + This value will be loaded in the IWDG counter each time the counter + is reloaded, then the IWDG will start counting down from this value. + (++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function. + (++) Configure the IWDG refresh window using IWDG_SetWindowValue() function. + + (#) Window option is disabled: + (++) Enable write access to IWDG_PR and IWDG_RLR registers using + IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function. + (++) Configure the IWDG prescaler using IWDG_SetPrescaler() function. + (++) Configure the IWDG counter value using IWDG_SetReload() function. + This value will be loaded in the IWDG counter each time the counter + is reloaded, then the IWDG will start counting down from this value. + (++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function. + (++) reload the IWDG counter at regular intervals during normal operation + to prevent an MCU reset, using IWDG_ReloadCounter() function. + (++) Start the IWDG using IWDG_Enable() function, when the IWDG is used + in software mode (no need to enable the LSI, it will be enabled + by hardware). + + @endverbatim + * + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_iwdg.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup IWDG + * @brief IWDG driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* ---------------------- IWDG registers bit mask ----------------------------*/ +/* KR register bit mask */ +#define KR_KEY_RELOAD ((uint16_t)0xAAAA) +#define KR_KEY_ENABLE ((uint16_t)0xCCCC) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup IWDG_Private_Functions + * @{ + */ + +/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions + * @brief Prescaler and Counter configuration functions + * +@verbatim + ============================================================================== + ##### Prescaler and Counter configuration functions ##### + ============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. + * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. + * This parameter can be one of the following values: + * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers + * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers + * @retval None + */ +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) +{ + /* Check the parameters */ + assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); + IWDG->KR = IWDG_WriteAccess; +} + +/** + * @brief Sets IWDG Prescaler value. + * @param IWDG_Prescaler: specifies the IWDG Prescaler value. + * This parameter can be one of the following values: + * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 + * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 + * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 + * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 + * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 + * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 + * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 + * @retval None + */ +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); + IWDG->PR = IWDG_Prescaler; +} + +/** + * @brief Sets IWDG Reload value. + * @param Reload: specifies the IWDG Reload value. + * This parameter must be a number between 0 and 0x0FFF. + * @retval None + */ +void IWDG_SetReload(uint16_t Reload) +{ + /* Check the parameters */ + assert_param(IS_IWDG_RELOAD(Reload)); + IWDG->RLR = Reload; +} + +/** + * @brief Reloads IWDG counter with value defined in the reload register + * (write access to IWDG_PR and IWDG_RLR registers disabled). + * @param None + * @retval None + */ +void IWDG_ReloadCounter(void) +{ + IWDG->KR = KR_KEY_RELOAD; +} + + +/** + * @brief Sets the IWDG window value. + * @param WindowValue: specifies the window value to be compared to the downcounter. + * @retval None + */ +void IWDG_SetWindowValue(uint16_t WindowValue) +{ + /* Check the parameters */ + assert_param(IS_IWDG_WINDOW_VALUE(WindowValue)); + IWDG->WINR = WindowValue; +} + +/** + * @} + */ + +/** @defgroup IWDG_Group2 IWDG activation function + * @brief IWDG activation function + * +@verbatim + ============================================================================== + ##### IWDG activation function ##### + ============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). + * @param None. + * @retval None. + */ +void IWDG_Enable(void) +{ + IWDG->KR = KR_KEY_ENABLE; +} + +/** + * @} + */ + +/** @defgroup IWDG_Group3 Flag management function + * @brief Flag management function + * +@verbatim + =============================================================================== + ##### Flag management function ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Checks whether the specified IWDG flag is set or not. + * @param IWDG_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg IWDG_FLAG_PVU: Prescaler Value Update on going + * @arg IWDG_FLAG_RVU: Reload Value Update on going + * @arg IWDG_FLAG_WVU: Counter Window Value Update on going + * @retval The new state of IWDG_FLAG (SET or RESET). + */ +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_IWDG_FLAG(IWDG_FLAG)); + if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_misc.c b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_misc.c new file mode 100644 index 0000000..8c80263 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_misc.c @@ -0,0 +1,169 @@ +/** + ****************************************************************************** + * @file stm32f0xx_misc.c + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file provides all the miscellaneous firmware functions (add-on + * to CMSIS functions). + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_misc.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup MISC + * @brief MISC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup MISC_Private_Functions + * @{ + */ +/** + * +@verbatim + ******************************************************************************* + ##### Interrupts configuration functions ##### + ******************************************************************************* + [..] This section provide functions allowing to configure the NVIC interrupts + (IRQ). The Cortex-M0 exceptions are managed by CMSIS functions. + (#) Enable and Configure the priority of the selected IRQ Channels. + The priority can be 0..3. + + -@- Lower priority values gives higher priority. + -@- Priority Order: + (#@) Lowest priority. + (#@) Lowest hardware priority (IRQn position). + +@endverbatim +*/ + +/** + * @brief Initializes the NVIC peripheral according to the specified + * parameters in the NVIC_InitStruct. + * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + * function should be called before. + * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains + * the configuration information for the specified NVIC peripheral. + * @retval None + */ +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) +{ + uint32_t tmppriority = 0x00; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); + assert_param(IS_NVIC_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPriority)); + + if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + /* Compute the Corresponding IRQ Priority --------------------------------*/ + tmppriority = NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel >> 0x02]; + tmppriority &= (uint32_t)(~(((uint32_t)0xFF) << ((NVIC_InitStruct->NVIC_IRQChannel & 0x03) * 8))); + tmppriority |= (uint32_t)((((uint32_t)NVIC_InitStruct->NVIC_IRQChannelPriority << 6) & 0xFF) << ((NVIC_InitStruct->NVIC_IRQChannel & 0x03) * 8)); + + NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel >> 0x02] = tmppriority; + + /* Enable the Selected IRQ Channels --------------------------------------*/ + NVIC->ISER[0] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } + else + { + /* Disable the Selected IRQ Channels -------------------------------------*/ + NVIC->ICER[0] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } +} + +/** + * @brief Selects the condition for the system to enter low power mode. + * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. + * This parameter can be one of the following values: + * @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend. + * @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request. + * @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit. + * @param NewState: new state of LP condition. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_NVIC_LP(LowPowerMode)); + + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + SCB->SCR |= LowPowerMode; + } + else + { + SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); + } +} + +/** + * @brief Configures the SysTick clock source. + * @param SysTick_CLKSource: specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); + + if (SysTick_CLKSource == SysTick_CLKSource_HCLK) + { + SysTick->CTRL |= SysTick_CLKSource_HCLK; + } + else + { + SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_pwr.c b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_pwr.c new file mode 100644 index 0000000..03ca321 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_pwr.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file stm32f0xx_pwr.c + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Backup Domain Access + * + PVD configuration + * + WakeUp pins configuration + * + Low Power modes configuration + * + Flags management + * + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_pwr.h" +#include "stm32f0xx_rcc.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup PWR + * @brief PWR driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* ------------------ PWR registers bit mask ------------------------ */ + +/* CR register bit mask */ +#define CR_DS_MASK ((uint32_t)0xFFFFFFFC) +#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup PWR_Private_Functions + * @{ + */ + +/** @defgroup PWR_Group1 Backup Domain Access function + * @brief Backup Domain Access function + * +@verbatim + ============================================================================== + ##### Backup Domain Access function ##### + ============================================================================== + + [..] After reset, the Backup Domain Registers (RCC BDCR Register, RTC registers + and RTC backup registers) are protected against possible stray write accesses. + [..] To enable access to Backup domain use the PWR_BackupAccessCmd(ENABLE) function. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the PWR peripheral registers to their default reset values. + * @param None + * @retval None + */ +void PWR_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); +} + +/** + * @brief Enables or disables access to the Backup domain registers. + * @note If the HSE divided by 32 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @param NewState: new state of the access to the Backup domain registers. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_BackupAccessCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Backup Domain Access */ + PWR->CR |= PWR_CR_DBP; + } + else + { + /* Disable the Backup Domain Access */ + PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_DBP); + } +} + +/** + * @} + */ + +/** @defgroup PWR_Group2 PVD configuration functions + * @brief PVD configuration functions + * +@verbatim + ============================================================================== + ##### PVD configuration functions ##### + ============================================================================== + [..] + (+) The PVD is used to monitor the VDD power supply by comparing it to a threshold + selected by the PVD Level (PLS[2:0] bits in the PWR_CR). + (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the + PVD threshold. This event is internally connected to the EXTI line16 + and can generate an interrupt if enabled through the EXTI registers. + (+) The PVD is stopped in Standby mode. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + * @param PWR_PVDLevel: specifies the PVD detection level + * This parameter can be one of the following values: + * @arg PWR_PVDLevel_0: PVD detection level set to 1.9V + * @arg PWR_PVDLevel_1: PVD detection level set to 2.1V + * @arg PWR_PVDLevel_2: PVD detection level set to 2.3V + * @arg PWR_PVDLevel_3: PVD detection level set to 2.5V + * @arg PWR_PVDLevel_4: PVD detection level set to 2.7V + * @arg PWR_PVDLevel_5: PVD detection level set to 2.9V + * @arg PWR_PVDLevel_6: PVD detection level set to 3.1V + * @arg PWR_PVDLevel_7: PVD detection level set to 3.3V + * @retval None + */ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); + + tmpreg = PWR->CR; + + /* Clear PLS[7:5] bits */ + tmpreg &= CR_PLS_MASK; + + /* Set PLS[7:5] bits according to PWR_PVDLevel value */ + tmpreg |= PWR_PVDLevel; + + /* Store the new value */ + PWR->CR = tmpreg; +} + +/** + * @brief Enables or disables the Power Voltage Detector(PVD). + * @param NewState: new state of the PVD. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_PVDCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the PVD */ + PWR->CR |= PWR_CR_PVDE; + } + else + { + /* Disable the PVD */ + PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_PVDE); + } +} + +/** + * @} + */ + +/** @defgroup PWR_Group3 WakeUp pins configuration functions + * @brief WakeUp pins configuration functions + * +@verbatim + ============================================================================== + ##### WakeUp pin configuration functions ##### + ============================================================================== + + (+) WakeUp pins are used to wakeup the system from Standby mode. These pins are + forced in input pull down configuration and are active on rising edges. + (+) There are three WakeUp pins: WakeUp Pin 1 on PA.00 and WakeUp Pin 2 on PC.13. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the WakeUp Pin functionality. + * @param PWR_WakeUpPin: specifies the WakeUpPin. + * This parameter can be: PWR_WakeUpPin_1 or PWR_WakeUpPin_2. + * @param NewState: new state of the WakeUp Pin functionality. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the EWUPx pin */ + PWR->CSR |= PWR_WakeUpPin; + } + else + { + /* Disable the EWUPx pin */ + PWR->CSR &= ~PWR_WakeUpPin; + } +} + +/** + * @} + */ + + +/** @defgroup PWR_Group4 Low Power modes configuration functions + * @brief Low Power modes configuration functions + * +@verbatim + ============================================================================== + ##### Low Power modes configuration functions ##### + ============================================================================== + + [..] The devices feature three low-power modes: + (+) Sleep mode: Cortex-M0 core stopped, peripherals kept running. + (+) Stop mode: all clocks are stopped, regulator running, regulator in low power mode + (+) Standby mode: VCORE domain powered off + + *** Sleep mode *** + ================== + [..] + (+) Entry: + (++) The Sleep mode is entered by executing the WFE() or WFI() instructions. + (+) Exit: + (++) Any peripheral interrupt acknowledged by the nested vectored interrupt + controller (NVIC) can wake up the device from Sleep mode. + + *** Stop mode *** + ================= + [..] In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the HSI, + the HSI14 and the HSE RC oscillators are disabled. Internal SRAM and register + contents are preserved. + The voltage regulator can be configured either in normal or low-power mode. + + (+) Entry: + (++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,) + function with regulator in LowPower or with Regulator ON. + (+) Exit: + (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode + or any internal IPs (I2C, UASRT or CEC) wakeup event. + + *** Standby mode *** + ==================== + [..] The Standby mode allows to achieve the lowest power consumption. It is based + on the Cortex-M0 deepsleep mode, with the voltage regulator disabled. + The VCORE domain is consequently powered off. The PLL, the HSI, the HSI14 + oscillator and the HSE oscillator are also switched off. SRAM and register + contents are lost except for the Backup domain (RTC registers, RTC backup + registers and Standby circuitry). + + [..] The voltage regulator is OFF. + + (+) Entry: + (++) The Standby mode is entered using the PWR_EnterSTANDBYMode() function. + (+) Exit: + (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, + tamper event, time-stamp event, external reset in NRST pin, IWDG reset. + + *** Auto-wakeup (AWU) from low-power mode *** + ============================================= + [..] The MCU can be woken up from low-power mode by an RTC Alarm event, a tamper + event, a time-stamp event, or a comparator event, without depending on an + external interrupt (Auto-wakeup mode). + + (+) RTC auto-wakeup (AWU) from the Stop mode + (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to: + (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt + or Event modes) using the EXTI_Init() function. + (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function + (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() + and RTC_AlarmCmd() functions. + (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it + is necessary to: + (+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt + or Event modes) using the EXTI_Init() function. + (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() + function. + (+++) Configure the RTC to detect the tamper or time stamp event using the + RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() + functions. + + (+) RTC auto-wakeup (AWU) from the Standby mode + (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to: + (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function. + (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() + and RTC_AlarmCmd() functions. + (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it + is necessary to: + (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() + function. + (+++) Configure the RTC to detect the tamper or time stamp event using the + RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() + functions. + + (+) Comparator auto-wakeup (AWU) from the Stop mode + (++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup + event, it is necessary to: + (+++) Configure the EXTI Line 21 for comparator 1 or EXTI Line 22 for comparator 2 + to be sensitive to to the selected edges (falling, rising or falling + and rising) (Interrupt or Event modes) using the EXTI_Init() function. + (+++) Configure the comparator to generate the event. + +@endverbatim + * @{ + */ + +/** + * @brief Enters Sleep mode. + * @note In Sleep mode, all I/O pins keep the same state as in Run mode. + * @param PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction + * @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction + * @retval None + */ +void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry)); + + /* Clear SLEEPDEEP bit of Cortex-M0 System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + + /* Select SLEEP mode entry -------------------------------------------------*/ + if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __WFE(); + } +} + +/** + * @brief Enters STOP mode. + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * @note When exiting Stop mode by issuing an interrupt or a wakeup event, + * the HSI RC oscillator is selected as system clock. + * @note When the voltage regulator operates in low power mode, an additional + * startup delay is incurred when waking up from Stop mode. + * By keeping the internal regulator ON during Stop mode, the consumption + * is higher although the startup time is reduced. + * @param PWR_Regulator: specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_Regulator_ON: STOP mode with regulator ON + * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode + * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction + * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction + * @retval None + */ +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(PWR_Regulator)); + assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); + + /* Select the regulator state in STOP mode ---------------------------------*/ + tmpreg = PWR->CR; + /* Clear PDDS and LPDSR bits */ + tmpreg &= CR_DS_MASK; + + /* Set LPDSR bit according to PWR_Regulator value */ + tmpreg |= PWR_Regulator; + + /* Store the new value */ + PWR->CR = tmpreg; + + /* Set SLEEPDEEP bit of Cortex-M0 System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Select STOP mode entry --------------------------------------------------*/ + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __WFE(); + } + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Enters STANDBY mode. + * @note In Standby mode, all I/O pins are high impedance except for: + * Reset pad (still available) + * RTC_AF1 pin (PC13) if configured for Wakeup pin 2 (WKUP2), tamper, + * time-stamp, RTC Alarm out, or RTC clock calibration out. + * WKUP pin 1 (PA0) if enabled. + * @param None + * @retval None + */ +void PWR_EnterSTANDBYMode(void) +{ + /* Clear Wakeup flag */ + PWR->CR |= PWR_CR_CWUF; + + /* Select STANDBY mode */ + PWR->CR |= PWR_CR_PDDS; + + /* Set SLEEPDEEP bit of Cortex-M0 System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Request Wait For Interrupt */ + __WFI(); +} + +/** + * @} + */ + +/** @defgroup PWR_Group5 Flags management functions + * @brief Flags management functions + * +@verbatim + ============================================================================== + ##### Flags management functions ##### + ============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Checks whether the specified PWR flag is set or not. + * @param PWR_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup + * event was received from the WKUP pin or from the RTC alarm + * (Alarm A or Alarm B), RTC Tamper event or RTC TimeStamp event. + * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the + * system was resumed from StandBy mode. + * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD + * is enabled by the PWR_PVDCmd() function. + * @arg PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag. + * This flag indicates the state of the internal voltage + * reference, VREFINT. + * @retval The new state of PWR_FLAG (SET or RESET). + */ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); + + if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the PWR's pending flags. + * @param PWR_FLAG: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag + * @arg PWR_FLAG_SB: StandBy flag + * @retval None + */ +void PWR_ClearFlag(uint32_t PWR_FLAG) +{ + /* Check the parameters */ + assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); + + PWR->CR |= PWR_FLAG << 2; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_rcc.c b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_rcc.c new file mode 100644 index 0000000..b788037 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_rcc.c @@ -0,0 +1,1555 @@ +/** + ****************************************************************************** + * @file stm32f0xx_rcc.c + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Reset and clock control (RCC) peripheral: + * + Internal/external clocks, PLL, CSS and MCO configuration + * + System, AHB and APB busses clocks configuration + * + Peripheral clocks configuration + * + Interrupts and flags management + * + @verbatim + + =============================================================================== + ##### RCC specific features ##### + =============================================================================== + [..] After reset the device is running from HSI (8 MHz) with Flash 0 WS, + all peripherals are off except internal SRAM, Flash and SWD. + (#) There is no prescaler on High speed (AHB) and Low speed (APB) busses; + all peripherals mapped on these busses are running at HSI speed. + (#) The clock for all peripherals is switched off, except the SRAM and FLASH. + (#) All GPIOs are in input floating state, except the SWD pins which + are assigned to be used for debug purpose. + [..] Once the device started from reset, the user application has to: + (#) Configure the clock source to be used to drive the System clock + (if the application needs higher frequency/performance) + (#) Configure the System clock frequency and Flash settings + (#) Configure the AHB and APB busses prescalers + (#) Enable the clock for the peripheral(s) to be used + (#) Configure the clock source(s) for peripherals which clocks are not + derived from the System clock (ADC, CEC, I2C, USART, RTC and IWDG) + + @endverbatim + + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_rcc.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup RCC + * @brief RCC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* ---------------------- RCC registers mask -------------------------------- */ +/* RCC Flag Mask */ +#define FLAG_MASK ((uint8_t)0x1F) + +/* CR register byte 2 (Bits[23:16]) base address */ +#define CR_BYTE2_ADDRESS ((uint32_t)0x40021002) + +/* CFGR register byte 3 (Bits[31:23]) base address */ +#define CFGR_BYTE3_ADDRESS ((uint32_t)0x40021007) + +/* CIR register byte 1 (Bits[15:8]) base address */ +#define CIR_BYTE1_ADDRESS ((uint32_t)0x40021009) + +/* CIR register byte 2 (Bits[23:16]) base address */ +#define CIR_BYTE2_ADDRESS ((uint32_t)0x4002100A) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup RCC_Private_Functions + * @{ + */ + +/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions + * @brief Internal and external clocks, PLL, CSS and MCO configuration functions + * +@verbatim + =============================================================================== + ##### Internal-external clocks, PLL, CSS and MCO configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to configure the internal/external clocks, + PLL, CSS and MCO. + (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly + or through the PLL as System clock source. + The HSI clock can be used also to clock the USART, I2C and CEC peripherals. + (#) HSI14 (high-speed internal for ADC), 14 MHz factory-trimmed RC used to clock + the ADC peripheral. + (#) LSI (low-speed internal), 40 KHz low consumption RC used as IWDG and/or RTC + clock source. + (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or + through the PLL as System clock source. Can be used also as RTC clock source. + (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + LSE can be used also to clock the USART and CEC peripherals. + (#) PLL (clocked by HSI or HSE), for System clock. + (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs + (HSE used directly or through PLL as System clock source), the System clock + is automatically switched to HSI and an interrupt is generated if enabled. + The interrupt is linked to the Cortex-M0 NMI (Non-Maskable Interrupt) + exception vector. + (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSI14, LSI, + HSE, LSE or PLL (divided by 2) clock on PA8 pin. + +@endverbatim + * @{ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * @note HSI ON and used as system clock source + * @note HSI14, HSE and PLL OFF + * @note AHB, APB prescaler set to 1. + * @note CSS and MCO OFF + * @note All interrupts disabled + * @note However, this function doesn't modify the configuration of the + * @note Peripheral clocks + * @note LSI, LSE and RTC clocks + * @param None + * @retval None + */ +void RCC_DeInit(void) +{ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */ + RCC->CFGR &= (uint32_t)0xF8FFB80C; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ + RCC->CFGR &= (uint32_t)0xFFC0FFFF; + + /* Reset PREDIV1[3:0] bits */ + RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; + + /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFFFEAC; + + /* Reset HSI14 bit */ + RCC->CR2 &= (uint32_t)0xFFFFFFFE; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; +} + +/** + * @brief Configures the External High Speed oscillator (HSE). + * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application + * software should wait on HSERDY flag to be set indicating that HSE clock + * is stable and can be used to clock the PLL and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note This function resets the CSSON bit, so if the Clock security system(CSS) + * was previously enabled you have to enable it again after calling this + * function. + * @param RCC_HSE: specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg RCC_HSE_ON: turn ON the HSE oscillator + * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock + * @retval None + */ +void RCC_HSEConfig(uint8_t RCC_HSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_HSE)); + + /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ + *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE_OFF; + + /* Set the new HSE configuration -------------------------------------------*/ + *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE; + +} + +/** + * @brief Waits for HSE start-up. + * @note This function waits on HSERDY flag to be set and return SUCCESS if + * this flag is set, otherwise returns ERROR if the timeout is reached + * and this flag is not set. The timeout value is defined by the constant + * HSE_STARTUP_TIMEOUT in stm32f0xx.h file. You can tailor it depending + * on the HSE crystal used in your application. + * - The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @param None + * @retval An ErrorStatus enumeration value: + * - SUCCESS: HSE oscillator is stable and ready to use + * - ERROR: HSE oscillator not yet ready + */ +ErrorStatus RCC_WaitForHSEStartUp(void) +{ + __IO uint32_t StartUpCounter = 0; + ErrorStatus status = ERROR; + FlagStatus HSEStatus = RESET; + + /* Wait till HSE is ready and if timeout is reached exit */ + do + { + HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); + StartUpCounter++; + } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); + + if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + return (status); +} + +/** + * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * Refer to the Application Note AN3300 for more details on how to + * calibrate the HSI. + * @param HSICalibrationValue: specifies the HSI calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + * @retval None + */ +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue)); + + tmpreg = RCC->CR; + + /* Clear HSITRIM[4:0] bits */ + tmpreg &= ~RCC_CR_HSITRIM; + + /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ + tmpreg |= (uint32_t)HSICalibrationValue << 3; + + /* Store the new value */ + RCC->CR = tmpreg; +} + +/** + * @brief Enables or disables the Internal High Speed oscillator (HSI). + * @note After enabling the HSI, the application software should wait on + * HSIRDY flag to be set indicating that HSI clock is stable and can + * be used to clock the PLL and/or system clock. + * @note HSI can not be stopped if it is used directly or through the PLL + * as system clock. In this case, you have to select another source + * of the system clock then stop the HSI. + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * @param NewState: new state of the HSI. + * This parameter can be: ENABLE or DISABLE. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + * @retval None + */ +void RCC_HSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->CR |= RCC_CR_HSION; + } + else + { + RCC->CR &= ~RCC_CR_HSION; + } +} + +/** + * @brief Adjusts the Internal High Speed oscillator for ADC (HSI14) + * calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * Refer to the Application Note AN3300 for more details on how to + * calibrate the HSI14. + * @param HSI14CalibrationValue: specifies the HSI14 calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + * @retval None + */ +void RCC_AdjustHSI14CalibrationValue(uint8_t HSI14CalibrationValue) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_HSI14_CALIBRATION_VALUE(HSI14CalibrationValue)); + + tmpreg = RCC->CR2; + + /* Clear HSI14TRIM[4:0] bits */ + tmpreg &= ~RCC_CR2_HSI14TRIM; + + /* Set the HSITRIM14[4:0] bits according to HSI14CalibrationValue value */ + tmpreg |= (uint32_t)HSI14CalibrationValue << 3; + + /* Store the new value */ + RCC->CR2 = tmpreg; +} + +/** + * @brief Enables or disables the Internal High Speed oscillator for ADC (HSI14). + * @note After enabling the HSI14, the application software should wait on + * HSIRDY flag to be set indicating that HSI clock is stable and can + * be used to clock the ADC. + * @note The HSI14 is stopped by hardware when entering STOP and STANDBY modes. + * @param NewState: new state of the HSI14. + * This parameter can be: ENABLE or DISABLE. + * @note When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator + * clock cycles. + * @retval None + */ +void RCC_HSI14Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->CR2 |= RCC_CR2_HSI14ON; + } + else + { + RCC->CR2 &= ~RCC_CR2_HSI14ON; + } +} + +/** + * @brief Enables or disables the Internal High Speed oscillator request from ADC. + * @param NewState: new state of the HSI14 ADC request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_HSI14ADCRequestCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->CR2 &= ~RCC_CR2_HSI14DIS; + } + else + { + RCC->CR2 |= RCC_CR2_HSI14DIS; + } +} + +/** + * @brief Configures the External Low Speed oscillator (LSE). + * @note As the LSE is in the Backup domain and write access is denied to this + * domain after reset, you have to enable write access using + * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @param RCC_LSE: specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg RCC_LSE_ON: turn ON the LSE oscillator + * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock + * @retval None + */ +void RCC_LSEConfig(uint32_t RCC_LSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_LSE)); + + /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ + /* Reset LSEON bit */ + RCC->BDCR &= ~(RCC_BDCR_LSEON); + + /* Reset LSEBYP bit */ + RCC->BDCR &= ~(RCC_BDCR_LSEBYP); + + /* Configure LSE */ + RCC->BDCR |= RCC_LSE; +} + +/** + * @brief Configures the External Low Speed oscillator (LSE) drive capability. + * @param RCC_LSEDrive: specifies the new state of the LSE drive capability. + * This parameter can be one of the following values: + * @arg RCC_LSEDrive_Low: LSE oscillator low drive capability. + * @arg RCC_LSEDrive_MediumLow: LSE oscillator medium low drive capability. + * @arg RCC_LSEDrive_MediumHigh: LSE oscillator medium high drive capability. + * @arg RCC_LSEDrive_High: LSE oscillator high drive capability. + * @retval None + */ +void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSE_DRIVE(RCC_LSEDrive)); + + /* Clear LSEDRV[1:0] bits */ + RCC->BDCR &= ~(RCC_BDCR_LSEDRV); + + /* Set the LSE Drive */ + RCC->BDCR |= RCC_LSEDrive; +} + +/** + * @brief Enables or disables the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + * @note LSI can not be disabled if the IWDG is running. + * @param NewState: new state of the LSI. + * This parameter can be: ENABLE or DISABLE. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + * @retval None + */ +void RCC_LSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->CSR |= RCC_CSR_LSION; + } + else + { + RCC->CSR &= ~RCC_CSR_LSION; + } +} + +/** + * @brief Configures the PLL clock source and multiplication factor. + * @note This function must be used only when the PLL is disabled. + * + * @param RCC_PLLSource: specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock selected as PLL clock source + * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry + * @note The minimum input clock frequency for PLL is 2 MHz (when using HSE as + * PLL source). + * + * @param RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock + * This parameter can be RCC_PLLMul_x where x:[2,16] + * + * @retval None + */ +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) +{ + /* Check the parameters */ + assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_PLLMul)); + + /* Clear PLL Source [16] and Multiplier [21:18] bits */ + RCC->CFGR &= ~(RCC_CFGR_PLLMULL | RCC_CFGR_PLLSRC); + + /* Set the PLL Source and Multiplier */ + RCC->CFGR |= (uint32_t)(RCC_PLLSource | RCC_PLLMul); +} + +/** + * @brief Enables or disables the PLL. + * @note - After enabling the PLL, the application software should wait on + * PLLRDY flag to be set indicating that PLL clock is stable and can + * be used as system clock source. + * - The PLL can not be disabled if it is used as system clock source + * - The PLL is disabled by hardware when entering STOP and STANDBY modes. + * @param NewState: new state of the PLL. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLLCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->CR |= RCC_CR_PLLON; + } + else + { + RCC->CR &= ~RCC_CR_PLLON; + } +} + +/** + * @brief Configures the PREDIV1 division factor. + * @note This function must be used only when the PLL is disabled. + * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor. + * This parameter can be RCC_PREDIV1_Divx where x:[1,16] + * @retval None + */ +void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div)); + + tmpreg = RCC->CFGR2; + /* Clear PREDIV1[3:0] bits */ + tmpreg &= ~(RCC_CFGR2_PREDIV1); + /* Set the PREDIV1 division factor */ + tmpreg |= RCC_PREDIV1_Div; + /* Store the new value */ + RCC->CFGR2 = tmpreg; +} + +/** + * @brief Enables or disables the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M0 NMI (Non-Maskable Interrupt) exception vector. + * @param NewState: new state of the Clock Security System. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_ClockSecuritySystemCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->CR |= RCC_CR_CSSON; + } + else + { + RCC->CR &= ~RCC_CR_CSSON; + } +} + +/** + * @brief Selects the clock source to output on MCO pin (PA8). + * @note PA8 should be configured in alternate function mode. + * @param RCC_MCOSource: specifies the clock source to output. + * This parameter can be one of the following values: + * @arg RCC_MCOSource_NoClock: No clock selected. + * @arg RCC_MCOSource_HSI14: HSI14 oscillator clock selected. + * @arg RCC_MCOSource_LSI: LSI oscillator clock selected. + * @arg RCC_MCOSource_LSE: LSE oscillator clock selected. + * @arg RCC_MCOSource_SYSCLK: System clock selected. + * @arg RCC_MCOSource_HSI: HSI oscillator clock selected. + * @arg RCC_MCOSource_HSE: HSE oscillator clock selected. + * @arg RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected. + * @retval None + */ +void RCC_MCOConfig(uint8_t RCC_MCOSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource)); + + /* Select MCO clock source and prescaler */ + *(__IO uint8_t *) CFGR_BYTE3_ADDRESS = RCC_MCOSource; +} + +/** + * @} + */ + +/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions + * @brief System, AHB and APB busses clocks configuration functions + * +@verbatim + =============================================================================== + ##### System, AHB and APB busses clocks configuration functions ##### + =============================================================================== + + [..] This section provide functions allowing to configure the System, AHB and + APB busses clocks. + (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, + HSE and PLL. + The AHB clock (HCLK) is derived from System clock through configurable prescaler + and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA and GPIO). + and APB (PCLK) clocks are derived from AHB clock through + configurable prescalers and used to clock the peripherals mapped on these busses. + You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks. + + -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: + (+@) The ADC clock which is derived from HSI14 or APB (APB divided by a + programmable prescaler: 2 or 4). + (+@) The CEC clock which is derived from LSE or HSI divided by 244. + (+@) The I2C clock which is derived from HSI or system clock (SYSCLK). + (+@) The USART clock which is derived from HSI, system clock (SYSCLK), APB or LSE. + (+@) The RTC/LCD clock which is derived from the LSE, LSI or 2 MHz HSE_RTC (HSE + divided by a programmable prescaler). + The System clock (SYSCLK) frequency must be higher or equal to the RTC/LCD + clock frequency. + (+@) IWDG clock which is always the LSI clock. + + (#) The maximum frequency of the SYSCLK, HCLK and PCLK is 48 MHz. + Depending on the maximum frequency, the FLASH wait states (WS) should be + adapted accordingly: + +--------------------------------------------- + + | Wait states | HCLK clock frequency (MHz) | + |---------------|------------------------------| + |0WS(1CPU cycle)| 0 < HCLK <= 24 | + |---------------|------------------------------| + |1WS(2CPU cycle)| 24 < HCLK <= 48 | + +----------------------------------------------+ + + (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and + prefetch is disabled. + + [..] It is recommended to use the following software sequences to tune the number + of wait states needed to access the Flash memory with the CPU frequency (HCLK). + (+) Increasing the CPU frequency + (++) Program the Flash Prefetch buffer, using "FLASH_PrefetchBufferCmd(ENABLE)" + function + (++) Check that Flash Prefetch buffer activation is taken into account by + reading FLASH_ACR using the FLASH_GetPrefetchBufferStatus() function + (++) Program Flash WS to 1, using "FLASH_SetLatency(FLASH_Latency_1)" function + (++) Check that the new number of WS is taken into account by reading FLASH_ACR + (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function + (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function + (++) Check that the new CPU clock source is taken into account by reading + the clock source status, using "RCC_GetSYSCLKSource()" function + (+) Decreasing the CPU frequency + (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function + (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function + (++) Check that the new CPU clock source is taken into account by reading + the clock source status, using "RCC_GetSYSCLKSource()" function + (++) Program the new number of WS, using "FLASH_SetLatency()" function + (++) Check that the new number of WS is taken into account by reading FLASH_ACR + (++) Disable the Flash Prefetch buffer using "FLASH_PrefetchBufferCmd(DISABLE)" + function + (++) Check that Flash Prefetch buffer deactivation is taken into account by reading FLASH_ACR + using the FLASH_GetPrefetchBufferStatus() function. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the system clock (SYSCLK). + * @note The HSI is used (enabled by hardware) as system clock source after + * startup from Reset, wake-up from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after startup delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source will be ready. + * You can use RCC_GetSYSCLKSource() function to know which clock is + * currently used as system clock source. + * @param RCC_SYSCLKSource: specifies the clock source used as system clock source + * This parameter can be one of the following values: + * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source + * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source + * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source + * @retval None + */ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); + + tmpreg = RCC->CFGR; + + /* Clear SW[1:0] bits */ + tmpreg &= ~RCC_CFGR_SW; + + /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ + tmpreg |= RCC_SYSCLKSource; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Returns the clock source used as system clock. + * @param None + * @retval The clock source used as system clock. The returned value can be one + * of the following values: + * - 0x00: HSI used as system clock + * - 0x04: HSE used as system clock + * - 0x08: PLL used as system clock + */ +uint8_t RCC_GetSYSCLKSource(void) +{ + return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS)); +} + +/** + * @brief Configures the AHB clock (HCLK). + * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from + * the system clock (SYSCLK). + * This parameter can be one of the following values: + * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK + * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 + * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 + * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 + * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 + * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 + * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 + * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 + * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 + * @retval None + */ +void RCC_HCLKConfig(uint32_t RCC_SYSCLK) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_HCLK(RCC_SYSCLK)); + + tmpreg = RCC->CFGR; + + /* Clear HPRE[3:0] bits */ + tmpreg &= ~RCC_CFGR_HPRE; + + /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ + tmpreg |= RCC_SYSCLK; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Configures the APB clock (PCLK). + * @param RCC_HCLK: defines the APB clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_Div1: APB clock = HCLK + * @arg RCC_HCLK_Div2: APB clock = HCLK/2 + * @arg RCC_HCLK_Div4: APB clock = HCLK/4 + * @arg RCC_HCLK_Div8: APB clock = HCLK/8 + * @arg RCC_HCLK_Div16: APB clock = HCLK/16 + * @retval None + */ +void RCC_PCLKConfig(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK)); + + tmpreg = RCC->CFGR; + + /* Clear PPRE[2:0] bits */ + tmpreg &= ~RCC_CFGR_PPRE; + + /* Set PPRE[2:0] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Configures the ADC clock (ADCCLK). + * @param RCC_ADCCLK: defines the ADC clock source. This clock is derived + * from the HSI14 or APB clock (PCLK). + * This parameter can be one of the following values: + * @arg RCC_ADCCLK_HSI14: ADC clock = HSI14 (14MHz) + * @arg RCC_ADCCLK_PCLK_Div2: ADC clock = PCLK/2 + * @arg RCC_ADCCLK_PCLK_Div4: ADC clock = PCLK/4 + * @retval None + */ +void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK) +{ + /* Check the parameters */ + assert_param(IS_RCC_ADCCLK(RCC_ADCCLK)); + + /* Clear ADCPRE bit */ + RCC->CFGR &= ~RCC_CFGR_ADCPRE; + /* Set ADCPRE bits according to RCC_PCLK value */ + RCC->CFGR |= RCC_ADCCLK & 0xFFFF; + + /* Clear ADCSW bit */ + RCC->CFGR3 &= ~RCC_CFGR3_ADCSW; + /* Set ADCSW bits according to RCC_ADCCLK value */ + RCC->CFGR3 |= RCC_ADCCLK >> 16; +} + +/** + * @brief Configures the CEC clock (CECCLK). + * @param RCC_CECCLK: defines the CEC clock source. This clock is derived + * from the HSI or LSE clock. + * This parameter can be one of the following values: + * @arg RCC_CECCLK_HSI_Div244: CEC clock = HSI/244 (32768Hz) + * @arg RCC_CECCLK_LSE: CEC clock = LSE + * @retval None + */ +void RCC_CECCLKConfig(uint32_t RCC_CECCLK) +{ + /* Check the parameters */ + assert_param(IS_RCC_CECCLK(RCC_CECCLK)); + + /* Clear CECSW bit */ + RCC->CFGR3 &= ~RCC_CFGR3_CECSW; + /* Set CECSW bits according to RCC_CECCLK value */ + RCC->CFGR3 |= RCC_CECCLK; +} + +/** + * @brief Configures the I2C1 clock (I2C1CLK). + * @param RCC_I2CCLK: defines the I2C1 clock source. This clock is derived + * from the HSI or System clock. + * This parameter can be one of the following values: + * @arg RCC_I2C1CLK_HSI: I2C1 clock = HSI + * @arg RCC_I2C1CLK_SYSCLK: I2C1 clock = System Clock + * @retval None + */ +void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK) +{ + /* Check the parameters */ + assert_param(IS_RCC_I2CCLK(RCC_I2CCLK)); + + /* Clear I2CSW bit */ + RCC->CFGR3 &= ~RCC_CFGR3_I2C1SW; + /* Set I2CSW bits according to RCC_I2CCLK value */ + RCC->CFGR3 |= RCC_I2CCLK; +} + +/** + * @brief Configures the USART1 clock (USART1CLK). + * @param RCC_USARTCLK: defines the USART1 clock source. This clock is derived + * from the HSI or System clock. + * This parameter can be one of the following values: + * @arg RCC_USART1CLK_PCLK: USART1 clock = APB Clock (PCLK) + * @arg RCC_USART1CLK_SYSCLK: USART1 clock = System Clock + * @arg RCC_USART1CLK_LSE: USART1 clock = LSE Clock + * @arg RCC_USART1CLK_HSI: USART1 clock = HSI Clock + * @retval None + */ +void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK) +{ + /* Check the parameters */ + assert_param(IS_RCC_USARTCLK(RCC_USARTCLK)); + + /* Clear USARTSW[1:0] bit */ + RCC->CFGR3 &= ~RCC_CFGR3_USART1SW; + /* Set USARTSW bits according to RCC_USARTCLK value */ + RCC->CFGR3 |= RCC_USARTCLK; +} + +/** + * @brief Returns the frequencies of the System, AHB and APB busses clocks. + * @note The frequency returned by this function is not the real frequency + * in the chip. It is calculated based on the predefined constant and + * the source selected by RCC_SYSCLKConfig(): + * + * @note If SYSCLK source is HSI, function returns constant HSI_VALUE(*) + * + * @note If SYSCLK source is HSE, function returns constant HSE_VALUE(**) + * + * @note If SYSCLK source is PLL, function returns constant HSE_VALUE(**) + * or HSI_VALUE(*) multiplied by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature, refer to RCC_AdjustHSICalibrationValue(). + * + * (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * return wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold + * the clocks frequencies. + * + * @note This function can be used by the user application to compute the + * baudrate for the communication peripherals or configure other parameters. + * @note Each time SYSCLK, HCLK and/or PCLK clock changes, this function + * must be called to update the structure's field. Otherwise, any + * configuration based on this function will be incorrect. + * + * @retval None + */ +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0, presc = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull; + } + else + { + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; + } + break; + default: /* HSI used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + } + /* Compute HCLK, PCLK clocks frequencies -----------------------------------*/ + /* Get HCLK prescaler */ + tmp = RCC->CFGR & RCC_CFGR_HPRE; + tmp = tmp >> 4; + presc = APBAHBPrescTable[tmp]; + /* HCLK clock frequency */ + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; + + /* Get PCLK prescaler */ + tmp = RCC->CFGR & RCC_CFGR_PPRE; + tmp = tmp >> 8; + presc = APBAHBPrescTable[tmp]; + /* PCLK clock frequency */ + RCC_Clocks->PCLK_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + + /* ADCCLK clock frequency */ + if((RCC->CFGR3 & RCC_CFGR3_ADCSW) != RCC_CFGR3_ADCSW) + { + /* ADC Clock is HSI14 Osc. */ + RCC_Clocks->ADCCLK_Frequency = HSI14_VALUE; + } + else + { + if((RCC->CFGR & RCC_CFGR_ADCPRE) != RCC_CFGR_ADCPRE) + { + /* ADC Clock is derived from PCLK/2 */ + RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK_Frequency >> 1; + } + else + { + /* ADC Clock is derived from PCLK/4 */ + RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK_Frequency >> 2; + } + + } + + /* CECCLK clock frequency */ + if((RCC->CFGR3 & RCC_CFGR3_CECSW) != RCC_CFGR3_CECSW) + { + /* CEC Clock is HSI/256 */ + RCC_Clocks->CECCLK_Frequency = HSI_VALUE / 244; + } + else + { + /* CECC Clock is LSE Osc. */ + RCC_Clocks->CECCLK_Frequency = LSE_VALUE; + } + + /* I2C1CLK clock frequency */ + if((RCC->CFGR3 & RCC_CFGR3_I2C1SW) != RCC_CFGR3_I2C1SW) + { + /* I2C1 Clock is HSI Osc. */ + RCC_Clocks->I2C1CLK_Frequency = HSI_VALUE; + } + else + { + /* I2C1 Clock is System Clock */ + RCC_Clocks->I2C1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency; + } + + /* USART1CLK clock frequency */ + if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == 0x0) + { + /* USART1 Clock is PCLK */ + RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->PCLK_Frequency; + } + else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_0) + { + /* USART1 Clock is System Clock */ + RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency; + } + else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_1) + { + /* USART1 Clock is LSE Osc. */ + RCC_Clocks->USART1CLK_Frequency = LSE_VALUE; + } + else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW) + { + /* USART1 Clock is HSI Osc. */ + RCC_Clocks->USART1CLK_Frequency = HSI_VALUE; + } + +} + + +/** + * @} + */ + +/** @defgroup RCC_Group3 Peripheral clocks configuration functions + * @brief Peripheral clocks configuration functions + * +@verbatim + =============================================================================== + #####Peripheral clocks configuration functions ##### + =============================================================================== + + [..] This section provide functions allowing to configure the Peripheral clocks. + (#) The RTC clock which is derived from the LSE, LSI or HSE_Div32 (HSE + divided by 32). + (#) After restart from Reset or wakeup from STANDBY, all peripherals are off + except internal SRAM, Flash and SWD. Before to start using a peripheral you + have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd(), + RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions. + (#) To reset the peripherals configuration (to the default state after device reset) + you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and + RCC_APB1PeriphResetCmd() functions. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using PWR_BackupAccessCmd(ENABLE) function before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it can't be changed unless the RTC + * is reset using RCC_BackupResetCmd function, or by a Power On Reset (POR) + * + * @param RCC_RTCCLKSource: specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock + * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock + * @arg RCC_RTCCLKSource_HSE_Div32: HSE divided by 32 selected as RTC clock + * + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wakeup source. + * However, when the HSE clock is used as RTC clock source, the RTC + * cannot be used in STOP and STANDBY modes. + * + * @note The maximum input clock frequency for RTC is 2MHz (when using HSE as + * RTC clock source). + * + * @retval None + */ +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); + + /* Select the RTC clock source */ + RCC->BDCR |= RCC_RTCCLKSource; +} + +/** + * @brief Enables or disables the RTC clock. + * @note This function must be used only after the RTC clock source was selected + * using the RCC_RTCCLKConfig function. + * @param NewState: new state of the RTC clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_RTCCLKCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->BDCR |= RCC_BDCR_RTCEN; + } + else + { + RCC->BDCR &= ~RCC_BDCR_RTCEN; + } +} + +/** + * @brief Forces or releases the Backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_BDCR register. + * @param NewState: new state of the Backup domain reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_BackupResetCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->BDCR |= RCC_BDCR_BDRST; + } + else + { + RCC->BDCR &= ~RCC_BDCR_BDRST; + } +} + +/** + * @brief Enables or disables the AHB peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_AHBPeriph_GPIOA: GPIOA clock + * @arg RCC_AHBPeriph_GPIOB: GPIOB clock + * @arg RCC_AHBPeriph_GPIOC: GPIOC clock + * @arg RCC_AHBPeriph_GPIOD: GPIOD clock + * @arg RCC_AHBPeriph_GPIOF: GPIOF clock + * @arg RCC_AHBPeriph_TS: TS clock + * @arg RCC_AHBPeriph_CRC: CRC clock + * @arg RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode) + * @arg RCC_AHBPeriph_SRAM: SRAM clock + * @arg RCC_AHBPeriph_DMA1: DMA1 clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHBENR |= RCC_AHBPeriph; + } + else + { + RCC->AHBENR &= ~RCC_AHBPeriph; + } +} + +/** + * @brief Enables or disables the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock + * @arg RCC_APB2Periph_ADC1: ADC1 clock + * @arg RCC_APB2Periph_TIM1: TIM1 clock + * @arg RCC_APB2Periph_SPI1: SPI1 clock + * @arg RCC_APB2Periph_USART1: USART1 clock + * @arg RCC_APB2Periph_TIM15: TIM15 clock + * @arg RCC_APB2Periph_TIM16: TIM16 clock + * @arg RCC_APB2Periph_TIM17: TIM17 clock + * @arg RCC_APB2Periph_DBGMCU: DBGMCU clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB2ENR |= RCC_APB2Periph; + } + else + { + RCC->APB2ENR &= ~RCC_APB2Periph; + } +} + +/** + * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2: TIM2 clock + * @arg RCC_APB1Periph_TIM3: TIM3 clock + * @arg RCC_APB1Periph_TIM6: TIM6 clock + * @arg RCC_APB1Periph_TIM14: TIM14 clock + * @arg RCC_APB1Periph_WWDG: WWDG clock + * @arg RCC_APB1Periph_SPI2: SPI2 clock + * @arg RCC_APB1Periph_USART2: USART2 clock + * @arg RCC_APB1Periph_I2C1: I2C1 clock + * @arg RCC_APB1Periph_I2C2: I2C2 clock + * @arg RCC_APB1Periph_PWR: PWR clock + * @arg RCC_APB1Periph_DAC: DAC clock + * @arg RCC_APB1Periph_CEC: CEC clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB1ENR |= RCC_APB1Periph; + } + else + { + RCC->APB1ENR &= ~RCC_APB1Periph; + } +} + +/** + * @brief Forces or releases AHB peripheral reset. + * @param RCC_AHBPeriph: specifies the AHB peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_AHBPeriph_GPIOA: GPIOA clock + * @arg RCC_AHBPeriph_GPIOB: GPIOB clock + * @arg RCC_AHBPeriph_GPIOC: GPIOC clock + * @arg RCC_AHBPeriph_GPIOD: GPIOD clock + * @arg RCC_AHBPeriph_GPIOF: GPIOF clock + * @arg RCC_AHBPeriph_TS: TS clock + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB_RST_PERIPH(RCC_AHBPeriph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHBRSTR |= RCC_AHBPeriph; + } + else + { + RCC->AHBRSTR &= ~RCC_AHBPeriph; + } +} + +/** + * @brief Forces or releases High Speed APB (APB2) peripheral reset. + * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock + * @arg RCC_APB2Periph_ADC1: ADC1 clock + * @arg RCC_APB2Periph_TIM1: TIM1 clock + * @arg RCC_APB2Periph_SPI1: SPI1 clock + * @arg RCC_APB2Periph_USART1: USART1 clock + * @arg RCC_APB2Periph_TIM15: TIM15 clock + * @arg RCC_APB2Periph_TIM16: TIM16 clock + * @arg RCC_APB2Periph_TIM17: TIM17 clock + * @arg RCC_APB2Periph_DBGMCU: DBGMCU clock + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB2RSTR |= RCC_APB2Periph; + } + else + { + RCC->APB2RSTR &= ~RCC_APB2Periph; + } +} + +/** + * @brief Forces or releases Low Speed APB (APB1) peripheral reset. + * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2: TIM2 clock + * @arg RCC_APB1Periph_TIM3: TIM3 clock + * @arg RCC_APB1Periph_TIM6: TIM6 clock + * @arg RCC_APB1Periph_TIM14: TIM14 clock + * @arg RCC_APB1Periph_WWDG: WWDG clock + * @arg RCC_APB1Periph_SPI2: SPI2 clock + * @arg RCC_APB1Periph_USART2: USART2 clock + * @arg RCC_APB1Periph_I2C1: I2C1 clock + * @arg RCC_APB1Periph_I2C2: I2C2 clock + * @arg RCC_APB1Periph_PWR: PWR clock + * @arg RCC_APB1Periph_DAC: DAC clock + * @arg RCC_APB1Periph_CEC: CEC clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB1RSTR |= RCC_APB1Periph; + } + else + { + RCC->APB1RSTR &= ~RCC_APB1Periph; + } +} + +/** + * @} + */ + +/** @defgroup RCC_Group4 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified RCC interrupts. + * @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled + * and if the HSE clock fails, the CSS interrupt occurs and an NMI is + * automatically generated. The NMI will be executed indefinitely, and + * since NMI has higher priority than any other IRQ (and main program) + * the application will be stacked in the NMI ISR unless the CSS interrupt + * pending bit is cleared. + * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt + * @param NewState: new state of the specified RCC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_IT(RCC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Perform Byte access to RCC_CIR[13:8] bits to enable the selected interrupts */ + *(__IO uint8_t *) CIR_BYTE1_ADDRESS |= RCC_IT; + } + else + { + /* Perform Byte access to RCC_CIR[13:8] bits to disable the selected interrupts */ + *(__IO uint8_t *) CIR_BYTE1_ADDRESS &= (uint8_t)~RCC_IT; + } +} + +/** + * @brief Checks whether the specified RCC flag is set or not. + * @param RCC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready + * @arg RCC_FLAG_PLLRDY: PLL clock ready + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready + * @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset + * @arg RCC_FLAG_PINRST: Pin reset + * @arg RCC_FLAG_V18PWRRSTF: V1.8 power domain reset + * @arg RCC_FLAG_PORRST: POR/PDR reset + * @arg RCC_FLAG_SFTRST: Software reset + * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset + * @arg RCC_FLAG_WWDGRST: Window Watchdog reset + * @arg RCC_FLAG_LPWRRST: Low Power reset + * @arg RCC_FLAG_HSI14RDY: HSI14 oscillator clock ready + * @retval The new state of RCC_FLAG (SET or RESET). + */ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_FLAG(RCC_FLAG)); + + /* Get the RCC register index */ + tmp = RCC_FLAG >> 5; + + if (tmp == 0) /* The flag to check is in CR register */ + { + statusreg = RCC->CR; + } + else if (tmp == 1) /* The flag to check is in BDCR register */ + { + statusreg = RCC->BDCR; + } + else if (tmp == 2) /* The flag to check is in CSR register */ + { + statusreg = RCC->CSR; + } + else /* The flag to check is in CR2 register */ + { + statusreg = RCC->CR2; + } + + /* Get the flag position */ + tmp = RCC_FLAG & FLAG_MASK; + + if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the RCC reset flags. + * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_V18PWRRSTF, + * RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, + * RCC_FLAG_LPWRRST. + * @param None + * @retval None + */ +void RCC_ClearFlag(void) +{ + /* Set RMVF bit to clear the reset flags */ + RCC->CSR |= RCC_CSR_RMVF; +} + +/** + * @brief Checks whether the specified RCC interrupt has occurred or not. + * @param RCC_IT: specifies the RCC interrupt source to check. + * This parameter can be one of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt + * @arg RCC_IT_CSS: Clock Security System interrupt + * @retval The new state of RCC_IT (SET or RESET). + */ +ITStatus RCC_GetITStatus(uint8_t RCC_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_GET_IT(RCC_IT)); + + /* Check the status of the specified RCC interrupt */ + if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the RCC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the RCC's interrupt pending bits. + * @param RCC_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt + * @arg RCC_IT_CSS: Clock Security System interrupt + * @retval None + */ +void RCC_ClearITPendingBit(uint8_t RCC_IT) +{ + /* Check the parameters */ + assert_param(IS_RCC_CLEAR_IT(RCC_IT)); + + /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt + pending bits */ + *(__IO uint8_t *) CIR_BYTE2_ADDRESS = RCC_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_rtc.c b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_rtc.c new file mode 100644 index 0000000..12664f2 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_rtc.c @@ -0,0 +1,2367 @@ +/** + ****************************************************************************** + * @file stm32f0xx_rtc.c + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Real-Time Clock (RTC) peripheral: + * + Initialization + * + Calendar (Time and Date) configuration + * + Alarms (Alarm A) configuration + * + Daylight Saving configuration + * + Output pin Configuration + * + Digital Calibration configuration + * + TimeStamp configuration + * + Tampers configuration + * + Backup Data Registers configuration + * + Output Type Config configuration + * + Shift control synchronisation + * + Interrupts and flags management + * + @verbatim + =============================================================================== + ##### Backup Domain Operating Condition ##### + =============================================================================== + [..] The real-time clock (RTC) and the RTC backup registers can be powered + from the VBAT voltage when the main VDD supply is powered off. + To retain the content of the RTC backup registers and supply the RTC + when VDD is turned off, VBAT pin can be connected to an optional + standby voltage supplied by a battery or by another source. + + [..] To allow the RTC to operate even when the main digital supply (VDD) + is turned off, the VBAT pin powers the following blocks: + (#) The RTC + (#) The LSE oscillator + (#) PC13 to PC15 I/Os I/Os (when available) + + [..] When the backup domain is supplied by VDD (analog switch connected + to VDD), the following functions are available: + (#) PC14 and PC15 can be used as either GPIO or LSE pins + (#) PC13 can be used as a GPIO or as the RTC_AF1 pin + + [..] When the backup domain is supplied by VBAT (analog switch connected + to VBAT because VDD is not present), the following functions are available: + (#) PC14 and PC15 can be used as LSE pins only + (#) PC13 can be used as the RTC_AF1 pin + + ##### Backup Domain Reset ##### + =============================================================================== + [..] The backup domain reset sets all RTC registers and the RCC_BDCR + register to their reset values. + A backup domain reset is generated when one of the following events + occurs: + (#) Software reset, triggered by setting the BDRST bit in the + RCC Backup domain control register (RCC_BDCR). You can use the + RCC_BackupResetCmd(). + (#) VDD or VBAT power on, if both supplies have previously been + powered off. + + ##### Backup Domain Access ##### + =============================================================================== + [..] After reset, the backup domain (RTC registers and RTC backup data + registers) is protected against possible unwanted write accesses. + [..] To enable access to the Backup Domain and RTC registers, proceed as follows: + (#) Enable the Power Controller (PWR) APB1 interface clock using the + RCC_APB1PeriphClockCmd() function. + (#) Enable access to Backup domain using the PWR_BackupAccessCmd() function. + (#) Select the RTC clock source using the RCC_RTCCLKConfig() function. + (#) Enable RTC Clock using the RCC_RTCCLKCmd() function. + + + ##### How to use this driver ##### + =============================================================================== + [..] + (+) Enable the backup domain access (see description in the section above) + (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and + RTC hour format using the RTC_Init() function. + + ***Time and Date configuration *** + ================================== + [..] + (+) To configure the RTC Calendar (Time and Date) use the RTC_SetTime() + and RTC_SetDate() functions. + (+) To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate() + functions. + (+) To read the RTC subsecond, use the RTC_GetSubSecond() function. + (+) Use the RTC_DayLightSavingConfig() function to add or sub one + hour to the RTC Calendar. + + ***Alarm configuration *** + ========================== + [..] + (+) To configure the RTC Alarm use the RTC_SetAlarm() function. + (+) Enable the selected RTC Alarm using the RTC_AlarmCmd() function + (+) To read the RTC Alarm, use the RTC_GetAlarm() function. + (+) To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function. + + ***Outputs configuration *** + ============================ + [..] The RTC has 2 different outputs: + (+) AFO_ALARM: this output is used to manage the RTC Alarm A. + To output the selected RTC signal on RTC_AF1 pin, use the + RTC_OutputConfig() function. + (+) AFO_CALIB: this output is 512Hz signal or 1Hz . + To output the RTC Clock on RTC_AF1 pin, use the RTC_CalibOutputCmd() + function. + + ***Original Digital Calibration configuration *** + ================================= + [..] Configure the RTC Original Digital Calibration Value and the corresponding + calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig() + function. + + ***TimeStamp configuration *** + ============================== + [..] + (+) Configure the RTC_AF1 trigger and enables the RTC TimeStamp + using the RTC_TimeStampCmd() function. + (+) To read the RTC TimeStamp Time and Date register, use the + RTC_GetTimeStamp() function. + (+) To read the RTC TimeStamp SubSecond register, use the + RTC_GetTimeStampSubSecond() function. + + ***Tamper configuration *** + =========================== + [..] + (+) Configure the Tamper filter count using RTC_TamperFilterConfig() + function. + (+) Configure the RTC Tamper trigger Edge or Level according to the Tamper + filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig() function + (+) Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig() + function. + (+) Configure the Tamper precharge or discharge duration using + RTC_TamperPinsPrechargeDuration() function. + (+) Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function. + (+) Enable the RTC Tamper using the RTC_TamperCmd() function. + (+) Enable the Time stamp on Tamper detection event using + RTC_TSOnTamperDetecCmd() function. + + ***Backup Data Registers configuration *** + ========================================== + [..] + (+) To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister() + function. + (+) To read the RTC Backup Data registers, use the RTC_ReadBackupRegister() + function. + + ##### RTC and low power modes ##### + =============================================================================== + [..] The MCU can be woken up from a low power mode by an RTC alternate + function. + [..] The RTC alternate functions are the RTC alarm (Alarm A), RTC tamper + event detection and RTC time stamp event detection. + These RTC alternate functions can wake up the system from the Stop + and Standby lowpower modes. + The system can also wake up from low power modes without depending + on an external interrupt (Auto-wakeup mode), by using the RTC alarm events. + [..] The RTC provides a programmable time base for waking up from the + Stop or Standby mode at regular intervals. + Wakeup from STOP and Standby modes is possible only when the RTC + clock source is LSE or LSI. + + ##### Selection of RTC_AF1 alternate functions ##### + =============================================================================== + [..] The RTC_AF1 pin (PC13) can be used for the following purposes: + (+) AFO_ALARM output + (+) AFO_CALIB output + (+) AFI_TAMPER + (+) AFI_TIMESTAMP + + +------------------------------------------------------------------------------------------+ + | Pin |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | WKUP2 |ALARMOUTTYPE | + | configuration | ENABLED | ENABLED | ENABLED | ENABLED |ENABLED | AFO_ALARM | + | and function | | | | | |Configuration | + |-----------------|----------|----------|-----------|--------------|--------|--------------| + | Alarm out | | | | | Don't | | + | output OD | 1 | 0 |Don't care | Don't care | care | 0 | + |-----------------|----------|----------|-----------|--------------|--------|--------------| + | Alarm out | | | | | Don't | | + | output PP | 1 | 0 |Don't care | Don't care | care | 1 | + |-----------------|----------|----------|-----------|--------------|--------|--------------| + | Calibration out | | | | | Don't | | + | output PP | 0 | 1 |Don't care | Don't care | care | Don't care | + |-----------------|----------|----------|-----------|--------------|--------|--------------| + | TAMPER input | | | | | Don't | | + | floating | 0 | 0 | 1 | 0 | care | Don't care | + |-----------------|----------|----------|-----------|--------------|--------|--------------| + | TIMESTAMP and | | | | | Don't | | + | TAMPER input | 0 | 0 | 1 | 1 | care | Don't care | + | floating | | | | | | | + |-----------------|----------|----------|-----------|--------------|--------|--------------| + | TIMESTAMP input | | | | | Don't | | + | floating | 0 | 0 | 0 | 1 | care | Don't care | + |-----------------|----------|----------|-----------|--------------|--------|--------------| + | Wakeup Pin 2 | 0 | 0 | 0 | 0 | 1 | Don't care | + |-----------------|----------|----------|-----------|--------------|--------|--------------| + | Standard GPIO | 0 | 0 | 0 | 0 | 0 | Don't care | + +------------------------------------------------------------------------------------------+ + + @endverbatim + + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_rtc.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup RTC + * @brief RTC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* Masks Definition */ +#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) +#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) +#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) +#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F) +#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_ALRAF | \ + RTC_FLAG_RSF | RTC_FLAG_INITS |RTC_FLAG_INITF | \ + RTC_FLAG_TAMP1F | RTC_FLAG_TAMP2F | RTC_FLAG_TAMP3F | \ + RTC_FLAG_RECALPF | RTC_FLAG_SHPF)) + +#define INITMODE_TIMEOUT ((uint32_t) 0x00004000) +#define SYNCHRO_TIMEOUT ((uint32_t) 0x00008000) +#define RECALPF_TIMEOUT ((uint32_t) 0x00001000) +#define SHPF_TIMEOUT ((uint32_t) 0x00001000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static uint8_t RTC_ByteToBcd2(uint8_t Value); +static uint8_t RTC_Bcd2ToByte(uint8_t Value); + +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup RTC_Private_Functions + * @{ + */ + +/** @defgroup RTC_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + + [..] This section provide functions allowing to initialize and configure the RTC + Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers + Write protection, enter and exit the RTC initialization mode, RTC registers + synchronization check and reference clock detection enable. + + (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. + It is split into 2 programmable prescalers to minimize power consumption. + (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler. + (++) When both prescalers are used, it is recommended to configure the + asynchronous prescaler to a high value to minimize consumption. + (#) All RTC registers are Write protected. Writing to the RTC registers + is enabled by writing a key into the Write Protection register, RTC_WPR. + (#) To Configure the RTC Calendar, user application should enter + initialization mode. In this mode, the calendar counter is stopped + and its value can be updated. When the initialization sequence is + complete, the calendar restarts counting after 4 RTCCLK cycles. + (#) To read the calendar through the shadow registers after Calendar + initialization, calendar update or after wakeup from low power modes + the software must first clear the RSF flag. The software must then + wait until it is set again before reading the calendar, which means + that the calendar registers have been correctly copied into the + RTC_TR and RTC_DR shadow registers.The RTC_WaitForSynchro() function + implements the above software sequence (RSF clear and RSF check). + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the RTC registers to their default reset values. + * @note This function doesn't reset the RTC Clock source and RTC Backup Data + * registers. + * @param None + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are deinitialized + * - ERROR: RTC registers are not deinitialized + */ +ErrorStatus RTC_DeInit(void) +{ + __IO uint32_t wutcounter = 0x00; + ErrorStatus status = ERROR; + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Reset TR, DR and CR registers */ + RTC->TR = (uint32_t)0x00000000; + RTC->DR = (uint32_t)0x00002101; + RTC->CR &= (uint32_t)0x00000000; + RTC->PRER = (uint32_t)0x007F00FF; + RTC->ALRMAR = (uint32_t)0x00000000; + RTC->SHIFTR = (uint32_t)0x00000000; + RTC->CAL = (uint32_t)0x00000000; + RTC->ALRMASSR = (uint32_t)0x00000000; + + /* Reset ISR register and exit initialization mode */ + RTC->ISR = (uint32_t)0x00000000; + + /* Reset Tamper and alternate functions configuration register */ + RTC->TAFCR = 0x00000000; + + /* Wait till the RTC RSF flag is set */ + if (RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @brief Initializes the RTC registers according to the specified parameters + * in RTC_InitStruct. + * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains + * the configuration information for the RTC peripheral. + * @note The RTC Prescaler register is write protected and can be written in + * initialization mode only. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are initialized + * - ERROR: RTC registers are not initialized + */ +ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat)); + assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv)); + assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Clear RTC CR FMT Bit */ + RTC->CR &= ((uint32_t)~(RTC_CR_FMT)); + /* Set RTC_CR register */ + RTC->CR |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat)); + + /* Configure the RTC PRER */ + RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv); + RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16); + + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + status = SUCCESS; + } + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @brief Fills each RTC_InitStruct member with its default value. + * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be + * initialized. + * @retval None + */ +void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct) +{ + /* Initialize the RTC_HourFormat member */ + RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24; + + /* Initialize the RTC_AsynchPrediv member */ + RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F; + + /* Initialize the RTC_SynchPrediv member */ + RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; +} + +/** + * @brief Enables or disables the RTC registers write protection. + * @note All the RTC registers are write protected except for RTC_ISR[13:8], + * RTC_TAFCR and RTC_BKPxR. + * @note Writing a wrong key reactivates the write protection. + * @note The protection mechanism is not affected by system reset. + * @param NewState: new state of the write protection. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_WriteProtectionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + } + else + { + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + } +} + +/** + * @brief Enters the RTC Initialization mode. + * @note The RTC Initialization mode is write protected, use the + * RTC_WriteProtectionCmd(DISABLE) before calling this function. + * @param None + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC is in Init mode + * - ERROR: RTC is not in Init mode + */ +ErrorStatus RTC_EnterInitMode(void) +{ + __IO uint32_t initcounter = 0x00; + ErrorStatus status = ERROR; + uint32_t initstatus = 0x00; + + /* Check if the Initialization mode is set */ + if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET) + { + /* Set the Initialization mode */ + RTC->ISR = (uint32_t)RTC_INIT_MASK; + + /* Wait till RTC is in INIT state and if Time out is reached exit */ + do + { + initstatus = RTC->ISR & RTC_ISR_INITF; + initcounter++; + } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00)); + + if ((RTC->ISR & RTC_ISR_INITF) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + } + else + { + status = SUCCESS; + } + + return (status); +} + +/** + * @brief Exits the RTC Initialization mode. + * @note When the initialization sequence is complete, the calendar restarts + * counting after 4 RTCCLK cycles. + * @note The RTC Initialization mode is write protected, use the + * RTC_WriteProtectionCmd(DISABLE) before calling this function. + * @param None + * @retval None + */ +void RTC_ExitInitMode(void) +{ + /* Exit Initialization mode */ + RTC->ISR &= (uint32_t)~RTC_ISR_INIT; +} + +/** + * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are + * synchronized with RTC APB clock. + * @note The RTC Resynchronization mode is write protected, use the + * RTC_WriteProtectionCmd(DISABLE) before calling this function. + * @note To read the calendar through the shadow registers after Calendar + * initialization, calendar update or after wakeup from low power modes + * the software must first clear the RSF flag. + * The software must then wait until it is set again before reading + * the calendar, which means that the calendar registers have been + * correctly copied into the RTC_TR and RTC_DR shadow registers. + * @param None + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are synchronised + * - ERROR: RTC registers are not synchronised + */ +ErrorStatus RTC_WaitForSynchro(void) +{ + __IO uint32_t synchrocounter = 0; + ErrorStatus status = ERROR; + uint32_t synchrostatus = 0x00; + + if ((RTC->CR & RTC_CR_BYPSHAD) != RESET) + { + /* Bypass shadow mode */ + status = SUCCESS; + } + else + { + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Clear RSF flag */ + RTC->ISR &= (uint32_t)RTC_RSF_MASK; + + /* Wait the registers to be synchronised */ + do + { + synchrostatus = RTC->ISR & RTC_ISR_RSF; + synchrocounter++; + } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00)); + + if ((RTC->ISR & RTC_ISR_RSF) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + } + + return (status); +} + +/** + * @brief Enables or disables the RTC reference clock detection. + * @param NewState: new state of the RTC reference clock. + * This parameter can be: ENABLE or DISABLE. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC reference clock detection is enabled + * - ERROR: RTC reference clock detection is disabled + */ +ErrorStatus RTC_RefClockCmd(FunctionalState NewState) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + if (NewState != DISABLE) + { + /* Enable the RTC reference clock detection */ + RTC->CR |= RTC_CR_REFCKON; + } + else + { + /* Disable the RTC reference clock detection */ + RTC->CR &= ~RTC_CR_REFCKON; + } + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + status = SUCCESS; + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @brief Enables or Disables the Bypass Shadow feature. + * @note When the Bypass Shadow is enabled the calendar value are taken + * directly from the Calendar counter. + * @param NewState: new state of the Bypass Shadow feature. + * This parameter can be: ENABLE or DISABLE. + * @retval None +*/ +void RTC_BypassShadowCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + if (NewState != DISABLE) + { + /* Set the BYPSHAD bit */ + RTC->CR |= (uint8_t)RTC_CR_BYPSHAD; + } + else + { + /* Reset the BYPSHAD bit */ + RTC->CR &= (uint8_t)~RTC_CR_BYPSHAD; + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @} + */ + +/** @defgroup RTC_Group2 Time and Date configuration functions + * @brief Time and Date configuration functions + * +@verbatim + =============================================================================== + ##### Time and Date configuration functions ##### + =============================================================================== + [..] This section provide functions allowing to program and read the RTC + Calendar (Time and Date). + +@endverbatim + * @{ + */ + +/** + * @brief Set the RTC current time. + * @param RTC_Format: specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains + * the time configuration information for the RTC. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Time register is configured + * - ERROR: RTC Time register is not configured + */ +ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) +{ + uint32_t tmpreg = 0; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + if (RTC_Format == RTC_Format_BIN) + { + if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours)); + assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); + } + else + { + RTC_TimeStruct->RTC_H12 = 0x00; + assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours)); + } + assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes)); + assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds)); + } + else + { + if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); + assert_param(IS_RTC_HOUR12(tmpreg)); + assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); + } + else + { + RTC_TimeStruct->RTC_H12 = 0x00; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours))); + } + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds))); + } + + /* Check the input parameters format */ + if (RTC_Format != RTC_Format_BIN) + { + tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \ + ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \ + ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \ + ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16)); + } + else + { + tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \ + (((uint32_t)RTC_TimeStruct->RTC_H12) << 16)); + } + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Set the RTC_TR register */ + RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); + + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if ((RTC->CR & RTC_CR_BYPSHAD) == RESET) + { + if (RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + else + { + status = SUCCESS; + } + + } + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @brief Fills each RTC_TimeStruct member with its default value + * (Time = 00h:00min:00sec). + * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be + * initialized. + * @retval None + */ +void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct) +{ + /* Time = 00h:00min:00sec */ + RTC_TimeStruct->RTC_H12 = RTC_H12_AM; + RTC_TimeStruct->RTC_Hours = 0; + RTC_TimeStruct->RTC_Minutes = 0; + RTC_TimeStruct->RTC_Seconds = 0; +} + +/** + * @brief Get the RTC current Time. + * @param RTC_Format: specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will + * contain the returned current time configuration. + * @retval None + */ +void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + /* Get the RTC_TR register */ + tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); + + /* Fill the structure fields with the read parameters */ + RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16); + RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8); + RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); + RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); + + /* Check the input parameters format */ + if (RTC_Format == RTC_Format_BIN) + { + /* Convert the structure parameters to Binary format */ + RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); + RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes); + RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds); + } +} + +/** + * @brief Gets the RTC current Calendar Subseconds value. + * @note This function freeze the Time and Date registers after reading the + * SSR register. + * @param None + * @retval RTC current Calendar Subseconds value. + */ +uint32_t RTC_GetSubSecond(void) +{ + uint32_t tmpreg = 0; + + /* Get subseconds values from the correspondent registers*/ + tmpreg = (uint32_t)(RTC->SSR); + + /* Read DR register to unfroze calendar registers */ + (void) (RTC->DR); + + return (tmpreg); +} + +/** + * @brief Set the RTC current date. + * @param RTC_Format: specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains + * the date configuration information for the RTC. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Date register is configured + * - ERROR: RTC Date register is not configured + */ +ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) +{ + uint32_t tmpreg = 0; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10)) + { + RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A; + } + if (RTC_Format == RTC_Format_BIN) + { + assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year)); + assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month)); + assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date)); + } + else + { + assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year))); + tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month); + assert_param(IS_RTC_MONTH(tmpreg)); + tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); + assert_param(IS_RTC_DATE(tmpreg)); + } + assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay)); + + /* Check the input parameters format */ + if (RTC_Format != RTC_Format_BIN) + { + tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \ + (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \ + ((uint32_t)RTC_DateStruct->RTC_Date) | \ + (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13)); + } + else + { + tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \ + ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13)); + } + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Set the RTC_DR register */ + RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK); + + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if ((RTC->CR & RTC_CR_BYPSHAD) == RESET) + { + if (RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + else + { + status = SUCCESS; + } + } + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @brief Fills each RTC_DateStruct member with its default value + * (Monday, January 01 xx00). + * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be + * initialized. + * @retval None + */ +void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct) +{ + /* Monday, January 01 xx00 */ + RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday; + RTC_DateStruct->RTC_Date = 1; + RTC_DateStruct->RTC_Month = RTC_Month_January; + RTC_DateStruct->RTC_Year = 0; +} + +/** + * @brief Get the RTC current date. + * @param RTC_Format: specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will + * contain the returned current date configuration. + * @retval None + */ +void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + /* Get the RTC_TR register */ + tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK); + + /* Fill the structure fields with the read parameters */ + RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16); + RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8); + RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU)); + RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13); + + /* Check the input parameters format */ + if (RTC_Format == RTC_Format_BIN) + { + /* Convert the structure parameters to Binary format */ + RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year); + RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month); + RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); + RTC_DateStruct->RTC_WeekDay = (uint8_t)(RTC_DateStruct->RTC_WeekDay); + } +} + +/** + * @} + */ + +/** @defgroup RTC_Group3 Alarms configuration functions + * @brief Alarms (Alarm A) configuration functions + * +@verbatim + =============================================================================== + ##### Alarms (Alarm A and Alarm B) configuration functions ##### + =============================================================================== + [..] This section provide functions allowing to program and read the RTC + Alarms. + +@endverbatim + * @{ + */ + +/** + * @brief Set the specified RTC Alarm. + * @note The Alarm register can only be written when the corresponding Alarm + * is disabled (Use the RTC_AlarmCmd(DISABLE)). + * @param RTC_Format: specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_Alarm: specifies the alarm to be configured. + * This parameter can be one of the following values: + * @arg RTC_Alarm_A: to select Alarm A + * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that + * contains the alarm configuration parameters. + * @retval None + */ +void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + assert_param(IS_RTC_ALARM(RTC_Alarm)); + assert_param(IS_RTC_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask)); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel)); + + if (RTC_Format == RTC_Format_BIN) + { + if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); + assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); + } + else + { + RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; + assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); + } + assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)); + assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)); + + if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); + } + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); + } + } + else + { + if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours); + assert_param(IS_RTC_HOUR12(tmpreg)); + assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); + } + else + { + RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours))); + } + + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds))); + + if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) + { + tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); + } + else + { + tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); + } + } + + /* Check the input parameters format */ + if (RTC_Format != RTC_Format_BIN) + { + tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ + ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ + ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \ + ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \ + ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ + ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ + ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); + } + else + { + tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \ + ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ + ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ + ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); + } + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Configure the Alarm register */ + RTC->ALRMAR = (uint32_t)tmpreg; + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @brief Fills each RTC_AlarmStruct member with its default value + * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask = + * all fields are masked). + * @param RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which + * will be initialized. + * @retval None + */ +void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct) +{ + /* Alarm Time Settings : Time = 00h:00mn:00sec */ + RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM; + RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0; + RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0; + RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0; + + /* Alarm Date Settings : Date = 1st day of the month */ + RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date; + RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1; + + /* Alarm Masks Settings : Mask = all fields are not masked */ + RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None; +} + +/** + * @brief Get the RTC Alarm value and masks. + * @param RTC_Format: specifies the format of the output parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_Alarm: specifies the alarm to be read. + * This parameter can be one of the following values: + * @arg RTC_Alarm_A: to select Alarm A + * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will + * contains the output alarm configuration values. + * @retval None + */ +void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + assert_param(IS_RTC_ALARM(RTC_Alarm)); + + /* Get the RTC_ALRMAR register */ + tmpreg = (uint32_t)(RTC->ALRMAR); + + /* Fill the structure with the read parameters */ + RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \ + RTC_ALRMAR_HU)) >> 16); + RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \ + RTC_ALRMAR_MNU)) >> 8); + RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \ + RTC_ALRMAR_SU)); + RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16); + RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24); + RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); + RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All); + + if (RTC_Format == RTC_Format_BIN) + { + RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ + RTC_AlarmTime.RTC_Hours); + RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ + RTC_AlarmTime.RTC_Minutes); + RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ + RTC_AlarmTime.RTC_Seconds); + RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); + } +} + +/** + * @brief Enables or disables the specified RTC Alarm. + * @param RTC_Alarm: specifies the alarm to be configured. + * This parameter can be any combination of the following values: + * @arg RTC_Alarm_A: to select Alarm A + * @param NewState: new state of the specified alarm. + * This parameter can be: ENABLE or DISABLE. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Alarm is enabled/disabled + * - ERROR: RTC Alarm is not enabled/disabled + */ +ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState) +{ + __IO uint32_t alarmcounter = 0x00; + uint32_t alarmstatus = 0x00; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_CMD_ALARM(RTC_Alarm)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Configure the Alarm state */ + if (NewState != DISABLE) + { + RTC->CR |= (uint32_t)RTC_Alarm; + + status = SUCCESS; + } + else + { + /* Disable the Alarm in RTC_CR register */ + RTC->CR &= (uint32_t)~RTC_Alarm; + + /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ + do + { + alarmstatus = RTC->ISR & (RTC_Alarm >> 8); + alarmcounter++; + } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00)); + + if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @brief Configure the RTC AlarmA/B Subseconds value and mask. + * @note This function is performed only when the Alarm is disabled. + * @param RTC_Alarm: specifies the alarm to be configured. + * This parameter can be one of the following values: + * @arg RTC_Alarm_A: to select Alarm A + * @param RTC_AlarmSubSecondValue: specifies the Subseconds value. + * This parameter can be a value from 0 to 0x00007FFF. + * @param RTC_AlarmSubSecondMask: specifies the Subseconds Mask. + * This parameter can be any combination of the following values: + * @arg RTC_AlarmSubSecondMask_All: All Alarm SS fields are masked. + * There is no comparison on sub seconds for Alarm. + * @arg RTC_AlarmSubSecondMask_SS14_1: SS[14:1] are don't care in Alarm comparison. + * Only SS[0] is compared + * @arg RTC_AlarmSubSecondMask_SS14_2: SS[14:2] are don't care in Alarm comparison. + * Only SS[1:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_3: SS[14:3] are don't care in Alarm comparison. + * Only SS[2:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_4: SS[14:4] are don't care in Alarm comparison. + * Only SS[3:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_5: SS[14:5] are don't care in Alarm comparison. + * Only SS[4:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_6: SS[14:6] are don't care in Alarm comparison. + * Only SS[5:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_7: SS[14:7] are don't care in Alarm comparison. + * Only SS[6:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_8: SS[14:8] are don't care in Alarm comparison. + * Only SS[7:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_9: SS[14:9] are don't care in Alarm comparison. + * Only SS[8:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_10: SS[14:10] are don't care in Alarm comparison. + * Only SS[9:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_11: SS[14:11] are don't care in Alarm comparison. + * Only SS[10:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_12: SS[14:12] are don't care in Alarm comparison. + * Only SS[11:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_13: SS[14:13] are don't care in Alarm comparison. + * Only SS[12:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14: SS[14] is don't care in Alarm comparison. + * Only SS[13:0] are compared + * @arg RTC_AlarmSubSecondMask_None: SS[14:0] are compared and must match + * to activate alarm + * @retval None + */ +void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint8_t RTC_AlarmSubSecondMask) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_ALARM(RTC_Alarm)); + assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue)); + assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(RTC_AlarmSubSecondMask)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Configure the Alarm A or Alarm B SubSecond registers */ + tmpreg = (uint32_t) (((uint32_t)(RTC_AlarmSubSecondValue)) | ((uint32_t)(RTC_AlarmSubSecondMask) << 24)); + + /* Configure the AlarmA SubSecond register */ + RTC->ALRMASSR = tmpreg; + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + +} + +/** + * @brief Gets the RTC Alarm Subseconds value. + * @param RTC_Alarm: specifies the alarm to be read. + * This parameter can be one of the following values: + * @arg RTC_Alarm_A: to select Alarm A + * @param None + * @retval RTC Alarm Subseconds value. + */ +uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm) +{ + uint32_t tmpreg = 0; + + /* Get the RTC_ALRMAR register */ + tmpreg = (uint32_t)((RTC->ALRMASSR) & RTC_ALRMASSR_SS); + + return (tmpreg); +} + +/** + * @} + */ + +/** @defgroup RTC_Group4 Daylight Saving configuration functions + * @brief Daylight Saving configuration functions + * +@verbatim + =============================================================================== + ##### WakeUp Timer configuration functions ##### + =============================================================================== + [..] This section provide functions allowing to program and read the RTC WakeUp. + + This section provide functions allowing to configure the RTC DayLight Saving. + +@endverbatim + * @{ + */ + +/** + * @brief Adds or substract one hour from the current time. + * @param RTC_DayLightSaveOperation: the value of hour adjustment. + * This parameter can be one of the following values: + * @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time) + * @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time) + * @param RTC_StoreOperation: Specifies the value to be written in the BCK bit + * in CR register to store the operation. + * This parameter can be one of the following values: + * @arg RTC_StoreOperation_Reset + * @arg RTC_StoreOperation_Set + * @retval None + */ +void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation) +{ + /* Check the parameters */ + assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving)); + assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Clear the bits to be configured */ + RTC->CR &= (uint32_t)~(RTC_CR_BCK); + + /* Configure the RTC_CR register */ + RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation); + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @brief Returns the RTC Day Light Saving stored operation. + * @param None + * @retval RTC Day Light Saving stored operation. + * - RTC_StoreOperation_Reset + * - RTC_StoreOperation_Set + */ +uint32_t RTC_GetStoreOperation(void) +{ + return (RTC->CR & RTC_CR_BCK); +} + +/** + * @} + */ + +/** @defgroup RTC_Group5 Output pin Configuration function + * @brief Output pin Configuration function + * +@verbatim + =============================================================================== + ##### Output pin Configuration function ##### + =============================================================================== + [..] This section provide functions allowing to configure the RTC Output source. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the RTC output source (AFO_ALARM). + * @param RTC_Output: Specifies which signal will be routed to the RTC output. + * This parameter can be one of the following values: + * @arg RTC_Output_Disable: No output selected + * @arg RTC_Output_AlarmA: signal of AlarmA mapped to output + * @param RTC_OutputPolarity: Specifies the polarity of the output signal. + * This parameter can be one of the following: + * @arg RTC_OutputPolarity_High: The output pin is high when the + * ALRAF is high (depending on OSEL) + * @arg RTC_OutputPolarity_Low: The output pin is low when the + * ALRAF is high (depending on OSEL) + * @retval None + */ +void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity) +{ + /* Check the parameters */ + assert_param(IS_RTC_OUTPUT(RTC_Output)); + assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Clear the bits to be configured */ + RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL); + + /* Configure the output selection and polarity */ + RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity); + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @} + */ + +/** @defgroup RTC_Group7 Digital Calibration configuration functions + * @brief Digital Calibration configuration functions + * +@verbatim + =============================================================================== + ##### Digital Calibration configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the RTC clock to be output through the relative + * pin. + * @param NewState: new state of the digital calibration Output. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_CalibOutputCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + if (NewState != DISABLE) + { + /* Enable the RTC clock output */ + RTC->CR |= (uint32_t)RTC_CR_COE; + } + else + { + /* Disable the RTC clock output */ + RTC->CR &= (uint32_t)~RTC_CR_COE; + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + * @param RTC_CalibOutput : Select the Calibration output Selection . + * This parameter can be one of the following values: + * @arg RTC_CalibOutput_512Hz: A signal has a regular waveform at 512Hz. + * @arg RTC_CalibOutput_1Hz: A signal has a regular waveform at 1Hz. + * @retval None +*/ +void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput) +{ + /* Check the parameters */ + assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /*clear flags before config*/ + RTC->CR &= (uint32_t)~(RTC_CR_CALSEL); + + /* Configure the RTC_CR register */ + RTC->CR |= (uint32_t)RTC_CalibOutput; + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @brief Configures the Smooth Calibration Settings. + * @param RTC_SmoothCalibPeriod: Select the Smooth Calibration Period. + * This parameter can be can be one of the following values: + * @arg RTC_SmoothCalibPeriod_32sec: The smooth calibration periode is 32s. + * @arg RTC_SmoothCalibPeriod_16sec: The smooth calibration periode is 16s. + * @arg RTC_SmoothCalibPeriod_8sec: The smooth calibartion periode is 8s. + * @param RTC_SmoothCalibPlusPulses: Select to Set or reset the CALP bit. + * This parameter can be one of the following values: + * @arg RTC_SmoothCalibPlusPulses_Set: Add one RTCCLK puls every 2**11 pulses. + * @arg RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added. + * @param RTC_SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits. + * This parameter can be one any value from 0 to 0x000001FF. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Calib registers are configured + * - ERROR: RTC Calib registers are not configured +*/ +ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, + uint32_t RTC_SmoothCalibPlusPulses, + uint32_t RTC_SmouthCalibMinusPulsesValue) +{ + ErrorStatus status = ERROR; + uint32_t recalpfcount = 0; + + /* Check the parameters */ + assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(RTC_SmoothCalibPeriod)); + assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses)); + assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* check if a calibration is pending*/ + if ((RTC->ISR & RTC_ISR_RECALPF) != RESET) + { + /* wait until the Calibration is completed*/ + while (((RTC->ISR & RTC_ISR_RECALPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT)) + { + recalpfcount++; + } + } + + /* check if the calibration pending is completed or if there is no calibration operation at all*/ + if ((RTC->ISR & RTC_ISR_RECALPF) == RESET) + { + /* Configure the Smooth calibration settings */ + RTC->CAL = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses | (uint32_t)RTC_SmouthCalibMinusPulsesValue); + + status = SUCCESS; + } + else + { + status = ERROR; + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return (ErrorStatus)(status); +} + +/** + * @} + */ + + +/** @defgroup RTC_Group7 TimeStamp configuration functions + * @brief TimeStamp configuration functions + * +@verbatim + =============================================================================== + ##### TimeStamp configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or Disables the RTC TimeStamp functionality with the + * specified time stamp pin stimulating edge. + * @param RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is + * activated. + * This parameter can be one of the following: + * @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising + * edge of the related pin. + * @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the + * falling edge of the related pin. + * @param NewState: new state of the TimeStamp. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Get the RTC_CR register and clear the bits to be configured */ + tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); + + /* Get the new configuration */ + if (NewState != DISABLE) + { + tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE); + } + else + { + tmpreg |= (uint32_t)(RTC_TimeStampEdge); + } + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Configure the Time Stamp TSEDGE and Enable bits */ + RTC->CR = (uint32_t)tmpreg; + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @brief Get the RTC TimeStamp value and masks. + * @param RTC_Format: specifies the format of the output parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will + * contains the TimeStamp time values. + * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will + * contains the TimeStamp date values. + * @retval None + */ +void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, + RTC_DateTypeDef* RTC_StampDateStruct) +{ + uint32_t tmptime = 0, tmpdate = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + /* Get the TimeStamp time and date registers values */ + tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK); + tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK); + + /* Fill the Time structure fields with the read parameters */ + RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16); + RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8); + RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU)); + RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); + + /* Fill the Date structure fields with the read parameters */ + RTC_StampDateStruct->RTC_Year = 0; + RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8); + RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU)); + RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13); + + /* Check the input parameters format */ + if (RTC_Format == RTC_Format_BIN) + { + /* Convert the Time structure parameters to Binary format */ + RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours); + RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes); + RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds); + + /* Convert the Date structure parameters to Binary format */ + RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month); + RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date); + RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay); + } +} + +/** + * @brief Get the RTC timestamp Subseconds value. + * @param None + * @retval RTC current timestamp Subseconds value. + */ +uint32_t RTC_GetTimeStampSubSecond(void) +{ + /* Get timestamp subseconds values from the correspondent registers */ + return (uint32_t)(RTC->TSSSR); +} + +/** + * @} + */ + +/** @defgroup RTC_Group8 Tampers configuration functions + * @brief Tampers configuration functions + * +@verbatim + =============================================================================== + ##### Tampers configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the select Tamper pin edge. + * @param RTC_Tamper: Selected tamper pin. + * This parameter can be any combination of the following values: + * @arg RTC_Tamper_1: Select Tamper 1. + * @arg RTC_Tamper_2: Select Tamper 2. + * @arg RTC_Tamper_3: Select Tamper 3. + * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that + * stimulates tamper event. + * This parameter can be one of the following values: + * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event. + * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event. + * @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event. + * @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event. + * @retval None + */ +void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(RTC_Tamper)); + assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger)); + + if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge) + { + /* Configure the RTC_TAFCR register */ + RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1)); + } + else + { + /* Configure the RTC_TAFCR register */ + RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1); + } +} + +/** + * @brief Enables or Disables the Tamper detection. + * @param RTC_Tamper: Selected tamper pin. + * This parameter can be any combination of the following values: + * @arg RTC_Tamper_1: Select Tamper 1. + * @arg RTC_Tamper_2: Select Tamper 2. + * @arg RTC_Tamper_3: Select Tamper 3. + * @param NewState: new state of the tamper pin. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(RTC_Tamper)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected Tamper pin */ + RTC->TAFCR |= (uint32_t)RTC_Tamper; + } + else + { + /* Disable the selected Tamper pin */ + RTC->TAFCR &= (uint32_t)~RTC_Tamper; + } +} + +/** + * @brief Configures the Tampers Filter. + * @param RTC_TamperFilter: Specifies the tampers filter. + * This parameter can be one of the following values: + * @arg RTC_TamperFilter_Disable: Tamper filter is disabled. + * @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive + * samples at the active level + * @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive + * samples at the active level + * @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive + * samples at the active level + * @retval None + */ +void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter)); + + /* Clear TAMPFLT[1:0] bits in the RTC_TAFCR register */ + RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFLT); + + /* Configure the RTC_TAFCR register */ + RTC->TAFCR |= (uint32_t)RTC_TamperFilter; +} + +/** + * @brief Configures the Tampers Sampling Frequency. + * @param RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency. + * This parameter can be one of the following values: + * @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 32768 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 16384 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 8192 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 4096 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 2048 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 1024 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 512 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled + * with a frequency = RTCCLK / 256 + * @retval None + */ +void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq)); + + /* Clear TAMPFREQ[2:0] bits in the RTC_TAFCR register */ + RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFREQ); + + /* Configure the RTC_TAFCR register */ + RTC->TAFCR |= (uint32_t)RTC_TamperSamplingFreq; +} + +/** + * @brief Configures the Tampers Pins input Precharge Duration. + * @param RTC_TamperPrechargeDuration: Specifies the Tampers Pins input + * Precharge Duration. + * This parameter can be one of the following values: + * @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle + * @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle + * @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle + * @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle + * @retval None + */ +void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration)); + + /* Clear TAMPPRCH[1:0] bits in the RTC_TAFCR register */ + RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPPRCH); + + /* Configure the RTC_TAFCR register */ + RTC->TAFCR |= (uint32_t)RTC_TamperPrechargeDuration; +} + +/** + * @brief Enables or Disables the TimeStamp on Tamper Detection Event. + * @note The timestamp is valid even the TSE bit in tamper control register + * is reset. + * @param NewState: new state of the timestamp on tamper event. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Save timestamp on tamper detection event */ + RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPTS; + } + else + { + /* Tamper detection does not cause a timestamp to be saved */ + RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPTS; + } +} + +/** + * @brief Enables or Disables the Precharge of Tamper pin. + * @param NewState: new state of tamper pull up. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_TamperPullUpCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable precharge of the selected Tamper pin */ + RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPPUDIS; + } + else + { + /* Disable precharge of the selected Tamper pin */ + RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPPUDIS; + } +} + +/** + * @} + */ + +/** @defgroup RTC_Group9 Backup Data Registers configuration functions + * @brief Backup Data Registers configuration functions + * +@verbatim + =============================================================================== + ##### Backup Data Registers configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Writes a data in a specified RTC Backup data register. + * @param RTC_BKP_DR: RTC Backup data Register number. + * This parameter can be: RTC_BKP_DRx where x can be from 0 to 4 to + * specify the register. + * @param Data: Data to be written in the specified RTC Backup data register. + * @retval None + */ +void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_RTC_BKP(RTC_BKP_DR)); + + tmp = RTC_BASE + 0x50; + tmp += (RTC_BKP_DR * 4); + + /* Write the specified register */ + *(__IO uint32_t *)tmp = (uint32_t)Data; +} + +/** + * @brief Reads data from the specified RTC Backup data Register. + * @param RTC_BKP_DR: RTC Backup data Register number. + * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to + * specify the register. + * @retval None + */ +uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_RTC_BKP(RTC_BKP_DR)); + + tmp = RTC_BASE + 0x50; + tmp += (RTC_BKP_DR * 4); + + /* Read the specified register */ + return (*(__IO uint32_t *)tmp); +} + +/** + * @} + */ + +/** @defgroup RTC_Group10 Output Type Config configuration functions + * @brief Output Type Config configuration functions + * +@verbatim + =============================================================================== + ##### Output Type Config configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the RTC Output Pin mode. + * @param RTC_OutputType: specifies the RTC Output (PC13) pin mode. + * This parameter can be one of the following values: + * @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in + * Open Drain mode. + * @arg RTC_OutputType_PushPull: RTC Output (PC13) is configured in + * Push Pull mode. + * @retval None + */ +void RTC_OutputTypeConfig(uint32_t RTC_OutputType) +{ + /* Check the parameters */ + assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType)); + + RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE); + RTC->TAFCR |= (uint32_t)(RTC_OutputType); +} + +/** + * @} + */ + +/** @defgroup RTC_Group11 Shift control synchronisation functions + * @brief Shift control synchronisation functions + * +@verbatim + =============================================================================== + ##### Shift control synchronisation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the Synchronization Shift Control Settings. + * @note When REFCKON is set, firmware must not write to Shift control register + * @param RTC_ShiftAdd1S: Select to add or not 1 second to the time Calendar. + * This parameter can be one of the following values : + * @arg RTC_ShiftAdd1S_Set: Add one second to the clock calendar. + * @arg RTC_ShiftAdd1S_Reset: No effect. + * @param RTC_ShiftSubFS: Select the number of Second Fractions to Substitute. + * This parameter can be one any value from 0 to 0x7FFF. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Shift registers are configured + * - ERROR: RTC Shift registers are not configured +*/ +ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS) +{ + ErrorStatus status = ERROR; + uint32_t shpfcount = 0; + + /* Check the parameters */ + assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S)); + assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Check if a Shift is pending*/ + if ((RTC->ISR & RTC_ISR_SHPF) != RESET) + { + /* Wait until the shift is completed*/ + while (((RTC->ISR & RTC_ISR_SHPF) != RESET) && (shpfcount != SHPF_TIMEOUT)) + { + shpfcount++; + } + } + + /* Check if the Shift pending is completed or if there is no Shift operation at all*/ + if ((RTC->ISR & RTC_ISR_SHPF) == RESET) + { + /* check if the reference clock detection is disabled */ + if((RTC->CR & RTC_CR_REFCKON) == RESET) + { + /* Configure the Shift settings */ + RTC->SHIFTR = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S); + + if(RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + else + { + status = ERROR; + } + } + else + { + status = ERROR; + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return (ErrorStatus)(status); +} + +/** + * @} + */ + +/** @defgroup RTC_Group12 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + [..] All RTC interrupts are connected to the EXTI controller. + + (+) To enable the RTC Alarm interrupt, the following sequence is required: + (++) Configure and enable the EXTI Line 17 in interrupt mode and select the rising + edge sensitivity using the EXTI_Init() function. + (++) Configure and enable the RTC_Alarm IRQ channel in the NVIC using the NVIC_Init() + function. + (++) Configure the RTC to generate RTC alarms (Alarm A) using + the RTC_SetAlarm() and RTC_AlarmCmd() functions. + + (+) To enable the RTC Tamper interrupt, the following sequence is required: + (++) Configure and enable the EXTI Line 19 in interrupt mode and select the rising + edge sensitivity using the EXTI_Init() function. + (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init() + function. + (++) Configure the RTC to detect the RTC tamper event using the + RTC_TamperTriggerConfig() and RTC_TamperCmd() functions. + + (+) To enable the RTC TimeStamp interrupt, the following sequence is required: + (++) Configure and enable the EXTI Line 19 in interrupt mode and select the rising + edge sensitivity using the EXTI_Init() function. + (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init() + function. + (++) Configure the RTC to detect the RTC time-stamp event using the + RTC_TimeStampCmd() functions. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified RTC interrupts. + * @param RTC_IT: specifies the RTC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_TS: Time Stamp interrupt mask + * @arg RTC_IT_ALRA: Alarm A interrupt mask + * @arg RTC_IT_TAMP: Tamper event interrupt mask + * @param NewState: new state of the specified RTC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RTC_CONFIG_IT(RTC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + if (NewState != DISABLE) + { + /* Configure the Interrupts in the RTC_CR register */ + RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE); + /* Configure the Tamper Interrupt in the RTC_TAFCR */ + RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE); + } + else + { + /* Configure the Interrupts in the RTC_CR register */ + RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE); + /* Configure the Tamper Interrupt in the RTC_TAFCR */ + RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE); + } + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; +} + +/** + * @brief Checks whether the specified RTC flag is set or not. + * @param RTC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg RTC_FLAG_RECALPF: RECALPF event flag + * @arg RTC_FLAG_TAMP3F: Tamper 3 event flag + * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag + * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag + * @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag + * @arg RTC_FLAG_TSF: Time Stamp event flag + * @arg RTC_FLAG_ALRAF: Alarm A flag + * @arg RTC_FLAG_INITF: Initialization mode flag + * @arg RTC_FLAG_RSF: Registers Synchronized flag + * @arg RTC_FLAG_INITS: Registers Configured flag + * @retval The new state of RTC_FLAG (SET or RESET). + */ +FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); + + /* Get all the flags */ + tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK); + + /* Return the status of the flag */ + if ((tmpreg & RTC_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the RTC's pending flags. + * @param RTC_FLAG: specifies the RTC flag to clear. + * This parameter can be any combination of the following values: + * @arg RTC_FLAG_TAMP3F: Tamper 3 event flag + * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag + * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag + * @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag + * @arg RTC_FLAG_TSF: Time Stamp event flag + * @arg RTC_FLAG_ALRAF: Alarm A flag + * @arg RTC_FLAG_RSF: Registers Synchronized flag + * @retval None + */ +void RTC_ClearFlag(uint32_t RTC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); + + /* Clear the Flags in the RTC_ISR register */ + RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0001FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); +} + +/** + * @brief Checks whether the specified RTC interrupt has occurred or not. + * @param RTC_IT: specifies the RTC interrupt source to check. + * This parameter can be one of the following values: + * @arg RTC_IT_TS: Time Stamp interrupt + * @arg RTC_IT_ALRA: Alarm A interrupt + * @arg RTC_IT_TAMP1: Tamper1 event interrupt + * @arg RTC_IT_TAMP2: Tamper2 event interrupt + * @arg RTC_IT_TAMP3: Tamper3 event interrupt + * @retval The new state of RTC_IT (SET or RESET). + */ +ITStatus RTC_GetITStatus(uint32_t RTC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0, enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_RTC_GET_IT(RTC_IT)); + + /* Get the TAMPER Interrupt enable bit and pending bit */ + tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE)); + + /* Get the Interrupt enable Status */ + enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & ((RTC_IT >> (RTC_IT >> 18)) >> 15))); + + /* Get the Interrupt pending bit */ + tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4))); + + /* Get the status of the Interrupt */ + if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the RTC's interrupt pending bits. + * @param RTC_IT: specifies the RTC interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RTC_IT_TS: Time Stamp interrupt + * @arg RTC_IT_ALRA: Alarm A interrupt + * @arg RTC_IT_TAMP1: Tamper1 event interrupt + * @arg RTC_IT_TAMP2: Tamper2 event interrupt + * @arg RTC_IT_TAMP3: Tamper3 event interrupt + * @retval None + */ +void RTC_ClearITPendingBit(uint32_t RTC_IT) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_CLEAR_IT(RTC_IT)); + + /* Get the RTC_ISR Interrupt pending bits mask */ + tmpreg = (uint32_t)(RTC_IT >> 4); + + /* Clear the interrupt pending bits in the RTC_ISR register */ + RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); +} + +/** + * @} + */ + +/** + * @brief Converts a 2 digit decimal to BCD format. + * @param Value: Byte to be converted. + * @retval Converted byte + */ +static uint8_t RTC_ByteToBcd2(uint8_t Value) +{ + uint8_t bcdhigh = 0; + + while (Value >= 10) + { + bcdhigh++; + Value -= 10; + } + + return ((uint8_t)(bcdhigh << 4) | Value); +} + +/** + * @brief Convert from 2 digit BCD to Binary. + * @param Value: BCD value to be converted. + * @retval Converted word + */ +static uint8_t RTC_Bcd2ToByte(uint8_t Value) +{ + uint8_t tmp = 0; + tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; + return (tmp + (Value & (uint8_t)0x0F)); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_spi.c b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_spi.c new file mode 100644 index 0000000..0592d9a --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_spi.c @@ -0,0 +1,1296 @@ +/** + ****************************************************************************** + * @file stm32f0xx_spi.c + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Serial peripheral interface (SPI): + * + Initialization and Configuration + * + Data transfers functions + * + Hardware CRC Calculation + * + DMA transfers management + * + Interrupts and flags management + * + * @verbatim + + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE) + function for SPI1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE) + function for SPI2. + + (#) Enable SCK, MOSI, MISO and NSS GPIO clocks using + RCC_AHBPeriphClockCmd() function. + + (#) Peripherals alternate function: + (++) Connect the pin to the desired peripherals' Alternate + Function (AF) using GPIO_PinAFConfig() function. + (++) Configure the desired pin in alternate function by: + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF. + (++) Select the type, pull-up/pull-down and output speed via + GPIO_PuPd, GPIO_OType and GPIO_Speed members. + (++) Call GPIO_Init() function. + + (#) Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave + Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() + function.In I2S mode, program the Mode, Standard, Data Format, MCLK + Output, Audio frequency and Polarity using I2S_Init() function. + + (#) Enable the NVIC and the corresponding interrupt using the function + SPI_ITConfig() if you need to use interrupt mode. + + (#) When using the DMA mode + (++) Configure the DMA using DMA_Init() function. + (++) Active the needed channel Request using SPI_I2S_DMACmd() function. + + (#) Enable the SPI using the SPI_Cmd() function or enable the I2S using + I2S_Cmd(). + + (#) Enable the DMA using the DMA_Cmd() function when using DMA mode. + + (#) Optionally, you can enable/configure the following parameters without + re-initialization (i.e there is no need to call again SPI_Init() function): + (++) When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx) + is programmed as Data direction parameter using the SPI_Init() + function it can be possible to switch between SPI_Direction_Tx + or SPI_Direction_Rx using the SPI_BiDirectionalLineConfig() function. + (++) When SPI_NSS_Soft is selected as Slave Select Management parameter + using the SPI_Init() function it can be possible to manage the + NSS internal signal using the SPI_NSSInternalSoftwareConfig() function. + (++) Reconfigure the data size using the SPI_DataSizeConfig() function. + (++) Enable or disable the SS output using the SPI_SSOutputCmd() function. + + (#) To use the CRC Hardware calculation feature refer to the Peripheral + CRC hardware Calculation subsection. + + @endverbatim + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_spi.h" +#include "stm32f0xx_rcc.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup SPI + * @brief SPI driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* SPI registers Masks */ +#define CR1_CLEAR_MASK ((uint16_t)0x3040) +#define CR1_CLEAR_MASK2 ((uint16_t)0xFFFB) +#define CR2_LDMA_MASK ((uint16_t)0x9FFF) + +#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup SPI_Private_Functions + * @{ + */ + +/** @defgroup SPI_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides a set of functions allowing to initialize the SPI Direction, + SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud + Rate Prescaler, SPI First Bit and SPI CRC Polynomial. + + [..] The SPI_Init() function follows the SPI configuration procedures for Master mode + and Slave mode (details for these procedures are available in reference manual). + + [..] When the Software NSS management (SPI_InitStruct->SPI_NSS = SPI_NSS_Soft) is selected, + use the following function to manage the NSS bit: + void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); + + [..] In Master mode, when the Hardware NSS management (SPI_InitStruct->SPI_NSS = SPI_NSS_Hard) + is selected, use the follwoing function to enable the NSS output feature. + void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); + + [..] The NSS pulse mode can be managed by the SPI TI mode when enabling it using the following function: + void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); + And it can be managed by software in the SPI Motorola mode using this function: + void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); + + [..] This section provides also functions to initialize the I2S Mode, Standard, + Data Format, MCLK Output, Audio frequency and Polarity. + + [..] The I2S_Init() function follows the I2S configuration procedures for Master mode + and Slave mode. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the SPIx peripheral registers to their default + * reset values. + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @retval None + */ +void SPI_I2S_DeInit(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + if (SPIx == SPI1) + { + /* Enable SPI1 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); + /* Release SPI1 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); + } + else + { + if (SPIx == SPI2) + { + /* Enable SPI2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); + /* Release SPI2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); + } + } +} + +/** + * @brief Fills each SPI_InitStruct member with its default value. + * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized. + * @retval None + */ +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) +{ +/*--------------- Reset SPI init structure parameters values -----------------*/ + /* Initialize the SPI_Direction member */ + SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + /* Initialize the SPI_Mode member */ + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + /* Initialize the SPI_DataSize member */ + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + /* Initialize the SPI_CPOL member */ + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + /* Initialize the SPI_CPHA member */ + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + /* Initialize the SPI_NSS member */ + SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; + /* Initialize the SPI_BaudRatePrescaler member */ + SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + /* Initialize the SPI_FirstBit member */ + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + /* Initialize the SPI_CRCPolynomial member */ + SPI_InitStruct->SPI_CRCPolynomial = 7; +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the SPI_InitStruct. + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral. + * @retval None + */ +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) +{ + uint16_t tmpreg = 0; + + /* check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Check the SPI parameters */ + assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); + assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); + assert_param(IS_SPI_DATA_SIZE(SPI_InitStruct->SPI_DataSize)); + assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); + assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); + assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); + assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); + + /*---------------------------- SPIx CR1 Configuration ------------------------*/ + /* Get the SPIx CR1 value */ + tmpreg = SPIx->CR1; + /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, CPOL and CPHA bits */ + tmpreg &= CR1_CLEAR_MASK; + /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler + master/slave mode, CPOL and CPHA */ + /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ + /* Set SSM, SSI bit according to SPI_NSS values */ + /* Set LSBFirst bit according to SPI_FirstBit value */ + /* Set BR bits according to SPI_BaudRatePrescaler value */ + /* Set CPOL bit according to SPI_CPOL value */ + /* Set CPHA bit according to SPI_CPHA value */ + tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_FirstBit | + SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA | + SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler); + /* Write to SPIx CR1 */ + SPIx->CR1 = tmpreg; + /*-------------------------Data Size Configuration -----------------------*/ + /* Get the SPIx CR2 value */ + tmpreg = SPIx->CR2; + /* Clear DS[3:0] bits */ + tmpreg &=(uint16_t)~SPI_CR2_DS; + /* Configure SPIx: Data Size */ + tmpreg |= (uint16_t)(SPI_InitStruct->SPI_DataSize); + /* Write to SPIx CR2 */ + SPIx->CR2 = tmpreg; + + /*---------------------------- SPIx CRCPOLY Configuration --------------------*/ + /* Write to SPIx CRCPOLY */ + SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; + + /*---------------------------- SPIx CR1 Configuration ------------------------*/ + /* Get the SPIx CR1 value */ + tmpreg = SPIx->CR1; + /* Clear MSTR bit */ + tmpreg &= CR1_CLEAR_MASK2; + /* Configure SPIx: master/slave mode */ + /* Set MSTR bit according to SPI_Mode */ + tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Mode); + /* Write to SPIx CR1 */ + SPIx->CR1 = tmpreg; + + /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ + SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD); +} + +/** + * @brief Fills each I2S_InitStruct member with its default value. + * @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized. + * @retval None + */ +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct) +{ +/*--------------- Reset I2S init structure parameters values -----------------*/ + /* Initialize the I2S_Mode member */ + I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; + + /* Initialize the I2S_Standard member */ + I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; + + /* Initialize the I2S_DataFormat member */ + I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; + + /* Initialize the I2S_MCLKOutput member */ + I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; + + /* Initialize the I2S_AudioFreq member */ + I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; + + /* Initialize the I2S_CPOL member */ + I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the I2S_InitStruct. + * @param SPIx: where x can be 1 to select the SPI peripheral. + * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral + * configured in I2S mode. + * @note + * The function calculates the optimal prescaler needed to obtain the most + * accurate audio frequency (depending on the I2S clock source, the PLL values + * and the product configuration). But in case the prescaler value is greater + * than 511, the default value (0x02) will be configured instead. + * @retval None + */ +void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) +{ + uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; + uint32_t tmp = 0; + RCC_ClocksTypeDef RCC_Clocks; + uint32_t sourceclock = 0; + + /* Check the I2S parameters */ + assert_param(IS_SPI_1_PERIPH(SPIx)); + assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); + assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); + assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); + assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput)); + assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq)); + assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); + +/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ + /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ + SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; + SPIx->I2SPR = 0x0002; + + /* Get the I2SCFGR register value */ + tmpreg = SPIx->I2SCFGR; + + /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ + if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) + { + i2sodd = (uint16_t)0; + i2sdiv = (uint16_t)2; + } + /* If the requested audio frequency is not the default, compute the prescaler */ + else + { + /* Check the frame length (For the Prescaler computing) */ + if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) + { + /* Packet length is 16 bits */ + packetlength = 1; + } + else + { + /* Packet length is 32 bits */ + packetlength = 2; + } + + /* I2S Clock source is System clock: Get System Clock frequency */ + RCC_GetClocksFreq(&RCC_Clocks); + + /* Get the source clock value: based on System Clock value */ + sourceclock = RCC_Clocks.SYSCLK_Frequency; + + /* Compute the Real divider depending on the MCLK output state with a floating point */ + if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) + { + /* MCLK output is enabled */ + tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + else + { + /* MCLK output is disabled */ + tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + + /* Remove the floating point */ + tmp = tmp / 10; + + /* Check the parity of the divider */ + i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); + + /* Compute the i2sdiv prescaler */ + i2sdiv = (uint16_t)((tmp - i2sodd) / 2); + + /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ + i2sodd = (uint16_t) (i2sodd << 8); + } + + /* Test if the divider is 1 or 0 or greater than 0xFF */ + if ((i2sdiv < 2) || (i2sdiv > 0xFF)) + { + /* Set the default values */ + i2sdiv = 2; + i2sodd = 0; + } + + /* Write to SPIx I2SPR register the computed value */ + SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); + + /* Configure the I2S with the SPI_InitStruct values */ + tmpreg |= (uint16_t)(SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \ + (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ + (uint16_t)I2S_InitStruct->I2S_CPOL)))); + + /* Write to SPIx I2SCFGR */ + SPIx->I2SCFGR = tmpreg; +} + +/** + * @brief Enables or disables the specified SPI peripheral. + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @param NewState: new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral */ + SPIx->CR1 |= SPI_CR1_SPE; + } + else + { + /* Disable the selected SPI peripheral */ + SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE); + } +} + +/** + * @brief Enables or disables the TI Mode. + * @note This function can be called only after the SPI_Init() function has + * been called. + * @note When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA + * are not taken into consideration and are configured by hardware + * respectively to the TI mode requirements. + * @param SPIx: where x can be 1 to select the SPI peripheral. + * @param NewState: new state of the selected SPI TI communication mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_1_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TI mode for the selected SPI peripheral */ + SPIx->CR2 |= SPI_CR2_FRF; + } + else + { + /* Disable the TI mode for the selected SPI peripheral */ + SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRF); + } +} + +/** + * @brief Enables or disables the specified SPI peripheral (in I2S mode). + * @param SPIx: where x can be 1 to select the SPI peripheral. + * @param NewState: new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_1_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral in I2S mode */ + SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE; + } + else + { + /* Disable the selected SPI peripheral in I2S mode */ + SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE); + } +} + +/** + * @brief Configures the data size for the selected SPI. + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @param SPI_DataSize: specifies the SPI data size. + * For the SPIx peripheral this parameter can be one of the following values: + * @arg SPI_DataSize_4b: Set data size to 4 bits + * @arg SPI_DataSize_5b: Set data size to 5 bits + * @arg SPI_DataSize_6b: Set data size to 6 bits + * @arg SPI_DataSize_7b: Set data size to 7 bits + * @arg SPI_DataSize_8b: Set data size to 8 bits + * @arg SPI_DataSize_9b: Set data size to 9 bits + * @arg SPI_DataSize_10b: Set data size to 10 bits + * @arg SPI_DataSize_11b: Set data size to 11 bits + * @arg SPI_DataSize_12b: Set data size to 12 bits + * @arg SPI_DataSize_13b: Set data size to 13 bits + * @arg SPI_DataSize_14b: Set data size to 14 bits + * @arg SPI_DataSize_15b: Set data size to 15 bits + * @arg SPI_DataSize_16b: Set data size to 16 bits + * @retval None + */ +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) +{ + uint16_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DATA_SIZE(SPI_DataSize)); + /* Read the CR2 register */ + tmpreg = SPIx->CR2; + /* Clear DS[3:0] bits */ + tmpreg &= (uint16_t)~SPI_CR2_DS; + /* Set new DS[3:0] bits value */ + tmpreg |= SPI_DataSize; + SPIx->CR2 = tmpreg; +} + +/** + * @brief Configures the FIFO reception threshold for the selected SPI. + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @param SPI_RxFIFOThreshold: specifies the FIFO reception threshold. + * This parameter can be one of the following values: + * @arg SPI_RxFIFOThreshold_HF: RXNE event is generated if the FIFO + * level is greater or equal to 1/2. + * @arg SPI_RxFIFOThreshold_QF: RXNE event is generated if the FIFO + * level is greater or equal to 1/4. + * @retval None + */ +void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_RX_FIFO_THRESHOLD(SPI_RxFIFOThreshold)); + + /* Clear FRXTH bit */ + SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRXTH); + + /* Set new FRXTH bit value */ + SPIx->CR2 |= SPI_RxFIFOThreshold; +} + +/** + * @brief Selects the data transfer direction in bidirectional mode for the specified SPI. + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @param SPI_Direction: specifies the data transfer direction in bidirectional mode. + * This parameter can be one of the following values: + * @arg SPI_Direction_Tx: Selects Tx transmission direction + * @arg SPI_Direction_Rx: Selects Rx receive direction + * @retval None + */ +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DIRECTION(SPI_Direction)); + if (SPI_Direction == SPI_Direction_Tx) + { + /* Set the Tx only mode */ + SPIx->CR1 |= SPI_Direction_Tx; + } + else + { + /* Set the Rx only mode */ + SPIx->CR1 &= SPI_Direction_Rx; + } +} + +/** + * @brief Configures internally by software the NSS pin for the selected SPI. + * @note - This function can be called only after the SPI_Init() function has + * been called. + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. + * This parameter can be one of the following values: + * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally + * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally + * @retval None + */ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); + + if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) + { + /* Set NSS pin internally by software */ + SPIx->CR1 |= SPI_NSSInternalSoft_Set; + } + else + { + /* Reset NSS pin internally by software */ + SPIx->CR1 &= SPI_NSSInternalSoft_Reset; + } +} + +/** + * @brief Enables or disables the SS output for the selected SPI. + * @note - This function can be called only after the SPI_Init() function has + * been called and the NSS hardware management mode is selected. + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @param NewState: new state of the SPIx SS output. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI SS output */ + SPIx->CR2 |= SPI_CR2_SSOE; + } + else + { + /* Disable the selected SPI SS output */ + SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE); + } +} + +/** + * @brief Enables or disables the NSS pulse management mode. + * @note This function can be called only after the SPI_Init() function has + * been called. + * @note When TI mode is selected, the control bits NSSP is not taken into + * consideration and are configured by hardware respectively to the + * TI mode requirements. + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @param NewState: new state of the NSS pulse management mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the NSS pulse management mode */ + SPIx->CR2 |= SPI_CR2_NSSP; + } + else + { + /* Disable the NSS pulse management mode */ + SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_NSSP); + } +} + +/** + * @} + */ + +/** @defgroup SPI_Group2 Data transfers functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### Data transfers functions ##### + =============================================================================== + [..] This section provides a set of functions allowing to manage the SPI or I2S + data transfers. + + [..] In reception, data are received and then stored into an internal Rx buffer while + In transmission, data are first stored into an internal Tx buffer before being + transmitted. + + [..] The read access of the SPI_DR register can be done using + SPI_ReceiveData8() (when data size is equal or inferior than 8bits) and. + SPI_I2S_ReceiveData16() (when data size is superior than 8bits)function + and returns the Rx buffered value. Whereas a write access to the SPI_DR + can be done using SPI_SendData8() (when data size is equal or inferior than 8bits) + and SPI_I2S_SendData16() (when data size is superior than 8bits) function + and stores the written data into Tx buffer. + +@endverbatim + * @{ + */ + +/** + * @brief Transmits a Data through the SPIx/I2Sx peripheral. + * @param SPIx: where x can be 1 or 2 in SPI mode to select the SPI peripheral. + * @param Data: Data to be transmitted. + * @retval None + */ +void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data) +{ + uint32_t spixbase = 0x00; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + spixbase = (uint32_t)SPIx; + spixbase += 0x0C; + + *(__IO uint8_t *) spixbase = Data; +} + +/** + * @brief Transmits a Data through the SPIx/I2Sx peripheral. + * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select + * the SPI peripheral. + * @param Data: Data to be transmitted. + * @retval None + */ +void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + SPIx->DR = (uint16_t)Data; +} + +/** + * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. + * @param SPIx: where x can be 1 or 2 in SPI mode to select the SPI peripheral. + * @retval The value of the received data. + */ +uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx) +{ + uint32_t spixbase = 0x00; + + spixbase = (uint32_t)SPIx; + spixbase += 0x0C; + + return *(__IO uint8_t *) spixbase; +} + +/** + * @brief Returns the most recent received data by the SPIx peripheral. + * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select + * the SPI peripheral. + * @retval The value of the received data. + */ +uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx) +{ + return SPIx->DR; +} +/** + * @} + */ + +/** @defgroup SPI_Group3 Hardware CRC Calculation functions + * @brief Hardware CRC Calculation functions + * +@verbatim + =============================================================================== + ##### Hardware CRC Calculation functions ##### + =============================================================================== + [..] This section provides a set of functions allowing to manage the SPI CRC hardware + calculation.SPI communication using CRC is possible through the following procedure: + + (#) Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler, + Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() + function. + (#) Enable the CRC calculation using the SPI_CalculateCRC() function. + (#) Enable the SPI using the SPI_Cmd() function + (#) Before writing the last data to the TX buffer, set the CRCNext bit using the + SPI_TransmitCRC() function to indicate that after transmission of the last + data, the CRC should be transmitted. + (#) After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT + bit is reset. The CRC is also received and compared against the SPI_RXCRCR + value. + If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt + can be generated when the SPI_I2S_IT_ERR interrupt is enabled. + + -@- + (+@) It is advised to don't read the calculate CRC values during the communication. + (+@) When the SPI is in slave mode, be careful to enable CRC calculation only + when the clock is stable, that is, when the clock is in the steady state. + If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive + to the SCK slave input clock as soon as CRCEN is set, and this, whatever + the value of the SPE bit. + (+@) With high bitrate frequencies, be careful when transmitting the CRC. + As the number of used CPU cycles has to be as low as possible in the CRC + transfer phase, it is forbidden to call software functions in the CRC + transmission sequence to avoid errors in the last data and CRC reception. + In fact, CRCNEXT bit has to be written before the end of the transmission/reception + of the last data. + (+@) For high bit rate frequencies, it is advised to use the DMA mode to avoid the + degradation of the SPI speed performance due to CPU accesses impacting the + SPI bandwidth. + (+@) When the STM32F0xx are configured as slaves and the NSS hardware mode is + used, the NSS pin needs to be kept low between the data phase and the CRC + phase. + (+@) When the SPI is configured in slave mode with the CRC feature enabled, CRC + calculation takes place even if a high level is applied on the NSS pin. + This may happen for example in case of a multislave environment where the + communication master addresses slaves alternately. + (+@) Between a slave deselection (high level on NSS) and a new slave selection + (low level on NSS), the CRC value should be cleared on both master and slave + sides in order to resynchronize the master and slave for their respective + CRC calculation. + + -@- To clear the CRC, follow the procedure below: + (#@) Disable SPI using the SPI_Cmd() function + (#@) Disable the CRC calculation using the SPI_CalculateCRC() function. + (#@) Enable the CRC calculation using the SPI_CalculateCRC() function. + (#@) Enable SPI using the SPI_Cmd() function. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the CRC calculation length for the selected SPI. + * @note - This function can be called only after the SPI_Init() function has + * been called. + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @param SPI_CRCLength: specifies the SPI CRC calculation length. + * This parameter can be one of the following values: + * @arg SPI_CRCLength_8b: Set CRC Calculation to 8 bits + * @arg SPI_CRCLength_16b: Set CRC Calculation to 16 bits + * @retval None + */ +void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_CRC_LENGTH(SPI_CRCLength)); + + /* Clear CRCL bit */ + SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCL); + + /* Set new CRCL bit value */ + SPIx->CR1 |= SPI_CRCLength; +} + +/** + * @brief Enables or disables the CRC value calculation of the transferred bytes. + * @note - This function can be called only after the SPI_Init() function has + * been called. + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @param NewState: new state of the SPIx CRC value calculation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected SPI CRC calculation */ + SPIx->CR1 |= SPI_CR1_CRCEN; + } + else + { + /* Disable the selected SPI CRC calculation */ + SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN); + } +} + +/** + * @brief Transmit the SPIx CRC value. + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @retval None + */ +void SPI_TransmitCRC(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Enable the selected SPI CRC transmission */ + SPIx->CR1 |= SPI_CR1_CRCNEXT; +} + +/** + * @brief Returns the transmit or the receive CRC register value for the specified SPI. + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @param SPI_CRC: specifies the CRC register to be read. + * This parameter can be one of the following values: + * @arg SPI_CRC_Tx: Selects Tx CRC register + * @arg SPI_CRC_Rx: Selects Rx CRC register + * @retval The selected CRC register value.. + */ +uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) +{ + uint16_t crcreg = 0; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_CRC(SPI_CRC)); + + if (SPI_CRC != SPI_CRC_Rx) + { + /* Get the Tx CRC register */ + crcreg = SPIx->TXCRCR; + } + else + { + /* Get the Rx CRC register */ + crcreg = SPIx->RXCRCR; + } + /* Return the selected CRC register */ + return crcreg; +} + +/** + * @brief Returns the CRC Polynomial register value for the specified SPI. + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @retval The CRC Polynomial register value. + */ +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Return the CRC polynomial register */ + return SPIx->CRCPR; +} + +/** + * @} + */ + +/** @defgroup SPI_Group4 DMA transfers management functions + * @brief DMA transfers management functions + * +@verbatim + =============================================================================== + ##### DMA transfers management functions ##### + =============================================================================== + [..] This section provides two functions that can be used only in DMA mode. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the SPIx/I2Sx DMA interface. + * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select + * the SPI peripheral. + * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request + * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request + * @param NewState: new state of the selected SPI DMA transfer request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_I2S_DMA_REQ(SPI_I2S_DMAReq)); + + if (NewState != DISABLE) + { + /* Enable the selected SPI DMA requests */ + SPIx->CR2 |= SPI_I2S_DMAReq; + } + else + { + /* Disable the selected SPI DMA requests */ + SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq; + } +} + +/** + * @brief Configures the number of data to transfer type(Even/Odd) for the DMA + * last transfers and for the selected SPI. + * @note - This function have a meaning only if DMA mode is selected and if + * the packing mode is used (data length <= 8 and DMA transfer size halfword) + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @param SPI_LastDMATransfer: specifies the SPI last DMA transfers state. + * This parameter can be one of the following values: + * @arg SPI_LastDMATransfer_TxEvenRxEven: Number of data for transmission Even + * and number of data for reception Even. + * @arg SPI_LastDMATransfer_TxOddRxEven: Number of data for transmission Odd + * and number of data for reception Even. + * @arg SPI_LastDMATransfer_TxEvenRxOdd: Number of data for transmission Even + * and number of data for reception Odd. + * @arg SPI_LastDMATransfer_TxOddRxOdd: Number of data for transmission Odd + * and number of data for reception Odd. + * @retval None + */ +void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_LAST_DMA_TRANSFER(SPI_LastDMATransfer)); + + /* Clear LDMA_TX and LDMA_RX bits */ + SPIx->CR2 &= CR2_LDMA_MASK; + + /* Set new LDMA_TX and LDMA_RX bits value */ + SPIx->CR2 |= SPI_LastDMATransfer; +} + +/** + * @} + */ + +/** @defgroup SPI_Group5 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + [..] This section provides a set of functions allowing to configure the SPI/I2S Interrupts + sources and check or clear the flags or pending bits status. + The user should identify which mode will be used in his application to manage + the communication: Polling mode, Interrupt mode or DMA mode. + + *** Polling Mode *** + ==================== + [..] In Polling Mode, the SPI/I2S communication can be managed by 9 flags: + (#) SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register + (#) SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register + (#) SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI. + (#) SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur + (#) SPI_FLAG_MODF : to indicate if a Mode Fault error occur + (#) SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur + (#) SPI_I2S_FLAG_FRE: to indicate a Frame Format error occurs. + (#) I2S_FLAG_UDR: to indicate an Underrun error occurs. + (#) I2S_FLAG_CHSIDE: to indicate Channel Side. + + [..] + (@)Do not use the BSY flag to handle each data transmission or reception. It is better + to use the TXE and RXNE flags instead. + + [..] In this Mode it is advised to use the following functions: + (+) FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); + (+) void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); + + *** Interrupt Mode *** + ====================== + [..] In Interrupt Mode, the SPI/I2S communication can be managed by 3 interrupt sources + and 5 pending bits: + [..] Pending Bits: + (#) SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register + (#) SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register + (#) SPI_I2S_IT_OVR : to indicate if an Overrun error occur + (#) I2S_IT_UDR : to indicate an Underrun Error occurs. + (#) SPI_I2S_FLAG_FRE : to indicate a Frame Format error occurs. + + [..] Interrupt Source: + (#) SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty + interrupt. + (#) SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not + empty interrupt. + (#) SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt. + + [..] In this Mode it is advised to use the following functions: + (+) void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); + (+) ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); + + *** FIFO Status *** + =================== + [..] It is possible to monitor the FIFO status when a transfer is ongoing using the + following function: + (+) uint32_t SPI_GetFIFOStatus(uint8_t SPI_FIFO_Direction); + + *** DMA Mode *** + ================ + [..] In DMA Mode, the SPI communication can be managed by 2 DMA Channel + requests: + (#) SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request. + (#) SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request. + + [..] In this Mode it is advised to use the following function: + (+) void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState). + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified SPI/I2S interrupts. + * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select + * the SPI peripheral. + * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. + * This parameter can be one of the following values: + * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask + * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask + * @arg SPI_I2S_IT_ERR: Error interrupt mask + * @param NewState: new state of the specified SPI interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) +{ + uint16_t itpos = 0, itmask = 0 ; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); + + /* Get the SPI IT index */ + itpos = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = (uint16_t)1 << (uint16_t)itpos; + + if (NewState != DISABLE) + { + /* Enable the selected SPI interrupt */ + SPIx->CR2 |= itmask; + } + else + { + /* Disable the selected SPI interrupt */ + SPIx->CR2 &= (uint16_t)~itmask; + } +} + +/** + * @brief Returns the current SPIx Transmission FIFO filled level. + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @retval The Transmission FIFO filling state. + * - SPI_TransmissionFIFOStatus_Empty: when FIFO is empty + * - SPI_TransmissionFIFOStatus_1QuarterFull: if more than 1 quarter-full. + * - SPI_TransmissionFIFOStatus_HalfFull: if more than 1 half-full. + * - SPI_TransmissionFIFOStatus_Full: when FIFO is full. + */ +uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx) +{ + /* Get the SPIx Transmission FIFO level bits */ + return (uint16_t)((SPIx->SR & SPI_SR_FTLVL)); +} + +/** + * @brief Returns the current SPIx Reception FIFO filled level. + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @retval The Reception FIFO filling state. + * - SPI_ReceptionFIFOStatus_Empty: when FIFO is empty + * - SPI_ReceptionFIFOStatus_1QuarterFull: if more than 1 quarter-full. + * - SPI_ReceptionFIFOStatus_HalfFull: if more than 1 half-full. + * - SPI_ReceptionFIFOStatus_Full: when FIFO is full. + */ +uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx) +{ + /* Get the SPIx Reception FIFO level bits */ + return (uint16_t)((SPIx->SR & SPI_SR_FRLVL)); +} + +/** + * @brief Checks whether the specified SPI flag is set or not. + * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select + * the SPI peripheral. + * @param SPI_I2S_FLAG: specifies the SPI flag to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag. + * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag. + * @arg SPI_I2S_FLAG_BSY: Busy flag. + * @arg SPI_I2S_FLAG_OVR: Overrun flag. + * @arg SPI_I2S_FLAG_MODF: Mode Fault flag. + * @arg SPI_I2S_FLAG_CRCERR: CRC Error flag. + * @arg SPI_I2S_FLAG_FRE: TI frame format error flag. + * @arg I2S_FLAG_UDR: Underrun Error flag. + * @arg I2S_FLAG_CHSIDE: Channel Side flag. + * @retval The new state of SPI_I2S_FLAG (SET or RESET). + */ +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); + + /* Check the status of the specified SPI flag */ + if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) + { + /* SPI_I2S_FLAG is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_FLAG is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the SPIx CRC Error (CRCERR) flag. + * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. + * @param SPI_I2S_FLAG: specifies the SPI flag to clear. + * This function clears only CRCERR flag. + * @note OVR (OverRun error) flag is cleared by software sequence: a read + * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by + * a read operation to SPI_SR register (SPI_I2S_GetFlagStatus()). + * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write + * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by + * a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI). + * @retval None + */ +void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_CLEAR_FLAG(SPI_I2S_FLAG)); + + /* Clear the selected SPI CRC Error (CRCERR) flag */ + SPIx->SR = (uint16_t)~SPI_I2S_FLAG; +} + +/** + * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. + * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select + * the SPI peripheral. + * @param SPI_I2S_IT: specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt. + * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt. + * @arg SPI_IT_MODF: Mode Fault interrupt. + * @arg SPI_I2S_IT_OVR: Overrun interrupt. + * @arg I2S_IT_UDR: Underrun interrupt. + * @arg SPI_I2S_IT_FRE: Format Error interrupt. + * @retval The new state of SPI_I2S_IT (SET or RESET). + */ +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); + + /* Get the SPI_I2S_IT index */ + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + + /* Get the SPI_I2S_IT IT mask */ + itmask = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = 0x01 << itmask; + + /* Get the SPI_I2S_IT enable bit status */ + enablestatus = (SPIx->CR2 & itmask) ; + + /* Check the status of the specified SPI interrupt */ + if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus) + { + /* SPI_I2S_IT is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_IT is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_IT status */ + return bitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_syscfg.c b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_syscfg.c new file mode 100644 index 0000000..fff2805 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_syscfg.c @@ -0,0 +1,304 @@ +/** + ****************************************************************************** + * @file stm32f0xx_syscfg.c + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the SYSCFG peripheral: + * + Remapping the memory mapped at 0x00000000 + * + Remapping the DMA channels + * + Enabling I2C fast mode plus driving capability for I2C pins + * + Configuring the EXTI lines connection to the GPIO port + * + Configuring the CFGR2 features (Connecting some internal signal + * to the break input of TIM1) + * + * @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The SYSCFG registers can be accessed only when the SYSCFG + interface APB clock is enabled. + To enable SYSCFG APB clock use: + RCC_APBPeriphClockCmd(RCC_APBPeriph_SYSCFG, ENABLE). + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_syscfg.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup SYSCFG + * @brief SYSCFG driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup SYSCFG_Private_Functions + * @{ + */ + +/** @defgroup SYSCFG_Group1 SYSCFG Initialization and Configuration functions + * @brief SYSCFG Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### SYSCFG Initialization and Configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the SYSCFG registers to their default reset values. + * @param None + * @retval None + * @note MEM_MODE bits are not affected by APB reset. + * MEM_MODE bits took the value from the user option bytes. + * @note CFGR2 register is not affected by APB reset. + * CLABBB configuration bits are locked when set. + * To unlock the configuration, perform a system reset. + */ +void SYSCFG_DeInit(void) +{ + /* Set SYSCFG_CFGR1 register to reset value without affecting MEM_MODE bits */ + SYSCFG->CFGR1 &= SYSCFG_CFGR1_MEM_MODE; + /* Set EXTICRx registers to reset value */ + SYSCFG->EXTICR[0] = 0; + SYSCFG->EXTICR[1] = 0; + SYSCFG->EXTICR[2] = 0; + SYSCFG->EXTICR[3] = 0; + /* Set CFGR2 register to reset value: clear SRAM parity error flag */ + SYSCFG->CFGR2 |= (uint32_t) SYSCFG_CFGR2_SRAM_PE; +} + +/** + * @brief Configures the memory mapping at address 0x00000000. + * @param SYSCFG_MemoryRemap: selects the memory remapping. + * This parameter can be one of the following values: + * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000 + * @arg SYSCFG_MemoryRemap_SystemMemory: System Flash memory mapped at 0x00000000 + * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000 + * @retval None + */ +void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap) +{ + uint32_t tmpctrl = 0; + + /* Check the parameter */ + assert_param(IS_SYSCFG_MEMORY_REMAP(SYSCFG_MemoryRemap)); + + /* Get CFGR1 register value */ + tmpctrl = SYSCFG->CFGR1; + + /* Clear MEM_MODE bits */ + tmpctrl &= (uint32_t) (~SYSCFG_CFGR1_MEM_MODE); + + /* Set the new MEM_MODE bits value */ + tmpctrl |= (uint32_t) SYSCFG_MemoryRemap; + + /* Set CFGR1 register with the new memory remap configuration */ + SYSCFG->CFGR1 = tmpctrl; +} + +/** + * @brief Configure the DMA channels remapping. + * @param SYSCFG_DMARemap: selects the DMA channels remap. + * This parameter can be one of the following values: + * @arg SYSCFG_DMARemap_TIM17: Remap TIM17 DMA requests from channel1 to channel2 + * @arg SYSCFG_DMARemap_TIM16: Remap TIM16 DMA requests from channel3 to channel4 + * @arg SYSCFG_DMARemap_USART1Rx: Remap USART1 Rx DMA requests from channel3 to channel5 + * @arg SYSCFG_DMARemap_USART1Tx: Remap USART1 Tx DMA requests from channel2 to channel4 + * @arg SYSCFG_DMARemap_ADC1: Remap ADC1 DMA requests from channel1 to channel2 + * @param NewState: new state of the DMA channel remapping. + * This parameter can be: ENABLE or DISABLE. + * @note When enabled, DMA channel of the selected peripheral is remapped + * @note When disabled, Default DMA channel is mapped to the selected peripheral + * @note + * By default TIM17 DMA requests is mapped to channel 1 + * use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Enable) + * to remap TIM17 DMA requests to channel 2 + * use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Disable) + * to map TIM17 DMA requests to channel 1 (default mapping) + * @retval None + */ +void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_DMA_REMAP(SYSCFG_DMARemap)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Remap the DMA channel */ + SYSCFG->CFGR1 |= (uint32_t)SYSCFG_DMARemap; + } + else + { + /* use the default DMA channel mapping */ + SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_DMARemap); + } +} + +/** + * @brief Configure the I2C fast mode plus driving capability. + * @param SYSCFG_I2CFastModePlus: selects the pin. + * This parameter can be one of the following values: + * @arg SYSCFG_I2CFastModePlus_PB6: Configure fast mode plus driving capability for PB6 + * @arg SYSCFG_I2CFastModePlus_PB7: Configure fast mode plus driving capability for PB7 + * @arg SYSCFG_I2CFastModePlus_PB8: Configure fast mode plus driving capability for PB8 + * @arg SYSCFG_I2CFastModePlus_PB9: Configure fast mode plus driving capability for PB9 + * @param NewState: new state of the DMA channel remapping. + * This parameter can be: ENABLE or DISABLE. + * @note ENABLE: Enable fast mode plus driving capability for selected pin + * @note DISABLE: Disable fast mode plus driving capability for selected pin + * @retval None + */ +void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_I2C_FMP(SYSCFG_I2CFastModePlus)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable fast mode plus driving capability for selected pin */ + SYSCFG->CFGR1 |= (uint32_t)SYSCFG_I2CFastModePlus; + } + else + { + /* Disable fast mode plus driving capability for selected pin */ + SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_I2CFastModePlus); + } +} + +/** + * @brief Selects the GPIO pin used as EXTI Line. + * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source + * for EXTI lines where x can be (A, B, C, D or F). + * @param EXTI_PinSourcex: specifies the EXTI line to be configured. + * This parameter can be EXTI_PinSourcex where x can be (0..15) + * @retval None + */ +void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex) +{ + uint32_t tmp = 0x00; + + /* Check the parameters */ + assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx)); + assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex)); + + tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)); + SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp; + SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03))); +} + +/** + * @brief Connect the selected parameter to the break input of TIM1. + * @note The selected configuration is locked and can be unlocked by system reset + * @param SYSCFG_Break: selects the configuration to be connected to break + * input of TIM1 + * This parameter can be any combination of the following values: + * @arg SYSCFG_Break_PVD: Connects the PVD event to the Break Input of TIM1. + * @arg SYSCFG_Break_SRAMParity: Connects the SRAM_PARITY error signal to the Break Input of TIM1 . + * @arg SYSCFG_Break_Lockup: Connects Lockup output of CortexM0 to the break input of TIM1. + * @retval None + */ +void SYSCFG_BreakConfig(uint32_t SYSCFG_Break) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_LOCK_CONFIG(SYSCFG_Break)); + + SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Break; +} + +/** + * @brief Checks whether the specified SYSCFG flag is set or not. + * @param SYSCFG_Flag: specifies the SYSCFG flag to check. + * This parameter can be one of the following values: + * @arg SYSCFG_FLAG_PE: SRAM parity error flag. + * @retval The new state of SYSCFG_Flag (SET or RESET). + */ +FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameter */ + assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag)); + + /* Check the status of the specified SPI flag */ + if ((SYSCFG->CFGR2 & SYSCFG_CFGR2_SRAM_PE) != (uint32_t)RESET) + { + /* SYSCFG_Flag is set */ + bitstatus = SET; + } + else + { + /* SYSCFG_Flag is reset */ + bitstatus = RESET; + } + /* Return the SYSCFG_Flag status */ + return bitstatus; +} + +/** + * @brief Clear the selected SYSCFG flag. + * @param SYSCFG_Flag: selects the flag to be cleared. + * This parameter can be any combination of the following values: + * @arg SYSCFG_FLAG_PE: SRAM parity error flag. + * @retval None + */ +void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag)); + + SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Flag; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_tim.c b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_tim.c new file mode 100644 index 0000000..41789f3 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_tim.c @@ -0,0 +1,3208 @@ +/** + ****************************************************************************** + * @file stm32f0xx_tim.c + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the TIM peripheral: + * + TimeBase management + * + Output Compare management + * + Input Capture management + * + Interrupts, DMA and flags management + * + Clocks management + * + Synchronization management + * + Specific interface management + * + Specific remapping management + * + * @verbatim + + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] This driver provides functions to configure and program the TIM + of all STM32F0xx devices These functions are split in 8 groups: + (#) TIM TimeBase management: this group includes all needed functions + to configure the TM Timebase unit: + (++) Set/Get Prescaler. + (++) Set/Get Autoreload. + (++) Counter modes configuration. + (++) Set Clock division. + (++) Select the One Pulse mode. + (++) Update Request Configuration. + (++) Update Disable Configuration. + (++) Auto-Preload Configuration. + (++) Enable/Disable the counter. + + (#) TIM Output Compare management: this group includes all needed + functions to configure the Capture/Compare unit used in Output + compare mode: + (++) Configure each channel, independently, in Output Compare mode. + (++) Select the output compare modes. + (++) Select the Polarities of each channel. + (++) Set/Get the Capture/Compare register values. + (++) Select the Output Compare Fast mode. + (++) Select the Output Compare Forced mode. + (++) Output Compare-Preload Configuration. + (++) Clear Output Compare Reference. + (++) Select the OCREF Clear signal. + (++) Enable/Disable the Capture/Compare Channels. + + (#) TIM Input Capture management: this group includes all needed + functions to configure the Capture/Compare unit used in + Input Capture mode: + (++) Configure each channel in input capture mode. + (++) Configure Channel1/2 in PWM Input mode. + (++) Set the Input Capture Prescaler. + (++) Get the Capture/Compare values. + + (#) Advanced-control timers (TIM1) specific features + (++) Configures the Break input, dead time, Lock level, the OSSI, + the OSSR State and the AOE(automatic output enable) + (++) Enable/Disable the TIM peripheral Main Outputs + (++) Select the Commutation event + (++) Set/Reset the Capture Compare Preload Control bit + + (#) TIM interrupts, DMA and flags management. + (++) Enable/Disable interrupt sources. + (++) Get flags status. + (++) Clear flags/ Pending bits. + (++) Enable/Disable DMA requests. + (++) Configure DMA burst mode. + (++) Select CaptureCompare DMA request. + + (#) TIM clocks management: this group includes all needed functions + to configure the clock controller unit: + (++) Select internal/External clock. + (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx. + + (#) TIM synchronization management: this group includes all needed. + functions to configure the Synchronization unit: + (++) Select Input Trigger. + (++) Select Output Trigger. + (++) Select Master Slave Mode. + (++) ETR Configuration when used as external trigger. + + (#) TIM specific interface management, this group includes all + needed functions to use the specific TIM interface: + (++) Encoder Interface Configuration. + (++) Select Hall Sensor. + + (#) TIM specific remapping management includes the Remapping + configuration of specific timers + +@endverbatim + * + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_tim.h" +#include "stm32f0xx_rcc.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup TIM + * @brief TIM driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* ---------------------- TIM registers bit mask ------------------------ */ +#define SMCR_ETR_MASK ((uint16_t)0x00FF) +#define CCMR_OFFSET ((uint16_t)0x0018) +#define CCER_CCE_SET ((uint16_t)0x0001) +#define CCER_CCNE_SET ((uint16_t)0x0004) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup TIM_Private_Functions + * @{ + */ + +/** @defgroup TIM_Group1 TimeBase management functions + * @brief TimeBase management functions + * +@verbatim + =============================================================================== + ##### TimeBase management functions ##### + =============================================================================== + + *** TIM Driver: how to use it in Timing(Time base) Mode *** + =============================================================================== + [..] To use the Timer in Timing(Time base) mode, the following steps are + mandatory: + (#) Enable TIM clock using + RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function. + (#) Fill the TIM_TimeBaseInitStruct with the desired parameters. + (#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure + the Time Base unit with the corresponding configuration. + (#) Enable the NVIC if you need to generate the update interrupt. + (#) Enable the corresponding interrupt using the function + TIM_ITConfig(TIMx, TIM_IT_Update). + (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. + [..] + (@) All other functions can be used seperatly to modify, if needed, + a specific feature of the Timer. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the TIMx peripheral registers to their default reset values. + * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM peripheral. + * @retval None + * + */ +void TIM_DeInit(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + if (TIMx == TIM1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); + } + else if (TIMx == TIM2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); + } + else if (TIMx == TIM3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); + } + else if (TIMx == TIM6) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); + } + else if (TIMx == TIM14) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); + } + else if (TIMx == TIM15) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE); + } + else if (TIMx == TIM16) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE); + } + else + { + if (TIMx == TIM17) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE); + } + } + +} + +/** + * @brief Initializes the TIMx Time Base Unit peripheral according to + * the specified parameters in the TIM_TimeBaseInitStruct. + * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM + * peripheral. + * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef + * structure that contains the configuration information for + * the specified TIM peripheral. + * @retval None + */ +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + uint16_t tmpcr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); + assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); + + tmpcr1 = TIMx->CR1; + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3)) + { + /* Select the Counter Mode */ + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; + } + + if(TIMx != TIM6) + { + /* Set the clock division */ + tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD)); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; + } + + TIMx->CR1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; + + /* Set the Prescaler value */ + TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; + + if ((TIMx == TIM1) || (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; + } + + /* Generate an update event to reload the Prescaler and the Repetition counter + values immediately */ + TIMx->EGR = TIM_PSCReloadMode_Immediate; +} + +/** + * @brief Fills each TIM_TimeBaseInitStruct member with its default value. + * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef + * structure which will be initialized. + * @retval None + */ +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + /* Set the default configuration */ + TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF; + TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; + TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; +} + +/** + * @brief Configures the TIMx Prescaler. + * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM peripheral. + * @param Prescaler: specifies the Prescaler Register value + * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode + * This parameter can be one of the following values: + * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. + * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly. + * @retval None + */ +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); + + /* Set the Prescaler value */ + TIMx->PSC = Prescaler; + /* Set or reset the UG Bit */ + TIMx->EGR = TIM_PSCReloadMode; +} + +/** + * @brief Specifies the TIMx Counter Mode to be used. + * @param TIMx: where x can be 1, 2, or 3 to select the TIM peripheral. + * @param TIM_CounterMode: specifies the Counter Mode to be used + * This parameter can be one of the following values: + * @arg TIM_CounterMode_Up: TIM Up Counting Mode + * @arg TIM_CounterMode_Down: TIM Down Counting Mode + * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 + * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 + * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 + * @retval None + */ +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) +{ + uint16_t tmpcr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); + + tmpcr1 = TIMx->CR1; + /* Reset the CMS and DIR Bits */ + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); + /* Set the Counter Mode */ + tmpcr1 |= TIM_CounterMode; + /* Write to TIMx CR1 register */ + TIMx->CR1 = tmpcr1; +} + +/** + * @brief Sets the TIMx Counter Register value + * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM + * peripheral. + * @param Counter: specifies the Counter register new value. + * @retval None + */ +void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Set the Counter Register value */ + TIMx->CNT = Counter; +} + +/** + * @brief Sets the TIMx Autoreload Register value + * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM peripheral. + * @param Autoreload: specifies the Autoreload register new value. + * @retval None + */ +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Set the Autoreload Register value */ + TIMx->ARR = Autoreload; +} + +/** + * @brief Gets the TIMx Counter value. + * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM + * peripheral. + * @retval Counter Register value. + */ +uint32_t TIM_GetCounter(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Get the Counter Register value */ + return TIMx->CNT; +} + +/** + * @brief Gets the TIMx Prescaler value. + * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM + * peripheral. + * @retval Prescaler Register value. + */ +uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Get the Prescaler Register value */ + return TIMx->PSC; +} + +/** + * @brief Enables or Disables the TIMx Update event. + * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM + * peripheral. + * @param NewState: new state of the TIMx UDIS bit + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the Update Disable Bit */ + TIMx->CR1 |= TIM_CR1_UDIS; + } + else + { + /* Reset the Update Disable Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS); + } +} + +/** + * @brief Configures the TIMx Update Request Interrupt source. + * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM + * peripheral. + * @param TIM_UpdateSource: specifies the Update source. + * This parameter can be one of the following values: + * @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow + or the setting of UG bit, or an update generation + through the slave mode controller. + * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow. + * @retval None + */ +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); + + if (TIM_UpdateSource != TIM_UpdateSource_Global) + { + /* Set the URS Bit */ + TIMx->CR1 |= TIM_CR1_URS; + } + else + { + /* Reset the URS Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS); + } +} + +/** + * @brief Enables or disables TIMx peripheral Preload register on ARR. + * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM + * peripheral. + * @param NewState: new state of the TIMx peripheral Preload register + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the ARR Preload Bit */ + TIMx->CR1 |= TIM_CR1_ARPE; + } + else + { + /* Reset the ARR Preload Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE); + } +} + +/** + * @brief Selects the TIMx's One Pulse Mode. + * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM + * peripheral. + * @param TIM_OPMode: specifies the OPM Mode to be used. + * This parameter can be one of the following values: + * @arg TIM_OPMode_Single + * @arg TIM_OPMode_Repetitive + * @retval None + */ +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); + + /* Reset the OPM Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM); + /* Configure the OPM Mode */ + TIMx->CR1 |= TIM_OPMode; +} + +/** + * @brief Sets the TIMx Clock Division value. + * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral. + * @param TIM_CKD: specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CKD_DIV1: TDTS = Tck_tim + * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim + * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim + * @retval None + */ +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_CKD_DIV(TIM_CKD)); + + /* Reset the CKD Bits */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD); + /* Set the CKD value */ + TIMx->CR1 |= TIM_CKD; +} + +/** + * @brief Enables or disables the specified TIM peripheral. + * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17to select the TIMx + * peripheral. + * @param NewState: new state of the TIMx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TIM Counter */ + TIMx->CR1 |= TIM_CR1_CEN; + } + else + { + /* Disable the TIM Counter */ + TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN)); + } +} + +/** + * @} + */ + +/** @defgroup TIM_Group2 Advanced-control timers (TIM1) specific features + * @brief Advanced-control timers (TIM1) specific features + * +@verbatim + =============================================================================== + ##### Advanced-control timers (TIM1) specific features ##### + =============================================================================== + + =================================================================== + *** TIM Driver: how to use the Break feature *** + =================================================================== + [..] After configuring the Timer channel(s) in the appropriate Output Compare mode: + + (#) Fill the TIM_BDTRInitStruct with the desired parameters for the Timer + Break Polarity, dead time, Lock level, the OSSI/OSSR State and the + AOE(automatic output enable). + + (#) Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer + + (#) Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE) + + (#) Once the break even occurs, the Timer's output signals are put in reset + state or in a known state (according to the configuration made in + TIM_BDTRConfig() function). + +@endverbatim + * @{ + */ +/** + * @brief Configures the: Break feature, dead time, Lock level, the OSSI, + * the OSSR State and the AOE(automatic output enable). + * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIM + * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @retval None + */ +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); + assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); + assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); + assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); + assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); + /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | + TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | + TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | + TIM_BDTRInitStruct->TIM_AutomaticOutput; +} + +/** + * @brief Fills each TIM_BDTRInitStruct member with its default value. + * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which + * will be initialized. + * @retval None + */ +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) +{ + /* Set the default configuration */ + TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; + TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; + TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; + TIM_BDTRInitStruct->TIM_DeadTime = 0x00; + TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; + TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; + TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; +} + +/** + * @brief Enables or disables the TIM peripheral Main Outputs. + * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIMx peripheral. + * @param NewState: new state of the TIM peripheral Main Outputs. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the TIM Main Output */ + TIMx->BDTR |= TIM_BDTR_MOE; + } + else + { + /* Disable the TIM Main Output */ + TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE)); + } +} + +/** + * @} + */ + +/** @defgroup TIM_Group3 Output Compare management functions + * @brief Output Compare management functions + * +@verbatim + =============================================================================== + ##### Output Compare management functions ##### + =============================================================================== + *** TIM Driver: how to use it in Output Compare Mode *** + =============================================================================== + [..] To use the Timer in Output Compare mode, the following steps are mandatory: + (#) Enable TIM clock using + RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function. + (#) Configure the TIM pins by configuring the corresponding GPIO pins + (#) Configure the Time base unit as described in the first part of this + driver, if needed, else the Timer will run with the default + configuration: + (++) Autoreload value = 0xFFFF. + (++) Prescaler value = 0x0000. + (++) Counter mode = Up counting. + (++) Clock Division = TIM_CKD_DIV1. + (#) Fill the TIM_OCInitStruct with the desired parameters including: + (++) The TIM Output Compare mode: TIM_OCMode. + (++) TIM Output State: TIM_OutputState. + (++) TIM Pulse value: TIM_Pulse. + (++) TIM Output Compare Polarity : TIM_OCPolarity. + (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired + channel with the corresponding configuration. + (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. + [..] + (@) All other functions can be used separately to modify, if needed, + a specific feature of the Timer. + (@) In case of PWM mode, this function is mandatory: + TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE). + (@) If the corresponding interrupt or DMA request are needed, the user should: + (#@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests). + (#@) Enable the corresponding interrupt (or DMA request) using the function + TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)). + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TIMx Channel1 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM + * peripheral. + * @retval None + */ +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E); + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S)); + + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P)); + /* Set the Output Compare Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; + + /* Set the Output State */ + tmpccer |= TIM_OCInitStruct->TIM_OutputState; + + if((TIMx == TIM1) || (TIMx == TIM15) || (TIMx == TIM16) || (TIMx == TIM17)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP)); + /* Set the Output N Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; + + /* Reset the Output N State */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE)); + /* Set the Output N State */ + tmpccer |= TIM_OCInitStruct->TIM_OutputNState; + + /* Reset the Ouput Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N)); + + /* Set the Output Idle state */ + tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel2 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM + * peripheral. + * @retval None + */ +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E)); + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); + + if(TIMx == TIM1) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP)); + /* Set the Output N Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); + + /* Reset the Output N State */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE)); + /* Set the Output N State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); + + /* Reset the Ouput Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N)); + + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); + /* Set the Output N Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel3 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM + * peripheral. + * @retval None + */ +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E)); + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S)); + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); + + if(TIMx == TIM1) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP)); + /* Set the Output N Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); + /* Reset the Output N State */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE)); + + /* Set the Output N State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); + /* Reset the Ouput Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N)); + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); + /* Set the Output N Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel4 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM + * peripheral. + * @retval None + */ +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 2: Reset the CC4E Bit */ + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E)); + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); + + if(TIMx == TIM1) + { + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + /* Reset the Ouput Compare IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4)); + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Fills each TIM_OCInitStruct member with its default value. + * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will + * be initialized. + * @retval None + */ +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + /* Set the default configuration */ + TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; + TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; + TIM_OCInitStruct->TIM_Pulse = 0x0000000; + TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; + TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; +} + +/** + * @brief Selects the TIM Output Compare Mode. + * @note This function disables the selected channel before changing the Output + * Compare Mode. + * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions. + * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @arg TIM_Channel_4: TIM Channel 4 + * @param TIM_OCMode: specifies the TIM Output Compare Mode. + * This parameter can be one of the following values: + * @arg TIM_OCMode_Timing + * @arg TIM_OCMode_Active + * @arg TIM_OCMode_Toggle + * @arg TIM_OCMode_PWM1 + * @arg TIM_OCMode_PWM2 + * @arg TIM_ForcedAction_Active + * @arg TIM_ForcedAction_InActive + * @retval None + */ +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) +{ + uint32_t tmp = 0; + uint16_t tmp1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OCM(TIM_OCMode)); + + tmp = (uint32_t) TIMx; + tmp += CCMR_OFFSET; + + tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel; + + /* Disable the Channel: Reset the CCxE Bit */ + TIMx->CCER &= (uint16_t) ~tmp1; + + if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) + { + tmp += (TIM_Channel>>1); + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M); + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp |= TIM_OCMode; + } + else + { + tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1; + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M); + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8); + } +} + +/** + * @brief Sets the TIMx Capture Compare1 Register value + * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. + * @param Compare1: specifies the Capture Compare1 register new value. + * @retval None + */ +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + + /* Set the Capture Compare1 Register value */ + TIMx->CCR1 = Compare1; +} + +/** + * @brief Sets the TIMx Capture Compare2 Register value + * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. + * @param Compare2: specifies the Capture Compare2 register new value. + * @retval None + */ +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + + /* Set the Capture Compare2 Register value */ + TIMx->CCR2 = Compare2; +} + +/** + * @brief Sets the TIMx Capture Compare3 Register value + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @param Compare3: specifies the Capture Compare3 register new value. + * @retval None + */ +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + + /* Set the Capture Compare3 Register value */ + TIMx->CCR3 = Compare3; +} + +/** + * @brief Sets the TIMx Capture Compare4 Register value + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @param Compare4: specifies the Capture Compare4 register new value. + * @retval None + */ +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + + /* Set the Capture Compare4 Register value */ + TIMx->CCR4 = Compare4; +} + +/** + * @brief Forces the TIMx output 1 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC1REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. + * @retval None + */ +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1M Bits */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M); + /* Configure The Forced output Mode */ + tmpccmr1 |= TIM_ForcedAction; + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 2 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM + * peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC2REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. + * @retval None + */ +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2M Bits */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M); + /* Configure The Forced output Mode */ + tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 3 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC3REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. + * @retval None + */ +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC1M Bits */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M); + /* Configure The Forced output Mode */ + tmpccmr2 |= TIM_ForcedAction; + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Forces the TIMx output 4 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC4REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. + * @retval None + */ +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC2M Bits */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M); + /* Configure The Forced output Mode */ + tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. + * @param TIMx: where x can be 1, 2, 3 or 15 + * to select the TIMx peripheral + * @param NewState: new state of the Capture Compare Preload Control bit + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the CCPC Bit */ + TIMx->CR2 |= TIM_CR2_CCPC; + } + else + { + /* Reset the CCPC Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC); + } +} + + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR1. + * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1PE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= TIM_OCPreload; + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR2. + * @param TIMx: where x can be 1, 2, 3 and 15 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2PE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR3. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC3PE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= TIM_OCPreload; + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR4. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC4PE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 1 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1FE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= TIM_OCFast; + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 2 Fast feature. + * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2FE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 3 Fast feature. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC3FE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= TIM_OCFast; + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 4 Fast feature. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC4FE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF1 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1CE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= TIM_OCClear; + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF2 signal on an external event + * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2CE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF3 signal on an external event + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC3CE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= TIM_OCClear; + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF4 signal on an external event + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC4CE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx channel 1 polarity. + * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC1 Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC1P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P); + tmpccer |= TIM_OCPolarity; + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 1N polarity. + * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC1N Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC1NP Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP); + tmpccer |= TIM_OCNPolarity; + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 2 polarity. + * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC2 Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC2P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 4); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 2N polarity. + * @param TIMx: where x can be 1 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC2N Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC2NP Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 3 polarity. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC3 Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC3P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 8); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 3N polarity. + * @param TIMx: where x can be 1 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC3N Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC3NP Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + + +/** + * @brief Configures the TIMx channel 4 polarity. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC4 Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC4P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 12); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Selects the OCReference Clear source. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @param TIM_OCReferenceClear: specifies the OCReference Clear source. + * This parameter can be one of the following values: + * @arg TIM_OCReferenceClear_ETRF: The internal OCreference clear input is connected to ETRF. + * @arg TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input. + * @retval None + */ +void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(TIM_OCREFERENCECECLEAR_SOURCE(TIM_OCReferenceClear)); + + /* Set the TIM_OCReferenceClear source */ + TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_OCCS); + TIMx->SMCR |= TIM_OCReferenceClear; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @arg TIM_Channel_4: TIM Channel 4 + * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. + * @retval None + */ +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_CCX(TIM_CCx)); + + tmp = CCER_CCE_SET << TIM_Channel; + + /* Reset the CCxE Bit */ + TIMx->CCER &= (uint16_t)~ tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parmeter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. + * @retval None + */ +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_CCXN(TIM_CCxN)); + + tmp = CCER_CCNE_SET << TIM_Channel; + + /* Reset the CCxNE Bit */ + TIMx->CCER &= (uint16_t) ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); +} + +/** + * @brief Selects the TIM peripheral Commutation event. + * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIMx peripheral + * @param NewState: new state of the Commutation event. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the COM Bit */ + TIMx->CR2 |= TIM_CR2_CCUS; + } + else + { + /* Reset the COM Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS); + } +} + +/** + * @} + */ + +/** @defgroup TIM_Group4 Input Capture management functions + * @brief Input Capture management functions + * +@verbatim + =============================================================================== + ##### Input Capture management functions ##### + =============================================================================== + + *** TIM Driver: how to use it in Input Capture Mode *** + =============================================================================== + [..] To use the Timer in Input Capture mode, the following steps are mandatory: + (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) + function. + (#) Configure the TIM pins by configuring the corresponding GPIO pins. + (#) Configure the Time base unit as described in the first part of this + driver, if needed, else the Timer will run with the default configuration: + (++) Autoreload value = 0xFFFF. + (++) Prescaler value = 0x0000. + (++) Counter mode = Up counting. + (++) Clock Division = TIM_CKD_DIV1. + (#) Fill the TIM_ICInitStruct with the desired parameters including: + (++) TIM Channel: TIM_Channel. + (++) TIM Input Capture polarity: TIM_ICPolarity. + (++) TIM Input Capture selection: TIM_ICSelection. + (++) TIM Input Capture Prescaler: TIM_ICPrescaler. + (++) TIM Input CApture filter value: TIM_ICFilter. + (#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired + channel with the corresponding configuration and to measure only + frequency or duty cycle of the input signal,or, Call + TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired + channels with the corresponding configuration and to measure the + frequency and the duty cycle of the input signal. + (#) Enable the NVIC or the DMA to read the measured frequency. + (#) Enable the corresponding interrupt (or DMA request) to read + the Captured value, using the function TIM_ITConfig(TIMx, TIM_IT_CCx) + (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)). + (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. + (#) Use TIM_GetCapturex(TIMx); to read the captured value. + [..] + (@) All other functions can be used separately to modify, if needed, + a specific feature of the Timer. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct. + * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure + * that contains the configuration information for the specified TIM + * peripheral. + * @retval None + */ +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel)); + assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); + assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); + + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) + { + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* TI2 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) + { + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* TI3 Configuration */ + TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* TI4 Configuration */ + TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/** + * @brief Fills each TIM_ICInitStruct member with its default value. + * @param TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will + * be initialized. + * @retval None + */ +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Set the default configuration */ + TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; + TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStruct->TIM_ICFilter = 0x00; +} + +/** + * @brief Configures the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct to measure an external PWM signal. + * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure + * that contains the configuration information for the specified TIM + * peripheral. + * @retval None + */ +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + uint16_t icoppositepolarity = TIM_ICPolarity_Rising; + uint16_t icoppositeselection = TIM_ICSelection_DirectTI; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* Select the Opposite Input Polarity */ + if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) + { + icoppositepolarity = TIM_ICPolarity_Falling; + } + else + { + icoppositepolarity = TIM_ICPolarity_Rising; + } + /* Select the Opposite Input */ + if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) + { + icoppositeselection = TIM_ICSelection_IndirectTI; + } + else + { + icoppositeselection = TIM_ICSelection_DirectTI; + } + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + /* TI2 Configuration */ + TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + /* TI2 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + /* TI1 Configuration */ + TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/** + * @brief Gets the TIMx Input Capture 1 value. + * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. + * @retval Capture Compare 1 Register value. + */ +uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + + /* Get the Capture 1 Register value */ + return TIMx->CCR1; +} + +/** + * @brief Gets the TIMx Input Capture 2 value. + * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. + * @retval Capture Compare 2 Register value. + */ +uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + + /* Get the Capture 2 Register value */ + return TIMx->CCR2; +} + +/** + * @brief Gets the TIMx Input Capture 3 value. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @retval Capture Compare 3 Register value. + */ +uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + + /* Get the Capture 3 Register value */ + return TIMx->CCR3; +} + +/** + * @brief Gets the TIMx Input Capture 4 value. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @retval Capture Compare 4 Register value. + */ +uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + + /* Get the Capture 4 Register value */ + return TIMx->CCR4; +} + +/** + * @brief Sets the TIMx Input Capture 1 prescaler. + * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC1PSC Bits */ + TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC); + /* Set the IC1PSC value */ + TIMx->CCMR1 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 2 prescaler. + * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC2PSC Bits */ + TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC); + /* Set the IC2PSC value */ + TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); +} + +/** + * @brief Sets the TIMx Input Capture 3 prescaler. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC3PSC Bits */ + TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC); + /* Set the IC3PSC value */ + TIMx->CCMR2 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 4 prescaler. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC4PSC Bits */ + TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC); + /* Set the IC4PSC value */ + TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); +} + +/** + * @} + */ + +/** @defgroup TIM_Group5 Interrupts DMA and flags management functions + * @brief Interrupts, DMA and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts, DMA and flags management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified TIM interrupts. + * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 or 17 to select the TIMx peripheral. + * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg TIM_IT_Update: TIM update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * @note + * - TIM6 can only generate an update interrupt. + * - TIM15 can have only TIM_IT_Update, TIM_IT_CC1, + * TIM_IT_CC2 or TIM_IT_Trigger. + * - TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. + * - TIM_IT_Break is used only with TIM1 and TIM15. + * - TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17. + * @param NewState: new state of the TIM interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_IT(TIM_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Interrupt sources */ + TIMx->DIER |= TIM_IT; + } + else + { + /* Disable the Interrupt sources */ + TIMx->DIER &= (uint16_t)~TIM_IT; + } +} + +/** + * @brief Configures the TIMx event to be generate by software. + * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 or 17 to select the + * TIM peripheral. + * @param TIM_EventSource: specifies the event source. + * This parameter can be one or more of the following values: + * @arg TIM_EventSource_Update: Timer update Event source + * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EventSource_COM: Timer COM event source + * @arg TIM_EventSource_Trigger: Timer Trigger Event source + * @arg TIM_EventSource_Break: Timer Break event source + * @note + * - TIM6 can only generate an update event. + * - TIM9 can only generate an update event, Capture Compare 1 event, + * Capture Compare 2 event and TIM_EventSource_Trigger. + * - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1. + * @retval None + */ +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); + /* Set the event sources */ + TIMx->EGR = TIM_EventSource; +} + +/** + * @brief Checks whether the specified TIM flag is set or not. + * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 or 17 to select the TIM peripheral. + * @param TIM_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_Update: TIM update Flag + * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag + * @arg TIM_FLAG_COM: TIM Commutation Flag + * @arg TIM_FLAG_Trigger: TIM Trigger Flag + * @arg TIM_FLAG_Break: TIM Break Flag + * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag + * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag + * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag + * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag + * @note + * - TIM6 can have only one update flag. + * - TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, TIM_FLAG_CC2 or + * TIM_FLAG_Trigger. + * - TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. + * - TIM_FLAG_Break is used only with TIM1 and TIM15. + * - TIM_FLAG_COM is used only with TIM1 TIM15, TIM16 and TIM17. + * @retval The new state of TIM_FLAG (SET or RESET). + */ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); + + if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's pending flags. + * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 or 17 to select the TIM peripheral. + * @param TIM_FLAG: specifies the flag bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_FLAG_Update: TIM update Flag + * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag + * @arg TIM_FLAG_COM: TIM Commutation Flag + * @arg TIM_FLAG_Trigger: TIM Trigger Flag + * @arg TIM_FLAG_Break: TIM Break Flag + * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag + * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag + * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag + * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag + * @note + * - TIM6 can have only one update flag. + * - TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,TIM_FLAG_CC2 or + * TIM_FLAG_Trigger. + * - TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. + * - TIM_FLAG_Break is used only with TIM1 and TIM15. + * - TIM_FLAG_COM is used only with TIM1, TIM15, TIM16 and TIM17. + * @retval None + */ +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG)); + + /* Clear the flags */ + TIMx->SR = (uint16_t)~TIM_FLAG; +} + +/** + * @brief Checks whether the TIM interrupt has occurred or not. + * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 or 17 to select the TIM peripheral. + * @param TIM_IT: specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_IT_Update: TIM update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * @note + * - TIM6 can generate only an update interrupt. + * - TIM15 can have only TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. + * - TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. + * - TIM_IT_Break is used only with TIM1 and TIM15. + * - TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17. + * @retval The new state of the TIM_IT(SET or RESET). + */ +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itstatus = 0x0, itenable = 0x0; + + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_GET_IT(TIM_IT)); + + itstatus = TIMx->SR & TIM_IT; + + itenable = TIMx->DIER & TIM_IT; + if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's interrupt pending bits. + * @param TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 or 17 to select the TIM peripheral. + * @param TIM_IT: specifies the pending bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_IT_Update: TIM1 update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * @note + * - TIM6 can generate only an update interrupt. + * - TIM15 can have only TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. + * - TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. + * - TIM_IT_Break is used only with TIM1 and TIM15. + * - TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17. + * @retval None + */ +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_IT(TIM_IT)); + + /* Clear the IT pending Bit */ + TIMx->SR = (uint16_t)~TIM_IT; +} + +/** + * @brief Configures the TIMx's DMA interface. + * @param TIMx: where x can be 1, 2, 3, 15, 16 or 17 to select the TIM peripheral. + * @param TIM_DMABase: DMA Base address. + * This parameter can be one of the following values: + * @arg TIM_DMABase_CR1, TIM_DMABase_CR2, TIM_DMABase_SMCR, + * TIM_DMABase_DIER, TIM_DMABase_SR, TIM_DMABase_EGR, + * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER, + * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR, + * TIM_DMABase_CCR1, TIM_DMABase_CCR2, TIM_DMABase_CCR3, + * TIM_DMABase_CCR4, TIM_DMABase_DCR, TIM_DMABase_OR. + * @param TIM_DMABurstLength: DMA Burst length. + * This parameter can be one value between: + * TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. + * @retval None + */ +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); + assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); + /* Set the DMA Base and the DMA Burst Length */ + TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; +} + +/** + * @brief Enables or disables the TIMx's DMA Requests. + * @param TIMx: where x can be 1, 2, 3, 6, 15, 16 or 17 to select the TIM peripheral. + * @param TIM_DMASource: specifies the DMA Request sources. + * This parameter can be any combination of the following values: + * @arg TIM_DMA_Update: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_Trigger: TIM Trigger DMA source + * @param NewState: new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST10_PERIPH(TIMx)); + assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA sources */ + TIMx->DIER |= TIM_DMASource; + } + else + { + /* Disable the DMA sources */ + TIMx->DIER &= (uint16_t)~TIM_DMASource; + } +} + +/** + * @brief Selects the TIMx peripheral Capture Compare DMA source. + * @param TIMx: where x can be 1, 2, 3, 15, 16 or 17 to select the TIM peripheral. + * @param NewState: new state of the Capture Compare DMA source + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the CCDS Bit */ + TIMx->CR2 |= TIM_CR2_CCDS; + } + else + { + /* Reset the CCDS Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS); + } +} + +/** + * @} + */ + +/** @defgroup TIM_Group6 Clocks management functions + * @brief Clocks management functions + * +@verbatim + =============================================================================== + ##### Clocks management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the TIMx internal Clock + * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. + * @retval None + */ +void TIM_InternalClockConfig(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* Disable slave mode to clock the prescaler directly with the internal clock */ + TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); +} + +/** + * @brief Configures the TIMx Internal Trigger as External Clock + * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. + * @param TIM_ITRSource: Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @retval None + */ +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); + /* Select the Internal Trigger */ + TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/** + * @brief Configures the TIMx Trigger as External Clock + * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. + * @param TIM_TIxExternalCLKSource: Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector + * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 + * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 + * @param TIM_ICPolarity: specifies the TIx Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param ICFilter : specifies the filter value. + * This parameter must be a value between 0x0 and 0xF. + * @retval None + */ +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); + assert_param(IS_TIM_IC_FILTER(ICFilter)); + + /* Configure the Timer Input Clock Source */ + if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + /* Select the Trigger source */ + TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/** + * @brief Configures the External clock Mode1 + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + + /* Configure the ETR Clock source */ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the SMS Bits */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); + /* Select the External clock mode1 */ + tmpsmcr |= TIM_SlaveMode_External1; + /* Select the Trigger selection : ETRF */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); + tmpsmcr |= TIM_TS_ETRF; + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Configures the External clock Mode2 + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + + /* Configure the ETR Clock source */ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + /* Enable the External clock mode2 */ + TIMx->SMCR |= TIM_SMCR_ECE; +} + +/** + * @} + */ + +/** @defgroup TIM_Group7 Synchronization management functions + * @brief Synchronization management functions + * +@verbatim + =============================================================================== + ##### Synchronization management functions ##### + =============================================================================== + *** TIM Driver: how to use it in synchronization Mode *** + =============================================================================== + [..] Case of two/several Timers + (#) Configure the Master Timers using the following functions: + (++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, + uint16_t TIM_TRGOSource). + (++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, + uint16_t TIM_MasterSlaveMode); + (#) Configure the Slave Timers using the following functions: + (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, + uint16_t TIM_InputTriggerSource); + (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); + [..] Case of Timers and external trigger(ETR pin) + (#) Configure the Etrenal trigger using this function: + (++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); + (#) Configure the Slave Timers using the following functions: + (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, + uint16_t TIM_InputTriggerSource); + (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); + +@endverbatim + * @{ + */ +/** + * @brief Selects the Input Trigger source + * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. + * @param TIM_InputTriggerSource: The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) +{ + uint16_t tmpsmcr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); + /* Set the Input Trigger source */ + tmpsmcr |= TIM_InputTriggerSource; + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Selects the TIMx Trigger Output Mode. + * @param TIMx: where x can be 1, 2, 3, 6, or 15 to select the TIM peripheral. + * @param TIM_TRGOSource: specifies the Trigger Output source. + * This paramter can be one of the following values: + * + * For all TIMx + * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO). + * + * For all TIMx except TIM6 + * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag + * is to be set, as soon as a capture or compare match occurs (TRGO). + * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO). + * + * @retval None + */ +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST9_PERIPH(TIMx)); + assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); + + /* Reset the MMS Bits */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS); + /* Select the TRGO source */ + TIMx->CR2 |= TIM_TRGOSource; +} + +/** + * @brief Selects the TIMx Slave Mode. + * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. + * @param TIM_SlaveMode: specifies the Timer Slave Mode. + * This paramter can be one of the following values: + * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes + * the counter and triggers an update of the registers. + * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high. + * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI. + * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter. + * @retval None + */ +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); + + /* Reset the SMS Bits */ + TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS); + /* Select the Slave Mode */ + TIMx->SMCR |= TIM_SlaveMode; +} + +/** + * @brief Sets or Resets the TIMx Master/Slave Mode. + * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. + * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. + * This paramter can be one of the following values: + * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer + * and its slaves (through TRGO). + * @arg TIM_MasterSlaveMode_Disable: No action + * @retval None + */ +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); + + /* Reset the MSM Bit */ + TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM); + + /* Set or Reset the MSM Bit */ + TIMx->SMCR |= TIM_MasterSlaveMode; +} + +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + + tmpsmcr = TIMx->SMCR; + /* Reset the ETR Bits */ + tmpsmcr &= SMCR_ETR_MASK; + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @} + */ + +/** @defgroup TIM_Group8 Specific interface management functions + * @brief Specific interface management functions + * +@verbatim + =============================================================================== + ##### Specific interface management functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configures the TIMx Encoder Interface. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. + * This parameter can be one of the following values: + * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. + * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. + * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending + * on the level of the other input. + * @param TIM_IC1Polarity: specifies the IC1 Polarity + * This parmeter can be one of the following values: + * @arg TIM_ICPolarity_Falling: IC Falling edge. + * @arg TIM_ICPolarity_Rising: IC Rising edge. + * @param TIM_IC2Polarity: specifies the IC2 Polarity + * This parmeter can be one of the following values: + * @arg TIM_ICPolarity_Falling: IC Falling edge. + * @arg TIM_ICPolarity_Rising: IC Rising edge. + * @retval None + */ +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) +{ + uint16_t tmpsmcr = 0; + uint16_t tmpccmr1 = 0; + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); + assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); + assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Set the encoder Mode */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); + tmpsmcr |= TIM_EncoderMode; + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S))); + tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; + /* Set the TI1 and the TI2 Polarities */ + //tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P))); + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP)) & (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP)); + tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Enables or disables the TIMx's Hall sensor interface. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @param NewState: new state of the TIMx Hall sensor interface. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the TI1S Bit */ + TIMx->CR2 |= TIM_CR2_TI1S; + } + else + { + /* Reset the TI1S Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S); + } +} + +/** + * @} + */ + +/** @defgroup TIM_Group9 Specific remapping management function + * @brief Specific remapping management function + * +@verbatim + =============================================================================== + ##### Specific remapping management function ##### + =============================================================================== + +@endverbatim + * @{ + */ +/** + * @brief Configures the TIM14 Remapping input Capabilities. + * @param TIMx: where x can be 14 to select the TIM peripheral. + * @param TIM_Remap: specifies the TIM input reampping source. + * This parameter can be one of the following values: + * @arg TIM14_GPIO : TIM14 Channel 1 is connected to GPIO. + * @arg TIM14_RTC_CLK : TIM14 Channel 1 is connected to RTC input clock. + * RTC input clock can be LSE, LSI or HSE/div128. + * @arg TIM14_HSE_DIV32 : TIM14 Channel 1 is connected to HSE/32 clock. + * @arg TIM14_MCO : TIM14 Channel 1 is connected to MCO clock. + * MCO clock can be HSI14, SYSCLK, HSI, HSE or PLL/2. + * @retval : None + */ +void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST11_PERIPH(TIMx)); + assert_param(IS_TIM_REMAP(TIM_Remap)); + + /* Set the Timer remapping configuration */ + TIMx->OR = TIM_Remap; +} + +/** + * @} + */ + +/** + * @brief Configure the TI1 as Input. + * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0; + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E); + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + /* Select the Input and set the filter */ + tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F))); + tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E); + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 4); + /* Select the Input and set the filter */ + tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F))); + tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); + tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E); + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 8); + /* Select the Input and set the filter */ + tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E); + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 12); + /* Select the Input and set the filter */ + tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); + tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P | TIM_CCER_CC4NP)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_usart.c b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_usart.c new file mode 100644 index 0000000..749b270 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_usart.c @@ -0,0 +1,2014 @@ +/** + ****************************************************************************** + * @file stm32f0xx_usart.c + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Universal synchronous asynchronous receiver + * transmitter (USART): + * + Initialization and Configuration + * + STOP Mode + * + AutoBaudRate + * + Data transfers + * + Multi-Processor Communication + * + LIN mode + * + Half-duplex mode + * + Smartcard mode + * + IrDA mode + * + RS485 mode + * + DMA transfers management + * + Interrupts and flags management + * + * @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE) + function for USART1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE) + function for USART2 and USART3. + (#) According to the USART mode, enable the GPIO clocks using + RCC_AHBPeriphClockCmd() function. (The I/O can be TX, RX, CTS, + or and SCLK). + (#) Peripheral's alternate function: + (++) Connect the pin to the desired peripherals' Alternate + Function (AF) using GPIO_PinAFConfig() function. + (++) Configure the desired pin in alternate function by: + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF. + (++) Select the type, pull-up/pull-down and output speed via + GPIO_PuPd, GPIO_OType and GPIO_Speed members. + (++) Call GPIO_Init() function. + (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware + flow control and Mode(Receiver/Transmitter) using the SPI_Init() + function. + (#) For synchronous mode, enable the clock and program the polarity, + phase and last bit using the USART_ClockInit() function. + (#) Enable the NVIC and the corresponding interrupt using the function + USART_ITConfig() if you need to use interrupt mode. + (#) When using the DMA mode: + (++) Configure the DMA using DMA_Init() function. + (++) Active the needed channel Request using USART_DMACmd() function. + (#) Enable the USART using the USART_Cmd() function. + (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode. + [..] + Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections + for more details. + +@endverbatim + + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_usart.h" +#include "stm32f0xx_rcc.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup USART + * @brief USART driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/*!< USART CR1 register clear Mask ((~(uint32_t)0xFFFFE6F3)) */ +#define CR1_CLEAR_MASK ((uint32_t)(USART_CR1_M | USART_CR1_PCE | \ + USART_CR1_PS | USART_CR1_TE | \ + USART_CR1_RE)) + +/*!< USART CR2 register clock bits clear Mask ((~(uint32_t)0xFFFFF0FF)) */ +#define CR2_CLOCK_CLEAR_MASK ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \ + USART_CR2_CPHA | USART_CR2_LBCL)) + +/*!< USART CR3 register clear Mask ((~(uint32_t)0xFFFFFCFF)) */ +#define CR3_CLEAR_MASK ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) + +/*!< USART Interrupts mask */ +#define IT_MASK ((uint32_t)0x000000FF) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup USART_Private_Functions + * @{ + */ + +/** @defgroup USART_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USART + in asynchronous and in synchronous modes. + (+) For the asynchronous mode only these parameters can be configured: + (++) Baud Rate. + (++) Word Length. + (++) Stop Bit. + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + Depending on the frame length defined by the M bit (8-bits or 9-bits), + the possible USART frame formats are as listed in the following table: + + +-------------------------------------------------------------+ + | M bit | PCE bit | USART frame | + |---------------------|---------------------------------------| + | 0 | 0 | | SB | 8 bit data | STB | | + |---------|-----------|---------------------------------------| + | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|-----------|---------------------------------------| + | 1 | 0 | | SB | 9 bit data | STB | | + |---------|-----------|---------------------------------------| + | 1 | 1 | | SB | 8 bit data | PB | STB | | + +-------------------------------------------------------------+ + + (++) Hardware flow control. + (++) Receiver/transmitter modes. + [..] The USART_Init() function follows the USART asynchronous configuration + procedure(details for the procedure are available in reference manual. + (+) For the synchronous mode in addition to the asynchronous mode parameters + these parameters should be also configured: + (++) USART Clock Enabled. + (++) USART polarity. + (++) USART phase. + (++) USART LastBit. + [..] These parameters can be configured using the USART_ClockInit() function. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the USARTx peripheral registers to their default reset values. + * @param USARTx: where x can be 1 or 2 to select the USART peripheral. + * @retval None + */ +void USART_DeInit(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + if (USARTx == USART1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); + } + else + { + if (USARTx == USART2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); + } + } +} + +/** + * @brief Initializes the USARTx peripheral according to the specified + * parameters in the USART_InitStruct . + * @param USARTx: where x can be 1 or 2 to select the USART peripheral. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure + * that contains the configuration information for the specified USART peripheral. + * @retval None + */ +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) +{ + uint32_t tmpreg = 0, apbclock = 0; + uint32_t integerdivider = 0; + uint32_t fractionaldivider = 0; + RCC_ClocksTypeDef RCC_ClocksStatus; + + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); + assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); + assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); + assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); + assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); + assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); + + /* Disable USART */ + USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UE); + +/*---------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = USARTx->CR2; + /* Clear STOP[13:12] bits */ + tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP); + + /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/ + /* Set STOP[13:12] bits according to USART_StopBits value */ + tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; + + /* Write to USART CR2 */ + USARTx->CR2 = tmpreg; + +/*---------------------------- USART CR1 Configuration -----------------------*/ + tmpreg = USARTx->CR1; + /* Clear M, PCE, PS, TE and RE bits */ + tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK); + + /* Configure the USART Word Length, Parity and mode ----------------------- */ + /* Set the M bits according to USART_WordLength value */ + /* Set PCE and PS bits according to USART_Parity value */ + /* Set TE and RE bits according to USART_Mode value */ + tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Mode; + + /* Write to USART CR1 */ + USARTx->CR1 = tmpreg; + +/*---------------------------- USART CR3 Configuration -----------------------*/ + tmpreg = USARTx->CR3; + /* Clear CTSE and RTSE bits */ + tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK); + + /* Configure the USART HFC -------------------------------------------------*/ + /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ + tmpreg |= USART_InitStruct->USART_HardwareFlowControl; + + /* Write to USART CR3 */ + USARTx->CR3 = tmpreg; + +/*---------------------------- USART BRR Configuration -----------------------*/ + /* Configure the USART Baud Rate -------------------------------------------*/ + RCC_GetClocksFreq(&RCC_ClocksStatus); + + if (USARTx == USART1) + { + apbclock = RCC_ClocksStatus.USART1CLK_Frequency; + } + else + { + apbclock = RCC_ClocksStatus.PCLK_Frequency; + } + /* Determine the integer part */ + if ((USARTx->CR1 & USART_CR1_OVER8) != 0) + { + /* Integer part computing in case Oversampling mode is 8 Samples */ + integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); + } + else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ + { + /* Integer part computing in case Oversampling mode is 16 Samples */ + integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); + } + tmpreg = (integerdivider / 100) << 4; + + /* Determine the fractional part */ + fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); + + /* Implement the fractional part in the register */ + if ((USARTx->CR1 & USART_CR1_OVER8) != 0) + { + tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); + } + else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ + { + tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); + } + + /* Write to USART BRR */ + USARTx->BRR = (uint16_t)tmpreg; +} + +/** + * @brief Fills each USART_InitStruct member with its default value. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure + * which will be initialized. + * @retval None + */ +void USART_StructInit(USART_InitTypeDef* USART_InitStruct) +{ + /* USART_InitStruct members default value */ + USART_InitStruct->USART_BaudRate = 9600; + USART_InitStruct->USART_WordLength = USART_WordLength_8b; + USART_InitStruct->USART_StopBits = USART_StopBits_1; + USART_InitStruct->USART_Parity = USART_Parity_No ; + USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; +} + +/** + * @brief Initializes the USARTx peripheral Clock according to the + * specified parameters in the USART_ClockInitStruct. + * @param USARTx: where x can be 1 or 2 to select the USART peripheral. + * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef + * structure that contains the configuration information for the specified + * USART peripheral. + * @retval None + */ +void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock)); + assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL)); + assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA)); + assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit)); +/*---------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = USARTx->CR2; + /* Clear CLKEN, CPOL, CPHA, LBCL and SSM bits */ + tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK); + /* Configure the USART Clock, CPOL, CPHA, LastBit and SSM ------------*/ + /* Set CLKEN bit according to USART_Clock value */ + /* Set CPOL bit according to USART_CPOL value */ + /* Set CPHA bit according to USART_CPHA value */ + /* Set LBCL bit according to USART_LastBit value */ + tmpreg |= (uint32_t)(USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | + USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit); + /* Write to USART CR2 */ + USARTx->CR2 = tmpreg; +} + +/** + * @brief Fills each USART_ClockInitStruct member with its default value. + * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef + * structure which will be initialized. + * @retval None + */ +void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) +{ + /* USART_ClockInitStruct members default value */ + USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; + USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; + USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; + USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; +} + +/** + * @brief Enables or disables the specified USART peripheral. + * @param USARTx: where x can be 1 or 2 to select the USART peripheral. + * @param NewState: new state of the USARTx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected USART by setting the UE bit in the CR1 register */ + USARTx->CR1 |= USART_CR1_UE; + } + else + { + /* Disable the selected USART by clearing the UE bit in the CR1 register */ + USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UE); + } +} + +/** + * @brief Enables or disables the USART's transmitter or receiver. + * @param USARTx: where x can be 1 or 2 to select the USART peripheral. + * @param USART_Direction: specifies the USART direction. + * This parameter can be any combination of the following values: + * @arg USART_Mode_Tx: USART Transmitter + * @arg USART_Mode_Rx: USART Receiver + * @param NewState: new state of the USART transfer direction. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_MODE(USART_DirectionMode)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the USART's transfer interface by setting the TE and/or RE bits + in the USART CR1 register */ + USARTx->CR1 |= USART_DirectionMode; + } + else + { + /* Disable the USART's transfer interface by clearing the TE and/or RE bits + in the USART CR3 register */ + USARTx->CR1 &= (uint32_t)~USART_DirectionMode; + } +} + +/** + * @brief Enables or disables the USART's 8x oversampling mode. + * @param USARTx: where x can be 1 or 2 to select the USART peripheral. + * @param NewState: new state of the USART 8x oversampling mode. + * This parameter can be: ENABLE or DISABLE. + * @note + * This function has to be called before calling USART_Init() + * function in order to have correct baudrate Divider value. + * @retval None + */ +void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */ + USARTx->CR1 |= USART_CR1_OVER8; + } + else + { + /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */ + USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_OVER8); + } +} + +/** + * @brief Enables or disables the USART's one bit sampling method. + * @param USARTx: where x can be 1 or 2 to select the USART peripheral. + * @param NewState: new state of the USART one bit sampling method. + * This parameter can be: ENABLE or DISABLE. + * @note + * This function has to be called before calling USART_Cmd() function. + * @retval None + */ +void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */ + USARTx->CR3 |= USART_CR3_ONEBIT; + } + else + { + /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */ + USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT); + } +} + +/** + * @brief Enables or disables the USART's most significant bit first + * transmitted/received following the start bit. + * @param USARTx: where x can be 1 or 2 to select the USART peripheral. + * @param NewState: new state of the USART most significant bit first + * transmitted/received following the start bit. + * This parameter can be: ENABLE or DISABLE. + * @note + * This function has to be called before calling USART_Cmd() function. + * @retval None + */ +void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the most significant bit first transmitted/received following the + start bit by setting the MSBFIRST bit in the CR2 register */ + USARTx->CR2 |= USART_CR2_MSBFIRST; + } + else + { + /* Disable the most significant bit first transmitted/received following the + start bit by clearing the MSBFIRST bit in the CR2 register */ + USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_MSBFIRST); + } +} + +/** + * @brief Enables or disables the binary data inversion. + * @param USARTx: where x can be 1 or 2 to select the USART peripheral. + * @param NewState: new defined levels for the USART data. + * This parameter can be: ENABLE or DISABLE. + * - ENABLE: Logical data from the data register are send/received in negative + * logic. (1=L, 0=H). The parity bit is also inverted. + * - DISABLE: Logical data from the data register are send/received in positive + * logic. (1=H, 0=L) + * @note + * This function has to be called before calling USART_Cmd() function. + * @retval None + */ +void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the binary data inversion feature by setting the DATAINV bit in + the CR2 register */ + USARTx->CR2 |= USART_CR2_DATAINV; + } + else + { + /* Disable the binary data inversion feature by clearing the DATAINV bit in + the CR2 register */ + USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_DATAINV); + } +} + +/** + * @brief Enables or disables the Pin(s) active level inversion. + * @param USARTx: where x can be 1 or 2 to select the USART peripheral. + * @param USART_InvPin: specifies the USART pin(s) to invert. + * This parameter can be any combination of the following values: + * @arg USART_InvPin_Tx: USART Tx pin active level inversion. + * @arg USART_InvPin_Rx: USART Rx pin active level inversion. + * @param NewState: new active level status for the USART pin(s). + * This parameter can be: ENABLE or DISABLE. + * - ENABLE: pin(s) signal values are inverted (Vdd =0, Gnd =1). + * - DISABLE: pin(s) signal works using the standard logic levels (Vdd =1, Gnd =0). + * @note + * This function has to be called before calling USART_Cmd() function. + * @retval None + */ +void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_INVERSTION_PIN(USART_InvPin)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the active level inversion for selected pins by setting the TXINV + and/or RXINV bits in the USART CR2 register */ + USARTx->CR2 |= USART_InvPin; + } + else + { + /* Disable the active level inversion for selected requests by clearing the + TXINV and/or RXINV bits in the USART CR2 register */ + USARTx->CR2 &= (uint32_t)~USART_InvPin; + } +} + +/** + * @brief Enables or disables the swap Tx/Rx pins. + * @param USARTx: where x can be 1 or 2 to select the USART peripheral. + * @param NewState: new state of the USARTx TX/RX pins pinout. + * This parameter can be: ENABLE or DISABLE. + * - ENABLE: The TX and RX pins functions are swapped. + * - DISABLE: TX/RX pins are used as defined in standard pinout + * @note + * This function has to be called before calling USART_Cmd() function. + * @retval None + */ +void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the SWAP feature by setting the SWAP bit in the CR2 register */ + USARTx->CR2 |= USART_CR2_SWAP; + } + else + { + /* Disable the SWAP feature by clearing the SWAP bit in the CR2 register */ + USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_SWAP); + } +} + +/** + * @brief Enables or disables the receiver Time Out feature. + * @param USARTx: where x can be 1 to select the USART peripheral. + * @param NewState: new state of the USARTx receiver Time Out. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_1_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the receiver time out feature by setting the RTOEN bit in the CR2 + register */ + USARTx->CR2 |= USART_CR2_RTOEN; + } + else + { + /* Disable the receiver time out feature by clearing the RTOEN bit in the CR2 + register */ + USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_RTOEN); + } +} + +/** + * @brief Sets the receiver Time Out value. + * @param USARTx: where x can be 1 to select the USART peripheral. + * @param USART_ReceiverTimeOut: specifies the Receiver Time Out value. + * @retval None + */ +void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut) +{ + /* Check the parameters */ + assert_param(IS_USART_1_PERIPH(USARTx)); + assert_param(IS_USART_TIMEOUT(USART_ReceiverTimeOut)); + + /* Clear the receiver Time Out value by clearing the RTO[23:0] bits in the RTOR + register */ + USARTx->RTOR &= (uint32_t)~((uint32_t)USART_RTOR_RTO); + /* Set the receiver Time Out value by setting the RTO[23:0] bits in the RTOR + register */ + USARTx->RTOR |= USART_ReceiverTimeOut; +} + +/** + * @brief Sets the system clock prescaler. + * @param USARTx: where x can be 1 to select the USART peripheral. + * @param USART_Prescaler: specifies the prescaler clock. + * @note + * This function has to be called before calling USART_Cmd() function. + * @retval None + */ +void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_USART_1_PERIPH(USARTx)); + + /* Clear the USART prescaler */ + USARTx->GTPR &= USART_GTPR_GT; + /* Set the USART prescaler */ + USARTx->GTPR |= USART_Prescaler; +} + +/** + * @} + */ + + +/** @defgroup USART_Group2 STOP Mode functions + * @brief STOP Mode functions + * +@verbatim + =============================================================================== + ##### STOP Mode functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage + WakeUp from STOP mode. + + [..] The USART is able to WakeUp from Stop Mode if USART clock is set to HSI + or LSI. + + [..] The WakeUp source is configured by calling USART_StopModeWakeUpSourceConfig() + function. + + [..] After configuring the source of WakeUp and before entering in Stop Mode + USART_STOPModeCmd() function should be called to allow USART WakeUp. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified USART peripheral in STOP Mode. + * @param USARTx: where x can be 1 to select the USART peripheral. + * @param NewState: new state of the USARTx peripheral state in stop mode. + * This parameter can be: ENABLE or DISABLE. + * @note + * This function has to be called when USART clock is set to HSI or LSE. + * @retval None + */ +void USART_STOPModeCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_1_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected USART in STOP mode by setting the UESM bit in the CR1 + register */ + USARTx->CR1 |= USART_CR1_UESM; + } + else + { + /* Disable the selected USART in STOP mode by clearing the UE bit in the CR1 + register */ + USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UESM); + } +} + +/** + * @brief Selects the USART WakeUp method form stop mode. + * @param USARTx: where x can be 1 to select the USART peripheral. + * @param USART_WakeUp: specifies the selected USART wakeup method. + * This parameter can be one of the following values: + * @arg USART_WakeUpSource_AddressMatch: WUF active on address match. + * @arg USART_WakeUpSource_StartBit: WUF active on Start bit detection. + * @arg USART_WakeUpSource_RXNE: WUF active on RXNE. + * @note + * This function has to be called before calling USART_Cmd() function. + * @retval None + */ +void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUpSource) +{ + /* Check the parameters */ + assert_param(IS_USART_1_PERIPH(USARTx)); + assert_param(IS_USART_STOPMODE_WAKEUPSOURCE(USART_WakeUpSource)); + + USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_WUS); + USARTx->CR3 |= USART_WakeUpSource; +} + +/** + * @} + */ + + +/** @defgroup USART_Group3 AutoBaudRate functions + * @brief AutoBaudRate functions + * +@verbatim + =============================================================================== + ##### AutoBaudRate functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage + the AutoBaudRate detections. + + [..] Before Enabling AutoBaudRate detection using USART_AutoBaudRateCmd () + The character patterns used to calculate baudrate must be chosen by calling + USART_AutoBaudRateConfig() function. These function take as parameter : + (#)USART_AutoBaudRate_StartBit : any character starting with a bit 1. + (#)USART_AutoBaudRate_FallingEdge : any character starting with a 10xx bit pattern. + + [..] At any later time, another request for AutoBaudRate detection can be performed + using USART_AutoBaudRateNewRequest() function. + + [..] The AutoBaudRate detection is monitored by the status of ABRF flag which indicate + that the AutoBaudRate detection is completed. In addition to ABRF flag, the ABRE flag + indicate that this procedure is completed without success. USART_GetFlagStatus () + function should be used to monitor the status of these flags. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the Auto Baud Rate. + * @param USARTx: where x can be 1 to select the USART peripheral. + * @param NewState: new state of the USARTx auto baud rate. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_1_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the auto baud rate feature by setting the ABREN bit in the CR2 + register */ + USARTx->CR2 |= USART_CR2_ABREN; + } + else + { + /* Disable the auto baud rate feature by clearing the ABREN bit in the CR2 + register */ + USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ABREN); + } +} + +/** + * @brief Selects the USART auto baud rate method. + * @param USARTx: where x can be 1 to select the USART peripheral. + * @param USART_AutoBaudRate: specifies the selected USART auto baud rate method. + * This parameter can be one of the following values: + * @arg USART_AutoBaudRate_StartBit: Start Bit duration measurement. + * @arg USART_AutoBaudRate_FallingEdge: Falling edge to falling edge measurement. + * @note + * This function has to be called before calling USART_Cmd() function. + * @retval None + */ +void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate) +{ + /* Check the parameters */ + assert_param(IS_USART_1_PERIPH(USARTx)); + assert_param(IS_USART_AUTOBAUDRATE_MODE(USART_AutoBaudRate)); + + USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ABRMODE); + USARTx->CR2 |= USART_AutoBaudRate; +} + +/** + * @brief Requests a new AutoBaudRate detection. + * @param USARTx: where x can be 1 to select the USART peripheral. + * @retval None + */ +void USART_AutoBaudRateNewRequest(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + USARTx->ISR &= (uint32_t)~((uint32_t)USART_FLAG_ABRF); +} + +/** + * @} + */ + + +/** @defgroup USART_Group4 Data transfers functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### Data transfers functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage + the USART data transfers. + [..] During an USART reception, data shifts in least significant bit first + through the RX pin. When a transmission is taking place, a write instruction to + the USART_TDR register stores the data in the shift register. + [..] The read access of the USART_RDR register can be done using + the USART_ReceiveData() function and returns the RDR value. + Whereas a write access to the USART_TDR can be done using USART_SendData() + function and stores the written data into TDR. + +@endverbatim + * @{ + */ + +/** + * @brief Transmits single data through the USARTx peripheral. + * @param USARTx: where x can be 1 or 2 to select the USART peripheral. + * @param Data: the data to transmit. + * @retval None + */ +void USART_SendData(USART_TypeDef* USARTx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DATA(Data)); + + /* Transmit Data */ + USARTx->TDR = (Data & (uint16_t)0x01FF); +} + +/** + * @brief Returns the most recent received data by the USARTx peripheral. + * @param USARTx: where x can be 1 or 2 to select the USART peripheral. + * @retval The received data. + */ +uint16_t USART_ReceiveData(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Receive Data */ + return (uint16_t)(USARTx->RDR & (uint16_t)0x01FF); +} + +/** + * @} + */ + +/** @defgroup USART_Group5 MultiProcessor Communication functions + * @brief Multi-Processor Communication functions + * +@verbatim + =============================================================================== + ##### Multi-Processor Communication functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage the USART + multiprocessor communication. + [..] For instance one of the USARTs can be the master, its TX output is + connected to the RX input of the other USART. The others are slaves, + their respective TX outputs are logically ANDed together and connected + to the RX input of the master. USART multiprocessor communication is + possible through the following procedure: + (#) Program the Baud rate, Word length = 9 bits, Stop bits, Parity, + Mode transmitter or Mode receiver and hardware flow control values + using the USART_Init() function. + (#) Configures the USART address using the USART_SetAddress() function. + (#) Configures the wake up methode (USART_WakeUp_IdleLine or + USART_WakeUp_AddressMark) using USART_WakeUpConfig() function only + for the slaves. + (#) Enable the USART using the USART_Cmd() function. + (#) Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() + function. + [..] The USART Slave exit from mute mode when receive the wake up condition. + +@endverbatim + * @{ + */ + +/** + * @brief Sets the address of the USART node. + * @param USARTx: where x can be 1 or 2 to select the USART peripheral. + * @param USART_Address: Indicates the address of the USART node. + * @retval None + */ +void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Clear the USART address */ + USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ADD); + /* Set the USART address node */ + USARTx->CR2 |=((uint32_t)USART_Address << (uint32_t)0x18); +} + +/** + * @brief Enables or disables the USART's mute mode. + * @param USARTx: where x can be 1 or 2 to select the USART peripheral. + * @param NewState: new state of the USART mute mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the USART mute mode by setting the MME bit in the CR1 register */ + USARTx->CR1 |= USART_CR1_MME; + } + else + { + /* Disable the USART mute mode by clearing the MME bit in the CR1 register */ + USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_MME); + } +} + +/** + * @brief Selects the USART WakeUp method from mute mode. + * @param USARTx: where x can be 1 or 2 to select the USART peripheral. + * @param USART_WakeUp: specifies the USART wakeup method. + * This parameter can be one of the following values: + * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection + * @arg USART_WakeUp_AddressMark: WakeUp by an address mark + * @retval None + */ +void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_MUTEMODE_WAKEUP(USART_WakeUp)); + + USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_WAKE); + USARTx->CR1 |= USART_WakeUp; +} + +/** + * @brief Configure the the USART Address detection length. + * @param USARTx: where x can be 1 or 2 to select the USART peripheral. + * @param USART_AddressLength: specifies the USART address length detection. + * This parameter can be one of the following values: + * @arg USART_AddressLength_4b: 4-bit address length detection + * @arg USART_AddressLength_7b: 7-bit address length detection + * @retval None + */ +void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_ADDRESS_DETECTION(USART_AddressLength)); + + USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ADDM7); + USARTx->CR2 |= USART_AddressLength; +} + +/** + * @} + */ + +/** @defgroup USART_Group6 LIN mode functions + * @brief LIN mode functions + * +@verbatim + =============================================================================== + ##### LIN mode functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage the USART + LIN Mode communication. + [..] In LIN mode, 8-bit data format with 1 stop bit is required in accordance + with the LIN standard. + [..] Only this LIN Feature is supported by the USART IP: + (+) LIN Master Synchronous Break send capability and LIN slave break + detection capability : 13-bit break generation and 10/11 bit break + detection. + [..] USART LIN Master transmitter communication is possible through the + following procedure: + (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, + Mode transmitter or Mode receiver and hardware flow control values + using the USART_Init() function. + (#) Enable the LIN mode using the USART_LINCmd() function. + (#) Enable the USART using the USART_Cmd() function. + (#) Send the break character using USART_SendBreak() function. + [..] USART LIN Master receiver communication is possible through the + following procedure: + (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, + Mode transmitter or Mode receiver and hardware flow control values + using the USART_Init() function. + (#) Configures the break detection length + using the USART_LINBreakDetectLengthConfig() function. + (#) Enable the LIN mode using the USART_LINCmd() function. + -@- In LIN mode, the following bits must be kept cleared: + (+@) CLKEN in the USART_CR2 register. + (+@) STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register. + (#) Enable the USART using the USART_Cmd() function. + +@endverbatim + * @{ + */ + +/** + * @brief Sets the USART LIN Break detection length. + * @param USARTx: where x can be 1 to select the USART peripheral. + * @param USART_LINBreakDetectLength: specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg USART_LINBreakDetectLength_10b: 10-bit break detection + * @arg USART_LINBreakDetectLength_11b: 11-bit break detection + * @retval None + */ +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint32_t USART_LINBreakDetectLength) +{ + /* Check the parameters */ + assert_param(IS_USART_1_PERIPH(USARTx)); + assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); + + USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_LBDL); + USARTx->CR2 |= USART_LINBreakDetectLength; +} + +/** + * @brief Enables or disables the USART's LIN mode. + * @param USARTx: where x can be 1 to select the USART peripheral. + * @param NewState: new state of the USART LIN mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_1_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + USARTx->CR2 |= USART_CR2_LINEN; + } + else + { + /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */ + USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_LINEN); + } +} + +/** + * @} + */ + +/** @defgroup USART_Group7 Halfduplex mode function + * @brief Half-duplex mode function + * +@verbatim + =============================================================================== + ##### Half-duplex mode function ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage the USART + Half-duplex communication. + [..] The USART can be configured to follow a single-wire half-duplex protocol + where the TX and RX lines are internally connected. + [..] USART Half duplex communication is possible through the following procedure: + (#) Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter + or Mode receiver and hardware flow control values using the USART_Init() + function. + (#) Configures the USART address using the USART_SetAddress() function. + (#) Enable the half duplex mode using USART_HalfDuplexCmd() function. + (#) Enable the USART using the USART_Cmd() function. + -@- The RX pin is no longer used. + -@- In Half-duplex mode the following bits must be kept cleared: + (+@) LINEN and CLKEN bits in the USART_CR2 register. + (+@) SCEN and IREN bits in the USART_CR3 register. + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the USART's Half Duplex communication. + * @param USARTx: where x can be 1 or 2 to select the USART peripheral. + * @param NewState: new state of the USART Communication. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + USARTx->CR3 |= USART_CR3_HDSEL; + } + else + { + /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ + USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_HDSEL); + } +} + +/** + * @} + */ + + +/** @defgroup USART_Group8 Smartcard mode functions + * @brief Smartcard mode functions + * +@verbatim + =============================================================================== + ##### Smartcard mode functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage the USART + Smartcard communication. + [..] The Smartcard interface is designed to support asynchronous protocol + Smartcards as defined in the ISO 7816-3 standard. The USART can provide + a clock to the smartcard through the SCLK output. In smartcard mode, + SCLK is not associated to the communication but is simply derived from + the internal peripheral input clock through a 5-bit prescaler. + [..] Smartcard communication is possible through the following procedure: + (#) Configures the Smartcard Prsecaler using the USART_SetPrescaler() + function. + (#) Configures the Smartcard Guard Time using the USART_SetGuardTime() + function. + (#) Program the USART clock using the USART_ClockInit() function as following: + (++) USART Clock enabled. + (++) USART CPOL Low. + (++) USART CPHA on first edge. + (++) USART Last Bit Clock Enabled. + (#) Program the Smartcard interface using the USART_Init() function as + following: + (++) Word Length = 9 Bits. + (++) 1.5 Stop Bit. + (++) Even parity. + (++) BaudRate = 12096 baud. + (++) Hardware flow control disabled (RTS and CTS signals). + (++) Tx and Rx enabled + (#) Optionally you can enable the parity error interrupt using + the USART_ITConfig() function. + (#) Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function. + (#) Enable the Smartcard interface using the USART_SmartCardCmd() function. + (#) Enable the USART using the USART_Cmd() function. + [..] + Please refer to the ISO 7816-3 specification for more details. + [..] + (@) It is also possible to choose 0.5 stop bit for receiving but it is + recommended to use 1.5 stop bits for both transmitting and receiving + to avoid switching between the two configurations. + (@) In smartcard mode, the following bits must be kept cleared: + (+@) LINEN bit in the USART_CR2 register. + (+@) HDSEL and IREN bits in the USART_CR3 register. + +@endverbatim + * @{ + */ + +/** + * @brief Sets the specified USART guard time. + * @param USARTx: where x can be 1 to select the USART peripheral. + * @param USART_GuardTime: specifies the guard time. + * @retval None + */ +void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime) +{ + /* Check the parameters */ + assert_param(IS_USART_1_PERIPH(USARTx)); + + /* Clear the USART Guard time */ + USARTx->GTPR &= USART_GTPR_PSC; + /* Set the USART guard time */ + USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); +} + +/** + * @brief Enables or disables the USART's Smart Card mode. + * @param USARTx: where x can be 1 to select the USART peripheral. + * @param NewState: new state of the Smart Card mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_1_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the SC mode by setting the SCEN bit in the CR3 register */ + USARTx->CR3 |= USART_CR3_SCEN; + } + else + { + /* Disable the SC mode by clearing the SCEN bit in the CR3 register */ + USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_SCEN); + } +} + +/** + * @brief Enables or disables NACK transmission. + * @param USARTx: where x can be 1 to select the USART peripheral. + * @param NewState: new state of the NACK transmission. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_1_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the NACK transmission by setting the NACK bit in the CR3 register */ + USARTx->CR3 |= USART_CR3_NACK; + } + else + { + /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */ + USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_NACK); + } +} + +/** + * @brief Sets the Smart Card number of retries in transmit and receive. + * @param USARTx: where x can be 1 to select the USART peripheral. + * @param USART_AutoCount: specifies the Smart Card auto retry count. + * @retval None + */ +void USART_SetAutoRetryCount(USART_TypeDef* USARTx, uint8_t USART_AutoCount) +{ + /* Check the parameters */ + assert_param(IS_USART_1_PERIPH(USARTx)); + assert_param(IS_USART_AUTO_RETRY_COUNTER(USART_AutoCount)); + /* Clear the USART auto retry count */ + USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_SCARCNT); + /* Set the USART auto retry count*/ + USARTx->CR3 |= (uint32_t)((uint32_t)USART_AutoCount << 0x11); +} + +/** + * @brief Sets the Smart Card Block length. + * @param USARTx: where x can be 1 to select the USART peripheral. + * @param USART_BlockLength: specifies the Smart Card block length. + * @retval None + */ +void USART_SetBlockLength(USART_TypeDef* USARTx, uint8_t USART_BlockLength) +{ + /* Check the parameters */ + assert_param(IS_USART_1_PERIPH(USARTx)); + + /* Clear the Smart card block length */ + USARTx->RTOR &= (uint32_t)~((uint32_t)USART_RTOR_BLEN); + /* Set the Smart Card block length */ + USARTx->RTOR |= (uint32_t)((uint32_t)USART_BlockLength << 0x18); +} + +/** + * @} + */ + +/** @defgroup USART_Group9 IrDA mode functions + * @brief IrDA mode functions + * +@verbatim + =============================================================================== + ##### IrDA mode functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage the USART + IrDA communication. + [..] IrDA is a half duplex communication protocol. If the Transmitter is busy, + any data on the IrDA receive line will be ignored by the IrDA decoder + and if the Receiver is busy, data on the TX from the USART to IrDA will + not be encoded by IrDA. While receiving data, transmission should be + avoided as the data to be transmitted could be corrupted. + [..] IrDA communication is possible through the following procedure: + (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity, + Transmitter/Receiver modes and hardware flow control values using + the USART_Init() function. + (#) Configures the IrDA pulse width by configuring the prescaler using + the USART_SetPrescaler() function. + (#) Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal + mode using the USART_IrDAConfig() function. + (#) Enable the IrDA using the USART_IrDACmd() function. + (#) Enable the USART using the USART_Cmd() function. + [..] + (@) A pulse of width less than two and greater than one PSC period(s) may or + may not be rejected. + (@) The receiver set up time should be managed by software. The IrDA physical + layer specification specifies a minimum of 10 ms delay between + transmission and reception (IrDA is a half duplex protocol). + (@) In IrDA mode, the following bits must be kept cleared: + (+@) LINEN, STOP and CLKEN bits in the USART_CR2 register. + (+@) SCEN and HDSEL bits in the USART_CR3 register. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the USART's IrDA interface. + * @param USARTx: where x can be 1 to select the USART peripheral. + * @param USART_IrDAMode: specifies the IrDA mode. + * This parameter can be one of the following values: + * @arg USART_IrDAMode_LowPower + * @arg USART_IrDAMode_Normal + * @retval None + */ +void USART_IrDAConfig(USART_TypeDef* USARTx, uint32_t USART_IrDAMode) +{ + /* Check the parameters */ + assert_param(IS_USART_1_PERIPH(USARTx)); + assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); + + USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_IRLP); + USARTx->CR3 |= USART_IrDAMode; +} + +/** + * @brief Enables or disables the USART's IrDA interface. + * @param USARTx: where x can be 1 to select the USART peripheral. + * @param NewState: new state of the IrDA mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_1_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ + USARTx->CR3 |= USART_CR3_IREN; + } + else + { + /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */ + USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_IREN); + } +} +/** + * @} + */ + +/** @defgroup USART_Group10 RS485 mode function + * @brief RS485 mode function + * +@verbatim + =============================================================================== + ##### RS485 mode functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage the USART + RS485 flow control. + [..] RS485 flow control (Driver enable feature) handling is possible through + the following procedure: + (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity, + Transmitter/Receiver modes and hardware flow control values using + the USART_Init() function. + (#) Enable the Driver Enable using the USART_DECmd() function. + (#) Configures the Driver Enable polarity using the USART_DEPolarityConfig() + function. + (#) Configures the Driver Enable assertion time using USART_SetDEAssertionTime() + function and deassertion time using the USART_SetDEDeassertionTime() + function. + (#) Enable the USART using the USART_Cmd() function. + -@- + (+@) The assertion and dessertion times are expressed in sample time units (1/8 or + 1/16 bit time, depending on the oversampling rate). + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the USART's DE functionality. + * @param USARTx: where x can be 1 or 2 to select the USART peripheral. + * @param NewState: new state of the driver enable mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the DE functionality by setting the DEM bit in the CR3 register */ + USARTx->CR3 |= USART_CR3_DEM; + } + else + { + /* Disable the DE functionality by clearing the DEM bit in the CR3 register */ + USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DEM); + } +} + +/** + * @brief Configures the USART's DE polarity + * @param USARTx: where x can be 1 or 2 to select the USART peripheral. + * @param USART_DEPolarity: specifies the DE polarity. + * This parameter can be one of the following values: + * @arg USART_DEPolarity_Low + * @arg USART_DEPolarity_High + * @retval None + */ +void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DE_POLARITY(USART_DEPolarity)); + + USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DEP); + USARTx->CR3 |= USART_DEPolarity; +} + +/** + * @brief Sets the specified RS485 DE assertion time + * @param USARTx: where x can be 1 or 2 to select the USART peripheral. + * @param USART_AssertionTime: specifies the time between the activation of the DE + * signal and the beginning of the start bit + * @retval None + */ +void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DE_ASSERTION_DEASSERTION_TIME(USART_DEAssertionTime)); + + /* Clear the DE assertion time */ + USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_DEAT); + /* Set the new value for the DE assertion time */ + USARTx->CR1 |=((uint32_t)USART_DEAssertionTime << (uint32_t)0x15); +} + +/** + * @brief Sets the specified RS485 DE deassertion time + * @param USARTx: where x can be 1 or 2 to select the USART peripheral. + * @param USART_DeassertionTime: specifies the time between the middle of the last + * stop bit in a transmitted message and the de-activation of the DE signal + * @retval None + */ +void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DE_ASSERTION_DEASSERTION_TIME(USART_DEDeassertionTime)); + + /* Clear the DE deassertion time */ + USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_DEDT); + /* Set the new value for the DE deassertion time */ + USARTx->CR1 |=((uint32_t)USART_DEDeassertionTime << (uint32_t)0x10); +} + +/** + * @} + */ + +/** @defgroup USART_Group11 DMA transfers management functions + * @brief DMA transfers management functions + * +@verbatim + =============================================================================== + ##### DMA transfers management functions ##### + =============================================================================== + [..] This section provides two functions that can be used only in DMA mode. + [..] In DMA Mode, the USART communication can be managed by 2 DMA Channel + requests: + (#) USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request. + (#) USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request. + [..] In this Mode it is advised to use the following function: + (+) void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, + FunctionalState NewState). +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the USART's DMA interface. + * @param USARTx: where x can be 1 or 2 to select the USART peripheral. + * @param USART_DMAReq: specifies the DMA request. + * This parameter can be any combination of the following values: + * @arg USART_DMAReq_Tx: USART DMA transmit request + * @arg USART_DMAReq_Rx: USART DMA receive request + * @param NewState: new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DMAREQ(USART_DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA transfer for selected requests by setting the DMAT and/or + DMAR bits in the USART CR3 register */ + USARTx->CR3 |= USART_DMAReq; + } + else + { + /* Disable the DMA transfer for selected requests by clearing the DMAT and/or + DMAR bits in the USART CR3 register */ + USARTx->CR3 &= (uint32_t)~USART_DMAReq; + } +} + +/** + * @brief Enables or disables the USART's DMA interface when reception error occurs. + * @param USARTx: where x can be 1 or 2 to select the USART peripheral. + * @param USART_DMAOnError: specifies the DMA status in case of reception error. + * This parameter can be any combination of the following values: + * @arg USART_DMAOnError_Enable: DMA receive request enabled when the USART DMA + * reception error is asserted. + * @arg USART_DMAOnError_Disable: DMA receive request disabled when the USART DMA + * reception error is asserted. + * @retval None + */ +void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DMAONERROR(USART_DMAOnError)); + + /* Clear the DMA Reception error detection bit */ + USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DDRE); + /* Set the new value for the DMA Reception error detection bit */ + USARTx->CR3 |= USART_DMAOnError; +} + +/** + * @} + */ + +/** @defgroup USART_Group12 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + =============================================================================== + ##### Interrupts and flags management functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to configure the + USART Interrupts sources, Requests and check or clear the flags or pending bits status. + The user should identify which mode will be used in his application to + manage the communication: Polling mode, Interrupt mode. + + *** Polling Mode *** + ==================== + [..] In Polling Mode, the SPI communication can be managed by these flags: + (#) USART_FLAG_REACK: to indicate the status of the Receive Enable + acknowledge flag + (#) USART_FLAG_TEACK: to indicate the status of the Transmit Enable + acknowledge flag. + (#) USART_FLAG_WUF: to indicate the status of the Wake up flag. + (#) USART_FLAG_RWU: to indicate the status of the Receive Wake up flag. + (#) USART_FLAG_SBK: to indicate the status of the Send Break flag. + (#) USART_FLAG_CMF: to indicate the status of the Character match flag. + (#) USART_FLAG_BUSY: to indicate the status of the Busy flag. + (#) USART_FLAG_ABRF: to indicate the status of the Auto baud rate flag. + (#) USART_FLAG_ABRE: to indicate the status of the Auto baud rate error flag. + (#) USART_FLAG_EOBF: to indicate the status of the End of block flag. + (#) USART_FLAG_RTOF: to indicate the status of the Receive time out flag. + (#) USART_FLAG_nCTSS: to indicate the status of the Inverted nCTS input + bit status. + (#) USART_FLAG_TXE: to indicate the status of the transmit buffer register. + (#) USART_FLAG_RXNE: to indicate the status of the receive buffer register. + (#) USART_FLAG_TC: to indicate the status of the transmit operation. + (#) USART_FLAG_IDLE: to indicate the status of the Idle Line. + (#) USART_FLAG_CTS: to indicate the status of the nCTS input. + (#) USART_FLAG_LBD: to indicate the status of the LIN break detection. + (#) USART_FLAG_NE: to indicate if a noise error occur. + (#) USART_FLAG_FE: to indicate if a frame error occur. + (#) USART_FLAG_PE: to indicate if a parity error occur. + (#) USART_FLAG_ORE: to indicate if an Overrun error occur. + [..] In this Mode it is advised to use the following functions: + (+) FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG). + (+) void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG). + + *** Interrupt Mode *** + ====================== + [..] In Interrupt Mode, the USART communication can be managed by 8 interrupt + sources and 10 pending bits: + (+) Pending Bits: + (##) USART_IT_WU: to indicate the status of the Wake up interrupt. + (##) USART_IT_CM: to indicate the status of Character match interrupt. + (##) USART_IT_EOB: to indicate the status of End of block interrupt. + (##) USART_IT_RTO: to indicate the status of Receive time out interrupt. + (##) USART_IT_CTS: to indicate the status of CTS change interrupt. + (##) USART_IT_LBD: to indicate the status of LIN Break detection interrupt. + (##) USART_IT_TC: to indicate the status of Transmission complete interrupt. + (##) USART_IT_IDLE: to indicate the status of IDLE line detected interrupt. + (##) USART_IT_ORE: to indicate the status of OverRun Error interrupt. + (##) USART_IT_NE: to indicate the status of Noise Error interrupt. + (##) USART_IT_FE: to indicate the status of Framing Error interrupt. + (##) USART_IT_PE: to indicate the status of Parity Error interrupt. + + (+) Interrupt Source: + (##) USART_IT_WU: specifies the interrupt source for Wake up interrupt. + (##) USART_IT_CM: specifies the interrupt source for Character match + interrupt. + (##) USART_IT_EOB: specifies the interrupt source for End of block + interrupt. + (##) USART_IT_RTO: specifies the interrupt source for Receive time-out + interrupt. + (##) USART_IT_CTS: specifies the interrupt source for CTS change interrupt. + (##) USART_IT_LBD: specifies the interrupt source for LIN Break + detection interrupt. + (##) USART_IT_TXE: specifies the interrupt source for Tansmit Data + Register empty interrupt. + (##) USART_IT_TC: specifies the interrupt source for Transmission + complete interrupt. + (##) USART_IT_RXNE: specifies the interrupt source for Receive Data + register not empty interrupt. + (##) USART_IT_IDLE: specifies the interrupt source for Idle line + detection interrupt. + (##) USART_IT_PE: specifies the interrupt source for Parity Error interrupt. + (##) USART_IT_ERR: specifies the interrupt source for Error interrupt + (Frame error, noise error, overrun error) + -@@- Some parameters are coded in order to use them as interrupt + source or as pending bits. + [..] In this Mode it is advised to use the following functions: + (+) void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState). + (+) ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT). + (+) void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT). + +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified USART interrupts. + * @param USARTx: where x can be 1 or 2 to select the USART peripheral. + * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg USART_IT_WU: Wake up interrupt. + * @arg USART_IT_CM: Character match interrupt. + * @arg USART_IT_EOB: End of block interrupt. + * @arg USART_IT_RTO: Receive time out interrupt. + * @arg USART_IT_CTS: CTS change interrupt. + * @arg USART_IT_LBD: LIN Break detection interrupt. + * @arg USART_IT_TXE: Tansmit Data Register empty interrupt. + * @arg USART_IT_TC: Transmission complete interrupt. + * @arg USART_IT_RXNE: Receive Data register not empty interrupt. + * @arg USART_IT_IDLE: Idle line detection interrupt. + * @arg USART_IT_PE: Parity Error interrupt. + * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @param NewState: new state of the specified USARTx interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState) +{ + uint32_t usartreg = 0, itpos = 0, itmask = 0; + uint32_t usartxbase = 0; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CONFIG_IT(USART_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + usartxbase = (uint32_t)USARTx; + + /* Get the USART register index */ + usartreg = (((uint16_t)USART_IT) >> 0x08); + + /* Get the interrupt position */ + itpos = USART_IT & IT_MASK; + itmask = (((uint32_t)0x01) << itpos); + + if (usartreg == 0x02) /* The IT is in CR2 register */ + { + usartxbase += 0x04; + } + else if (usartreg == 0x03) /* The IT is in CR3 register */ + { + usartxbase += 0x08; + } + else /* The IT is in CR1 register */ + { + } + if (NewState != DISABLE) + { + *(__IO uint32_t*)usartxbase |= itmask; + } + else + { + *(__IO uint32_t*)usartxbase &= ~itmask; + } +} + +/** + * @brief Enables the specified USART's Request. + * @param USARTx: where x can be 1 or 2 to select the USART peripheral. + * @param USART_Request: specifies the USART request. + * This parameter can be any combination of the following values: + * @arg USART_Request_TXFRQ: Transmit data flush ReQuest + * @arg USART_Request_RXFRQ: Receive data flush ReQuest + * @arg USART_Request_MMRQ: Mute Mode ReQuest + * @arg USART_Request_SBKRQ: Send Break ReQuest + * @arg USART_Request_ABRRQ: Auto Baud Rate ReQuest + * @param NewState: new state of the DMA interface when reception error occurs. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_REQUEST(USART_Request)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the USART ReQuest by setting the dedicated request bit in the RQR + register.*/ + USARTx->RQR |= USART_Request; + } + else + { + /* Disable the USART ReQuest by clearing the dedicated request bit in the RQR + register.*/ + USARTx->RQR &= (uint32_t)~USART_Request; + } +} + +/** + * @brief Enables or disables the USART's Overrun detection. + * @param USARTx: where x can be 1 or 2 to select the USART peripheral. + * @param USART_OVRDetection: specifies the OVR detection status in case of OVR error. + * This parameter can be any combination of the following values: + * @arg USART_OVRDetection_Enable: OVR error detection enabled when the USART OVR error + * is asserted. + * @arg USART_OVRDetection_Disable: OVR error detection disabled when the USART OVR error + * is asserted. + * @retval None + */ +void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_OVRDETECTION(USART_OVRDetection)); + + /* Clear the OVR detection bit */ + USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_OVRDIS); + /* Set the new value for the OVR detection bit */ + USARTx->CR3 |= USART_OVRDetection; +} + +/** + * @brief Checks whether the specified USART flag is set or not. + * @param USARTx: where x can be 1 or 2 to select the USART peripheral. + * @param USART_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg USART_FLAG_REACK: Receive Enable acknowledge flag. + * @arg USART_FLAG_TEACK: Transmit Enable acknowledge flag. + * @arg USART_FLAG_WUF: Wake up flag. + * @arg USART_FLAG_RWU: Receive Wake up flag. + * @arg USART_FLAG_SBK: Send Break flag. + * @arg USART_FLAG_CMF: Character match flag. + * @arg USART_FLAG_BUSY: Busy flag. + * @arg USART_FLAG_ABRF: Auto baud rate flag. + * @arg USART_FLAG_ABRE: Auto baud rate error flag. + * @arg USART_FLAG_EOBF: End of block flag. + * @arg USART_FLAG_RTOF: Receive time out flag. + * @arg USART_FLAG_nCTSS: Inverted nCTS input bit status. + * @arg USART_FLAG_CTS: CTS Change flag. + * @arg USART_FLAG_LBD: LIN Break detection flag. + * @arg USART_FLAG_TXE: Transmit data register empty flag. + * @arg USART_FLAG_TC: Transmission Complete flag. + * @arg USART_FLAG_RXNE: Receive data register not empty flag. + * @arg USART_FLAG_IDLE: Idle Line detection flag. + * @arg USART_FLAG_ORE: OverRun Error flag. + * @arg USART_FLAG_NE: Noise Error flag. + * @arg USART_FLAG_FE: Framing Error flag. + * @arg USART_FLAG_PE: Parity Error flag. + * @retval The new state of USART_FLAG (SET or RESET). + */ +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_FLAG(USART_FLAG)); + + if ((USARTx->ISR & USART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the USARTx's pending flags. + * @param USARTx: where x can be 1 or 2 to select the USART peripheral. + * @param USART_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg USART_FLAG_WUF: Wake up flag. + * @arg USART_FLAG_CMF: Character match flag. + * @arg USART_FLAG_EOBF: End of block flag. + * @arg USART_FLAG_RTOF: Receive time out flag. + * @arg USART_FLAG_CTS: CTS Change flag. + * @arg USART_FLAG_LBD: LIN Break detection flag. + * @arg USART_FLAG_TC: Transmission Complete flag. + * @arg USART_FLAG_IDLE: IDLE line detected flag. + * @arg USART_FLAG_ORE: OverRun Error flag. + * @arg USART_FLAG_NE: Noise Error flag. + * @arg USART_FLAG_FE: Framing Error flag. + * @arg USART_FLAG_PE: Parity Errorflag. + * + * @note RXNE pending bit is cleared by a read to the USART_RDR register + * (USART_ReceiveData()) or by writing 1 to the RXFRQ in the register + * USART_RQR (USART_RequestCmd()). + * @note TC flag can be also cleared by software sequence: a read operation + * to USART_SR register (USART_GetFlagStatus()) followed by a write + * operation to USART_TDR register (USART_SendData()). + * @note TXE flag is cleared by a write to the USART_TDR register (USART_SendData()) + * or by writing 1 to the TXFRQ in the register USART_RQR (USART_RequestCmd()). + * @note SBKF flag is cleared by 1 to the SBKRQ in the register USART_RQR + * (USART_RequestCmd()). + * @retval None + */ +void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); + + USARTx->ICR = USART_FLAG; +} + +/** + * @brief Checks whether the specified USART interrupt has occurred or not. + * @param USARTx: where x can be 1 or 2 to select the USART peripheral. + * @param USART_IT: specifies the USART interrupt source to check. + * This parameter can be one of the following values: + * @arg USART_IT_WU: Wake up interrupt. + * @arg USART_IT_CM: Character match interrupt. + * @arg USART_IT_EOB: End of block interrupt. + * @arg USART_IT_RTO: Receive time out interrupt. + * @arg USART_IT_CTS: CTS change interrupt. + * @arg USART_IT_LBD: LIN Break detection interrupt. + * @arg USART_IT_TXE: Tansmit Data Register empty interrupt. + * @arg USART_IT_TC: Transmission complete interrupt. + * @arg USART_IT_RXNE: Receive Data register not empty interrupt. + * @arg USART_IT_IDLE: Idle line detection interrupt. + * @arg USART_IT_ORE: OverRun Error interrupt. + * @arg USART_IT_NE: Noise Error interrupt. + * @arg USART_IT_FE: Framing Error interrupt. + * @arg USART_IT_PE: Parity Error interrupt. + * @retval The new state of USART_IT (SET or RESET). + */ +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT) +{ + uint32_t bitpos = 0, itmask = 0, usartreg = 0; + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_GET_IT(USART_IT)); + + /* Get the USART register index */ + usartreg = (((uint16_t)USART_IT) >> 0x08); + /* Get the interrupt position */ + itmask = USART_IT & IT_MASK; + itmask = (uint32_t)0x01 << itmask; + + if (usartreg == 0x01) /* The IT is in CR1 register */ + { + itmask &= USARTx->CR1; + } + else if (usartreg == 0x02) /* The IT is in CR2 register */ + { + itmask &= USARTx->CR2; + } + else /* The IT is in CR3 register */ + { + itmask &= USARTx->CR3; + } + + bitpos = USART_IT >> 0x10; + bitpos = (uint32_t)0x01 << bitpos; + bitpos &= USARTx->ISR; + if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** + * @brief Clears the USARTx's interrupt pending bits. + * @param USARTx: where x can be 1 or 2 to select the USART peripheral. + * @param USART_IT: specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg USART_IT_WU: Wake up interrupt. + * @arg USART_IT_CM: Character match interrupt. + * @arg USART_IT_EOB: End of block interrupt. + * @arg USART_IT_RTO: Receive time out interrupt. + * @arg USART_IT_CTS: CTS change interrupt. + * @arg USART_IT_LBD: LIN Break detection interrupt. + * @arg USART_IT_TC: Transmission complete interrupt. + * @arg USART_IT_IDLE: IDLE line detected interrupt. + * @arg USART_IT_ORE: OverRun Error interrupt. + * @arg USART_IT_NE: Noise Error interrupt. + * @arg USART_IT_FE: Framing Error interrupt. + * @arg USART_IT_PE: Parity Error interrupt. + * + * @note RXNE pending bit is cleared by a read to the USART_RDR register + * (USART_ReceiveData()) or by writing 1 to the RXFRQ in the register + * USART_RQR (USART_RequestCmd()). + * @note TC pending bit can be also cleared by software sequence: a read + * operation to USART_SR register (USART_GetITStatus()) followed by + * a write operation to USART_TDR register (USART_SendData()). + * @note TXE pending bit is cleared by a write to the USART_TDR register + * (USART_SendData()) or by writing 1 to the TXFRQ in the register + * USART_RQR (USART_RequestCmd()). + * @retval None + */ +void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT) +{ + uint32_t bitpos = 0, itmask = 0; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_IT(USART_IT)); + + bitpos = USART_IT >> 0x10; + itmask = ((uint32_t)0x01 << (uint32_t)bitpos); + USARTx->ICR = (uint32_t)itmask; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_wwdg.c b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_wwdg.c new file mode 100644 index 0000000..4788d58 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/STM32F03x_FWLib/src/stm32f0xx_wwdg.c @@ -0,0 +1,303 @@ +/** + ****************************************************************************** + * @file stm32f0xx_wwdg.c + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file provides firmware functions to manage the following + * functionalities of the Window watchdog (WWDG) peripheral: + * + Prescaler, Refresh window and Counter configuration + * + WWDG activation + * + Interrupts and flags management + * + * @verbatim + * + ============================================================================== + ##### WWDG features ##### + ============================================================================== + [..] Once enabled the WWDG generates a system reset on expiry of a programmed + time period, unless the program refreshes the counter (downcounter) + before to reach 0x3F value (i.e. a reset is generated when the counter + value rolls over from 0x40 to 0x3F). + [..] An MCU reset is also generated if the counter value is refreshed + before the counter has reached the refresh window value. This + implies that the counter must be refreshed in a limited window. + + [..] Once enabled the WWDG cannot be disabled except by a system reset. + + [..] WWDGRST flag in RCC_CSR register can be used to inform when a WWDG + reset occurs. + + [..] The WWDG counter input clock is derived from the APB clock divided + by a programmable prescaler. + + [..] WWDG counter clock = PCLK1 / Prescaler. + [..] WWDG timeout = (WWDG counter clock) * (counter value). + + [..] Min-max timeout value @32MHz (PCLK1): ~85us / ~43ms. + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) + function. + + (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function. + + (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function. + + (#) Set the WWDG counter value and start it using WWDG_Enable() function. + When the WWDG is enabled the counter value should be configured to + a value greater than 0x40 to prevent generating an immediate reset. + + (#) Optionally you can enable the Early wakeup interrupt which is + generated when the counter reach 0x40. + Once enabled this interrupt cannot be disabled except by a system reset. + + (#) Then the application program must refresh the WWDG counter at regular + intervals during normal operation to prevent an MCU reset, using + WWDG_SetCounter() function. This operation must occur only when + the counter value is lower than the refresh window value, + programmed using WWDG_SetWindowValue(). + + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_wwdg.h" +#include "stm32f0xx_rcc.h" + +/** @addtogroup STM32F0xx_StdPeriph_Driver + * @{ + */ + +/** @defgroup WWDG + * @brief WWDG driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* --------------------- WWDG registers bit mask ---------------------------- */ +/* CFR register bit mask */ +#define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F) +#define CFR_W_MASK ((uint32_t)0xFFFFFF80) +#define BIT_MASK ((uint8_t)0x7F) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup WWDG_Private_Functions + * @{ + */ + +/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions + * @brief Prescaler, Refresh window and Counter configuration functions + * +@verbatim + ============================================================================== + ##### Prescaler, Refresh window and Counter configuration functions ##### + ============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the WWDG peripheral registers to their default reset values. + * @param None + * @retval None + */ +void WWDG_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); +} + +/** + * @brief Sets the WWDG Prescaler. + * @param WWDG_Prescaler: specifies the WWDG Prescaler. + * This parameter can be one of the following values: + * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 + * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 + * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 + * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 + * @retval None + */ +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); + /* Clear WDGTB[1:0] bits */ + tmpreg = WWDG->CFR & CFR_WDGTB_MASK; + /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ + tmpreg |= WWDG_Prescaler; + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/** + * @brief Sets the WWDG window value. + * @param WindowValue: specifies the window value to be compared to the downcounter. + * This parameter value must be lower than 0x80. + * @retval None + */ +void WWDG_SetWindowValue(uint8_t WindowValue) +{ + __IO uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); + /* Clear W[6:0] bits */ + + tmpreg = WWDG->CFR & CFR_W_MASK; + + /* Set W[6:0] bits according to WindowValue value */ + tmpreg |= WindowValue & (uint32_t) BIT_MASK; + + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/** + * @brief Enables the WWDG Early Wakeup interrupt(EWI). + * @note Once enabled this interrupt cannot be disabled except by a system reset. + * @param None + * @retval None + */ +void WWDG_EnableIT(void) +{ + WWDG->CFR |= WWDG_CFR_EWI; +} + +/** + * @brief Sets the WWDG counter value. + * @param Counter: specifies the watchdog counter value. + * This parameter must be a number between 0x40 and 0x7F (to prevent generating + * an immediate reset). + * @retval None + */ +void WWDG_SetCounter(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_COUNTER(Counter)); + /* Write to T[6:0] bits to configure the counter value, no need to do + a read-modify-write; writing a 0 to WDGA bit does nothing */ + WWDG->CR = Counter & BIT_MASK; +} + +/** + * @} + */ + +/** @defgroup WWDG_Group2 WWDG activation functions + * @brief WWDG activation functions + * +@verbatim + ============================================================================== + ##### WWDG activation function ##### + ============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables WWDG and load the counter value. + * @param Counter: specifies the watchdog counter value. + * This parameter must be a number between 0x40 and 0x7F (to prevent generating + * an immediate reset). + * @retval None + */ +void WWDG_Enable(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_COUNTER(Counter)); + WWDG->CR = WWDG_CR_WDGA | Counter; +} + +/** + * @} + */ + +/** @defgroup WWDG_Group3 Interrupts and flags management functions + * @brief Interrupts and flags management functions + * +@verbatim + ============================================================================== + ##### Interrupts and flags management functions ##### + ============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Checks whether the Early Wakeup interrupt flag is set or not. + * @param None + * @retval The new state of the Early Wakeup interrupt flag (SET or RESET). + */ +FlagStatus WWDG_GetFlagStatus(void) +{ + FlagStatus bitstatus = RESET; + + if ((WWDG->SR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears Early Wakeup interrupt flag. + * @param None + * @retval None + */ +void WWDG_ClearFlag(void) +{ + WWDG->SR = (uint32_t)RESET; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/SYSTEM/delay.c b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/SYSTEM/delay.c new file mode 100644 index 0000000..2347b36 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/SYSTEM/delay.c @@ -0,0 +1,49 @@ +#include "delay.h" + + +static int8_t fac_us=0;//us +static int16_t fac_ms=0;//ms + +void delay_init() +{ + SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);//ѡⲿʱ HCLK/8 + fac_us=SystemCoreClock/8000000; //Ϊϵͳʱӵ1/8 + fac_ms=(int16_t)fac_us*1000;//ÿmsҪsystickʱ +} +//ʱNus +void delay_us(int32_t nus) +{ + int32_t temp; + SysTick->LOAD=nus*fac_us; //ʱ + SysTick->VAL=0x00; //ռ + SysTick->CTRL|=SysTick_CTRL_ENABLE_Msk ; //ʼ + do + { + temp=SysTick->CTRL; + } + while(temp&0x01&&!(temp&(1<<16)));//ȴʱ䵽 + SysTick->CTRL&=~SysTick_CTRL_ENABLE_Msk; //رռ + SysTick->VAL =0X00; //ռ +} +//ʱNms +//ʱnms +//עnmsķΧ +//SysTick->LOADΪ24λĴ,,ʱΪ: +//nms<=0xffffff*8*1000/SYSCLK +//SYSCLKλΪHz,nmsλΪms +//72M,nms<=1864 + +void delay_ms(int16_t nms) +{ + int32_t temp; + SysTick->LOAD=(int32_t)nms*fac_ms;//ʱ(SysTick->LOADΪ24bit) + SysTick->VAL =0x00; //ռ + SysTick->CTRL|=SysTick_CTRL_ENABLE_Msk ; //ʼ + do + { + temp=SysTick->CTRL; + } + while(temp&0x01&&!(temp&(1<<16)));//ȴʱ䵽 + SysTick->CTRL&=~SysTick_CTRL_ENABLE_Msk; //رռ + SysTick->VAL =0X00; //ռ +} diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/SYSTEM/delay.h b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/SYSTEM/delay.h new file mode 100644 index 0000000..0b44801 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/SYSTEM/delay.h @@ -0,0 +1,8 @@ +#ifndef _DELAY_H_ +#define _DELAY_H_ + +#include "stm32f0xx.h" +void delay_init(void); +void delay_us(int32_t nus); +void delay_ms(int16_t nms); +#endif diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/DebugConfig/Stm32f030demo_STM32F030F4.dbgconf b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/DebugConfig/Stm32f030demo_STM32F030F4.dbgconf new file mode 100644 index 0000000..5074c41 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/DebugConfig/Stm32f030demo_STM32F030F4.dbgconf @@ -0,0 +1,37 @@ +// File: STM32F030_070.dbgconf +// Version: 1.0.0 +// Note: refer to STM32F030x4/x6/x8/xC, STM32F070x6/xB Reference manual (RM0360) +// refer to STM32F030x4 STM32F030x6, STM32F030x8 STM32F030xC datasheet +// STM32F070CB STM32F070RB, STM32F070C6 STM32F070F6 datasheet + +// <<< Use Configuration Wizard in Context Menu >>> + +// Debug MCU configuration register (DBGMCU_CR) +// DBG_STANDBY Debug standby mode +// DBG_STOP Debug stop mode +// +DbgMCU_CR = 0x00000006; + +// Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) +// Reserved bits must be kept at reset value +// DBG_I2C1_TIMEOUT I2C1 SMBUS timeout mode stopped when core is halted +// DBG_IWDG_STOP Independent watchdog stopped when core is halted +// DBG_WWDG_STOP Window watchdog stopped when core is halted +// DBG_RTC_STOP RTC stopped when core is halted +// DBG_TIM14_STOP TIM14 counter stopped when core is halted +// DBG_TIM7_STOP TIM7 counter stopped when core is halted +// DBG_TIM6_STOP TIM6 counter stopped when core is halted +// DBG_TIM3_STOP TIM3 counter stopped when core is halted +// +DbgMCU_APB1_Fz = 0x00000000; + +// Debug MCU APB2 freeze register (DBGMCU_APB2_FZ) +// Reserved bits must be kept at reset value +// DBG_TIM17_STOP TIM17 counter stopped when core is halted +// DBG_TIM16_STOP TIM16 counter stopped when core is halted +// DBG_TIM15_STOP TIM15 counter stopped when core is halted +// DBG_TIM1_STOP TIM1 counter stopped when core is halted +// +DbgMCU_APB2_Fz = 0x00000000; + +// <<< end of configuration section >>> diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/JLinkLog.txt b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/JLinkLog.txt new file mode 100644 index 0000000..435c8d6 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/JLinkLog.txt @@ -0,0 +1,734 @@ + +T1E3C 000:451 SEGGER J-Link V4.80g Log File (0001ms, 0272ms total) +T1E3C 000:451 DLL Compiled: Feb 13 2014 20:50:02 (0001ms, 0272ms total) +T1E3C 000:451 Logging started @ 2014-05-10 12:35 (0001ms, 0272ms total) +T1E3C 000:452 JLINK_SetWarnOutHandler(...) (0000ms, 0272ms total) +T1E3C 000:452 JLINK_OpenEx(...) +Firmware: J-Link ARM V8 compiled Nov 25 2013 19:20:08 +Hardware: V8.00 +S/N: 58009527 +Feature(s): RDI,FlashDL,FlashBP,JFlash,GDBFULL returns O.K. (0270ms, 0542ms total) +T1E3C 000:722 JLINK_SetErrorOutHandler(...) (0000ms, 0542ms total) +T1E3C 000:722 JLINK_ExecCommand("ProjectFile = "C:\Documents and Settings\Administrator\\STM32F030F4P6ϰ\STM32F030\User\JLinkSettings.ini"", ...) returns 0x00 (0001ms, 0543ms total) +T1E3C 000:727 JLINK_ExecCommand("Device = STM32F030F4", ...)Device "STM32F030F4" selected (16 KB flash, 4 KB RAM). returns 0x00 (0003ms, 0546ms total) +T1E3C 000:730 JLINK_ExecCommand("DisableConnectionTimeout", ...) returns 0x01 (0000ms, 0546ms total) +T1E3C 000:730 JLINK_GetHardwareVersion() returns 0x13880 (0000ms, 0546ms total) +T1E3C 000:730 JLINK_GetDLLVersion() returns 48007 (0000ms, 0546ms total) +T1E3C 000:730 JLINK_GetFirmwareString(...) (0000ms, 0546ms total) +T1E3C 000:740 JLINK_GetDLLVersion() returns 48007 (0000ms, 0546ms total) +T1E3C 000:740 JLINK_GetCompileDateTime() (0000ms, 0546ms total) +T1E3C 000:743 JLINK_GetFirmwareString(...) (0000ms, 0546ms total) +T1E3C 000:746 JLINK_GetHardwareVersion() returns 0x13880 (0000ms, 0546ms total) +T1E3C 000:753 JLINK_TIF_Select(JLINKARM_TIF_SWD) returns 0x00 (0004ms, 0550ms total) +T1E3C 000:757 JLINK_SetSpeed(50) (0001ms, 0551ms total) +T1E3C 000:758 JLINK_GetId() >0x108 TIF>Found SWD-DP with ID 0x0BB11477 >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x108 TIF>Found SWD-DP with ID 0x0BB11477 + >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF>Found Cortex-M0 r0p0, Little endian. + -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE0002000)FPUnit: 4 code (BP) slots and 0 literal slots -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0001000) -- CPU_ReadMem(4 bytes @ 0xE00FF018) -- CPU_WriteMem(4096 bytes @ 0x20000000) >0x0D TIF> >0x21 TIF> returns 0x0BB11477 (0354ms, 0905ms total) +T1E3C 001:112 JLINK_GetDeviceFamily() returns 6 (0000ms, 0905ms total) +T1E3C 001:114 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) -- Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0011ms, 0916ms total) +T1E3C 001:125 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) -- Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0013ms, 0929ms total) +T1E3C 001:139 JLINK_ReadMem (0xE00FF000, 0x0018 Bytes, ...) -- CPU_ReadMem(24 bytes @ 0xE00FF000) -- Data: 03 F0 F0 FF 03 20 F0 FF 03 30 F0 FF 00 00 00 00 ... returns 0x00 (0011ms, 0940ms total) +T1E3C 001:150 JLINK_ReadMemU32(0xE000ED00, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000ED00) -- Data: 00 C2 0C 41 returns 0x01 (0007ms, 0947ms total) +T1E3C 001:157 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 0947ms total) +T1E3C 001:157 JLINK_Reset() -- CPU_ReadMem(4 bytes @ 0x20000000) -- CPU_WriteMem(4 bytes @ 0x20000000) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) >0x35 TIF> -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) + -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0001000) (0177ms, 1124ms total) +T1E3C 001:334 JLINK_Halt() returns 0x00 (0000ms, 1124ms total) +T1E3C 001:334 JLINK_IsHalted() returns TRUE (0001ms, 1125ms total) +T1E3C 001:335 JLINK_ReadMemU32(0xE000EDF0, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- Data: 03 00 03 00 returns 0x01 (0007ms, 1131ms total) +T1E3C 001:342 JLINK_WriteU32(0xE000EDF0, 0xA05F0003) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) returns 0x00 (0008ms, 1139ms total) +T1E3C 001:350 JLINK_WriteU32(0xE000EDFC, 0x01000000) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x00 (0007ms, 1146ms total) +T1E3C 001:371 JLINK_GetHWStatus(...) returns 0x00 (0002ms, 1148ms total) +T1E3C 001:382 JLINK_GetNumBPUnits(Type = 0xFFFFFF00) returns 0x04 (0000ms, 1148ms total) +T1E3C 001:382 JLINK_GetNumBPUnits(Type = 0xF0) returns 0x2000 (0000ms, 1148ms total) +T1E3C 001:382 JLINK_GetNumWPUnits() returns 0x02 (0000ms, 1148ms total) +T1E3C 001:389 JLINK_GetSpeed() returns 0x32 (0000ms, 1148ms total) +T1E3C 001:391 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) -- Data: 00 00 00 00 returns 0x01 (0009ms, 1157ms total) +T1E3C 001:400 JLINK_Halt() returns 0x00 (0000ms, 1157ms total) +T1E3C 001:400 JLINK_IsHalted() returns TRUE (0000ms, 1157ms total) +T1E3C 001:403 JLINK_WriteMem(0x20000000, 0x0170 Bytes, ...) -- Data: 00 BE 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... -- CPU_WriteMem(368 bytes @ 0x20000000) returns 0x170 (0096ms, 1253ms total) +T1E3C 001:499 JLINK_WriteReg(R0, 0x08000000) returns 0x00 (0000ms, 1253ms total) +T1E3C 001:499 JLINK_WriteReg(R1, 0x02DC6C00) returns 0x00 (0000ms, 1253ms total) +T1E3C 001:499 JLINK_WriteReg(R2, 0x00000001) returns 0x00 (0000ms, 1253ms total) +T1E3C 001:499 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1253ms total) +T1E3C 001:499 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1253ms total) +T1E3C 001:499 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1253ms total) +T1E3C 001:500 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1253ms total) +T1E3C 001:500 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1253ms total) +T1E3C 001:500 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1253ms total) +T1E3C 001:500 JLINK_WriteReg(R9, 0x2000016C) returns 0x00 (0000ms, 1253ms total) +T1E3C 001:500 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1253ms total) +T1E3C 001:500 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1253ms total) +T1E3C 001:500 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1253ms total) +T1E3C 001:500 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 1253ms total) +T1E3C 001:500 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 1253ms total) +T1E3C 001:500 JLINK_WriteReg(R15 (PC), 0x20000038) returns 0x00 (0000ms, 1253ms total) +T1E3C 001:500 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1253ms total) +T1E3C 001:500 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 1253ms total) +T1E3C 001:500 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 1253ms total) +T1E3C 001:500 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1253ms total) +T1E3C 001:500 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) -- CPU_ReadMem(2 bytes @ 0x20000000) returns 0x00000001 (0007ms, 1260ms total) +T1E3C 001:507 JLINK_Go() -- CPU_WriteMem(2 bytes @ 0x20000000) -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0001004) (0093ms, 1353ms total) +T1E3C 001:600 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0074ms, 1427ms total) +T1E3C 001:674 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 1353ms total) +T1E3C 001:674 JLINK_ClrBPEx(BPHandle = 0x00000001) returns 0x00 (0000ms, 1353ms total) +T1E3C 001:674 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1353ms total) +T1E3C 001:675 JLINK_WriteReg(R0, 0x08000000) returns 0x00 (0000ms, 1353ms total) +T1E3C 001:675 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 1353ms total) +T1E3C 001:675 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 1353ms total) +T1E3C 001:675 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1353ms total) +T1E3C 001:675 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1353ms total) +T1E3C 001:675 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1353ms total) +T1E3C 001:675 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1353ms total) +T1E3C 001:675 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1353ms total) +T1E3C 001:675 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1353ms total) +T1E3C 001:675 JLINK_WriteReg(R9, 0x2000016C) returns 0x00 (0000ms, 1353ms total) +T1E3C 001:675 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1353ms total) +T1E3C 001:675 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1353ms total) +T1E3C 001:675 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1353ms total) +T1E3C 001:675 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 1353ms total) +T1E3C 001:675 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 1353ms total) +T1E3C 001:675 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 1353ms total) +T1E3C 001:675 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1353ms total) +T1E3C 001:675 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 1353ms total) +T1E3C 001:675 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 1353ms total) +T1E3C 001:675 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1353ms total) +T1E3C 001:675 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000002 (0000ms, 1353ms total) +T1E3C 001:675 JLINK_Go() (0026ms, 1379ms total) +T1E3C 001:701 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0073ms, 1452ms total) +T1E3C 001:775 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 1379ms total) +T1E3C 001:775 JLINK_ClrBPEx(BPHandle = 0x00000002) returns 0x00 (0000ms, 1379ms total) +T1E3C 001:775 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 1379ms total) +T1E3C 001:775 JLINK_WriteReg(R0, 0x08000000) returns 0x00 (0000ms, 1379ms total) +T1E3C 001:775 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 1379ms total) +T1E3C 001:775 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 1379ms total) +T1E3C 001:775 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1379ms total) +T1E3C 001:775 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1379ms total) +T1E3C 001:775 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1379ms total) +T1E3C 001:775 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1379ms total) +T1E3C 001:775 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1379ms total) +T1E3C 001:775 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1379ms total) +T1E3C 001:775 JLINK_WriteReg(R9, 0x2000016C) returns 0x00 (0000ms, 1379ms total) +T1E3C 001:775 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1379ms total) +T1E3C 001:775 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1379ms total) +T1E3C 001:775 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1379ms total) +T1E3C 001:775 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 1379ms total) +T1E3C 001:775 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 1379ms total) +T1E3C 001:775 JLINK_WriteReg(R15 (PC), 0x200000B8) returns 0x00 (0000ms, 1379ms total) +T1E3C 001:775 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1379ms total) +T1E3C 001:775 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 1379ms total) +T1E3C 001:775 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 1379ms total) +T1E3C 001:775 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1379ms total) +T1E3C 001:775 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000003 (0000ms, 1379ms total) +T1E3C 001:775 JLINK_Go() (0025ms, 1404ms total) +T1E3C 001:800 JLINK_IsHalted() returns FALSE (0007ms, 1411ms total) +T1E3C 001:843 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0072ms, 1476ms total) +T1E3C 001:915 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 1404ms total) +T1E3C 001:915 JLINK_ClrBPEx(BPHandle = 0x00000003) returns 0x00 (0000ms, 1404ms total) +T1E3C 001:915 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1404ms total) +T1E3C 001:916 JLINK_WriteReg(R0, 0x08000400) returns 0x00 (0000ms, 1404ms total) +T1E3C 001:916 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 1404ms total) +T1E3C 001:916 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 1404ms total) +T1E3C 001:916 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1404ms total) +T1E3C 001:916 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1404ms total) +T1E3C 001:916 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1404ms total) +T1E3C 001:916 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1404ms total) +T1E3C 001:916 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1404ms total) +T1E3C 001:916 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1404ms total) +T1E3C 001:916 JLINK_WriteReg(R9, 0x2000016C) returns 0x00 (0000ms, 1404ms total) +T1E3C 001:916 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1404ms total) +T1E3C 001:916 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1404ms total) +T1E3C 001:916 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1404ms total) +T1E3C 001:916 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 1404ms total) +T1E3C 001:916 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 1404ms total) +T1E3C 001:916 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 1404ms total) +T1E3C 001:916 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1404ms total) +T1E3C 001:916 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 1404ms total) +T1E3C 001:916 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 1404ms total) +T1E3C 001:916 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1404ms total) +T1E3C 001:916 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000004 (0000ms, 1404ms total) +T1E3C 001:916 JLINK_Go() (0028ms, 1432ms total) +T1E3C 001:944 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0073ms, 1505ms total) +T1E3C 002:017 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 1432ms total) +T1E3C 002:017 JLINK_ClrBPEx(BPHandle = 0x00000004) returns 0x00 (0000ms, 1432ms total) +T1E3C 002:017 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 1432ms total) +T1E3C 002:017 JLINK_WriteReg(R0, 0x08000400) returns 0x00 (0000ms, 1432ms total) +T1E3C 002:017 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 1432ms total) +T1E3C 002:017 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 1432ms total) +T1E3C 002:017 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1432ms total) +T1E3C 002:017 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1432ms total) +T1E3C 002:017 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1432ms total) +T1E3C 002:017 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1432ms total) +T1E3C 002:017 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1432ms total) +T1E3C 002:017 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1432ms total) +T1E3C 002:017 JLINK_WriteReg(R9, 0x2000016C) returns 0x00 (0000ms, 1432ms total) +T1E3C 002:017 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1432ms total) +T1E3C 002:017 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1432ms total) +T1E3C 002:017 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1432ms total) +T1E3C 002:017 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 1432ms total) +T1E3C 002:017 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 1432ms total) +T1E3C 002:017 JLINK_WriteReg(R15 (PC), 0x200000B8) returns 0x00 (0000ms, 1432ms total) +T1E3C 002:017 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1432ms total) +T1E3C 002:017 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 1432ms total) +T1E3C 002:017 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 1432ms total) +T1E3C 002:017 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1432ms total) +T1E3C 002:017 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000005 (0000ms, 1432ms total) +T1E3C 002:017 JLINK_Go() (0023ms, 1455ms total) +T1E3C 002:040 JLINK_IsHalted() returns FALSE (0007ms, 1462ms total) +T1E3C 002:060 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0073ms, 1528ms total) +T1E3C 002:133 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0001ms, 1456ms total) +T1E3C 002:134 JLINK_ClrBPEx(BPHandle = 0x00000005) returns 0x00 (0000ms, 1456ms total) +T1E3C 002:134 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1456ms total) +T1E3C 002:135 JLINK_WriteReg(R0, 0x08000800) returns 0x00 (0000ms, 1456ms total) +T1E3C 002:135 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 1456ms total) +T1E3C 002:135 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 1456ms total) +T1E3C 002:135 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1456ms total) +T1E3C 002:135 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1456ms total) +T1E3C 002:135 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1456ms total) +T1E3C 002:135 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1456ms total) +T1E3C 002:135 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1456ms total) +T1E3C 002:135 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1456ms total) +T1E3C 002:135 JLINK_WriteReg(R9, 0x2000016C) returns 0x00 (0000ms, 1456ms total) +T1E3C 002:135 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0001ms, 1457ms total) +T1E3C 002:136 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1457ms total) +T1E3C 002:136 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1457ms total) +T1E3C 002:136 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 1457ms total) +T1E3C 002:136 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 1457ms total) +T1E3C 002:136 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 1457ms total) +T1E3C 002:136 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1457ms total) +T1E3C 002:136 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 1457ms total) +T1E3C 002:136 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 1457ms total) +T1E3C 002:136 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1457ms total) +T1E3C 002:136 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000006 (0000ms, 1457ms total) +T1E3C 002:136 JLINK_Go() (0028ms, 1485ms total) +T1E3C 002:164 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0074ms, 1559ms total) +T1E3C 002:238 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 1485ms total) +T1E3C 002:238 JLINK_ClrBPEx(BPHandle = 0x00000006) returns 0x00 (0000ms, 1485ms total) +T1E3C 002:238 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 1485ms total) +T1E3C 002:238 JLINK_WriteReg(R0, 0x08000800) returns 0x00 (0000ms, 1485ms total) +T1E3C 002:238 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 1485ms total) +T1E3C 002:238 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 1485ms total) +T1E3C 002:238 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1485ms total) +T1E3C 002:238 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1485ms total) +T1E3C 002:238 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1485ms total) +T1E3C 002:238 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1485ms total) +T1E3C 002:238 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1485ms total) +T1E3C 002:238 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1485ms total) +T1E3C 002:238 JLINK_WriteReg(R9, 0x2000016C) returns 0x00 (0000ms, 1485ms total) +T1E3C 002:238 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1485ms total) +T1E3C 002:238 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1485ms total) +T1E3C 002:238 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1485ms total) +T1E3C 002:238 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 1485ms total) +T1E3C 002:238 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 1485ms total) +T1E3C 002:238 JLINK_WriteReg(R15 (PC), 0x200000B8) returns 0x00 (0000ms, 1485ms total) +T1E3C 002:238 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1485ms total) +T1E3C 002:238 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 1485ms total) +T1E3C 002:238 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 1485ms total) +T1E3C 002:238 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1485ms total) +T1E3C 002:238 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000007 (0000ms, 1485ms total) +T1E3C 002:238 JLINK_Go() (0025ms, 1510ms total) +T1E3C 002:263 JLINK_IsHalted() returns FALSE (0007ms, 1517ms total) +T1E3C 002:281 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0073ms, 1583ms total) +T1E3C 002:354 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 1510ms total) +T1E3C 002:354 JLINK_ClrBPEx(BPHandle = 0x00000007) returns 0x00 (0000ms, 1510ms total) +T1E3C 002:354 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1510ms total) +T1E3C 002:354 JLINK_WriteReg(R0, 0x08000C00) returns 0x00 (0000ms, 1510ms total) +T1E3C 002:354 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 1510ms total) +T1E3C 002:354 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 1510ms total) +T1E3C 002:354 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1510ms total) +T1E3C 002:354 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1510ms total) +T1E3C 002:354 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1510ms total) +T1E3C 002:354 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1510ms total) +T1E3C 002:354 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1510ms total) +T1E3C 002:354 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1510ms total) +T1E3C 002:354 JLINK_WriteReg(R9, 0x2000016C) returns 0x00 (0000ms, 1510ms total) +T1E3C 002:354 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1510ms total) +T1E3C 002:354 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1510ms total) +T1E3C 002:354 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1510ms total) +T1E3C 002:354 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 1510ms total) +T1E3C 002:354 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 1510ms total) +T1E3C 002:354 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 1510ms total) +T1E3C 002:354 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1510ms total) +T1E3C 002:354 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0001ms, 1511ms total) +T1E3C 002:355 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 1511ms total) +T1E3C 002:355 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1511ms total) +T1E3C 002:355 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000008 (0000ms, 1511ms total) +T1E3C 002:355 JLINK_Go() (0028ms, 1539ms total) +T1E3C 002:383 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0073ms, 1612ms total) +T1E3C 002:456 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 1539ms total) +T1E3C 002:456 JLINK_ClrBPEx(BPHandle = 0x00000008) returns 0x00 (0000ms, 1539ms total) +T1E3C 002:456 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 1539ms total) +T1E3C 002:456 JLINK_WriteReg(R0, 0x08000C00) returns 0x00 (0000ms, 1539ms total) +T1E3C 002:456 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 1539ms total) +T1E3C 002:456 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 1539ms total) +T1E3C 002:456 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1539ms total) +T1E3C 002:456 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1539ms total) +T1E3C 002:456 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1539ms total) +T1E3C 002:456 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1539ms total) +T1E3C 002:456 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1539ms total) +T1E3C 002:456 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1539ms total) +T1E3C 002:456 JLINK_WriteReg(R9, 0x2000016C) returns 0x00 (0000ms, 1539ms total) +T1E3C 002:456 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1539ms total) +T1E3C 002:456 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1539ms total) +T1E3C 002:456 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1539ms total) +T1E3C 002:456 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 1539ms total) +T1E3C 002:456 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 1539ms total) +T1E3C 002:456 JLINK_WriteReg(R15 (PC), 0x200000B8) returns 0x00 (0000ms, 1539ms total) +T1E3C 002:456 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1539ms total) +T1E3C 002:457 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 1540ms total) +T1E3C 002:457 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 1540ms total) +T1E3C 002:457 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1540ms total) +T1E3C 002:457 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000009 (0000ms, 1540ms total) +T1E3C 002:457 JLINK_Go() (0024ms, 1564ms total) +T1E3C 002:481 JLINK_IsHalted() returns FALSE (0007ms, 1571ms total) +T1E3C 002:497 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0072ms, 1636ms total) +T1E3C 002:569 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 1564ms total) +T1E3C 002:569 JLINK_ClrBPEx(BPHandle = 0x00000009) returns 0x00 (0000ms, 1564ms total) +T1E3C 002:569 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1564ms total) +T1E3C 002:569 JLINK_WriteReg(R0, 0x08001000) returns 0x00 (0000ms, 1564ms total) +T1E3C 002:569 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 1564ms total) +T1E3C 002:569 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 1564ms total) +T1E3C 002:569 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1564ms total) +T1E3C 002:569 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1564ms total) +T1E3C 002:569 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1564ms total) +T1E3C 002:569 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1564ms total) +T1E3C 002:569 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1564ms total) +T1E3C 002:569 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1564ms total) +T1E3C 002:569 JLINK_WriteReg(R9, 0x2000016C) returns 0x00 (0000ms, 1564ms total) +T1E3C 002:569 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1564ms total) +T1E3C 002:569 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1564ms total) +T1E3C 002:569 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1564ms total) +T1E3C 002:570 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 1565ms total) +T1E3C 002:570 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 1565ms total) +T1E3C 002:570 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 1565ms total) +T1E3C 002:570 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1565ms total) +T1E3C 002:570 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 1565ms total) +T1E3C 002:570 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 1565ms total) +T1E3C 002:570 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1565ms total) +T1E3C 002:570 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000000A (0000ms, 1565ms total) +T1E3C 002:570 JLINK_Go() (0028ms, 1593ms total) +T1E3C 002:598 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0073ms, 1666ms total) +T1E3C 002:671 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 1593ms total) +T1E3C 002:671 JLINK_ClrBPEx(BPHandle = 0x0000000A) returns 0x00 (0000ms, 1593ms total) +T1E3C 002:671 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 1593ms total) +T1E3C 002:671 JLINK_WriteReg(R0, 0x08001000) returns 0x00 (0000ms, 1593ms total) +T1E3C 002:671 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 1593ms total) +T1E3C 002:671 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 1593ms total) +T1E3C 002:671 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1593ms total) +T1E3C 002:671 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1593ms total) +T1E3C 002:671 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1593ms total) +T1E3C 002:671 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1593ms total) +T1E3C 002:671 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1593ms total) +T1E3C 002:671 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1593ms total) +T1E3C 002:671 JLINK_WriteReg(R9, 0x2000016C) returns 0x00 (0000ms, 1593ms total) +T1E3C 002:672 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1594ms total) +T1E3C 002:672 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1594ms total) +T1E3C 002:672 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1594ms total) +T1E3C 002:672 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 1594ms total) +T1E3C 002:672 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 1594ms total) +T1E3C 002:672 JLINK_WriteReg(R15 (PC), 0x200000B8) returns 0x00 (0000ms, 1594ms total) +T1E3C 002:672 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1594ms total) +T1E3C 002:672 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 1594ms total) +T1E3C 002:672 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 1594ms total) +T1E3C 002:672 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1594ms total) +T1E3C 002:672 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000000B (0000ms, 1594ms total) +T1E3C 002:672 JLINK_Go() (0024ms, 1618ms total) +T1E3C 002:696 JLINK_IsHalted() returns FALSE (0007ms, 1625ms total) +T1E3C 002:713 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0072ms, 1690ms total) +T1E3C 002:785 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 1618ms total) +T1E3C 002:785 JLINK_ClrBPEx(BPHandle = 0x0000000B) returns 0x00 (0000ms, 1618ms total) +T1E3C 002:785 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1618ms total) +T1E3C 002:785 JLINK_WriteReg(R0, 0x08001400) returns 0x00 (0000ms, 1618ms total) +T1E3C 002:785 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 1618ms total) +T1E3C 002:785 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 1618ms total) +T1E3C 002:785 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1618ms total) +T1E3C 002:785 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0001ms, 1619ms total) +T1E3C 002:786 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1619ms total) +T1E3C 002:786 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1619ms total) +T1E3C 002:786 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1619ms total) +T1E3C 002:786 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1619ms total) +T1E3C 002:786 JLINK_WriteReg(R9, 0x2000016C) returns 0x00 (0000ms, 1619ms total) +T1E3C 002:786 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1619ms total) +T1E3C 002:786 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1619ms total) +T1E3C 002:786 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1619ms total) +T1E3C 002:786 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 1619ms total) +T1E3C 002:786 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 1619ms total) +T1E3C 002:786 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 1619ms total) +T1E3C 002:786 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1619ms total) +T1E3C 002:786 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 1619ms total) +T1E3C 002:786 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 1619ms total) +T1E3C 002:786 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1619ms total) +T1E3C 002:786 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000000C (0000ms, 1619ms total) +T1E3C 002:786 JLINK_Go() (0028ms, 1647ms total) +T1E3C 002:814 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0073ms, 1720ms total) +T1E3C 002:888 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 1647ms total) +T1E3C 002:888 JLINK_ClrBPEx(BPHandle = 0x0000000C) returns 0x00 (0000ms, 1647ms total) +T1E3C 002:888 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 1647ms total) +T1E3C 002:888 JLINK_WriteReg(R0, 0x08001400) returns 0x00 (0000ms, 1647ms total) +T1E3C 002:888 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0001ms, 1648ms total) +T1E3C 002:889 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 1648ms total) +T1E3C 002:889 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1648ms total) +T1E3C 002:889 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1648ms total) +T1E3C 002:889 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1648ms total) +T1E3C 002:889 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1648ms total) +T1E3C 002:889 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1648ms total) +T1E3C 002:889 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1648ms total) +T1E3C 002:889 JLINK_WriteReg(R9, 0x2000016C) returns 0x00 (0000ms, 1648ms total) +T1E3C 002:889 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1648ms total) +T1E3C 002:889 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1648ms total) +T1E3C 002:889 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1648ms total) +T1E3C 002:889 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 1648ms total) +T1E3C 002:889 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 1648ms total) +T1E3C 002:889 JLINK_WriteReg(R15 (PC), 0x200000B8) returns 0x00 (0000ms, 1648ms total) +T1E3C 002:889 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1648ms total) +T1E3C 002:889 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 1648ms total) +T1E3C 002:889 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 1648ms total) +T1E3C 002:889 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1648ms total) +T1E3C 002:889 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000000D (0000ms, 1648ms total) +T1E3C 002:889 JLINK_Go() (0024ms, 1672ms total) +T1E3C 002:913 JLINK_IsHalted() returns FALSE (0007ms, 1679ms total) +T1E3C 002:929 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0072ms, 1744ms total) +T1E3C 003:001 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 1672ms total) +T1E3C 003:001 JLINK_ClrBPEx(BPHandle = 0x0000000D) returns 0x00 (0000ms, 1672ms total) +T1E3C 003:001 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1672ms total) +T1E3C 003:001 JLINK_WriteReg(R0, 0x00000001) returns 0x00 (0000ms, 1672ms total) +T1E3C 003:001 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0001ms, 1673ms total) +T1E3C 003:002 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 1673ms total) +T1E3C 003:002 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1673ms total) +T1E3C 003:002 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1673ms total) +T1E3C 003:002 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1673ms total) +T1E3C 003:002 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1673ms total) +T1E3C 003:002 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1673ms total) +T1E3C 003:002 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 1673ms total) +T1E3C 003:002 JLINK_WriteReg(R9, 0x2000016C) returns 0x00 (0000ms, 1673ms total) +T1E3C 003:002 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1673ms total) +T1E3C 003:002 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1673ms total) +T1E3C 003:002 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1673ms total) +T1E3C 003:002 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 1673ms total) +T1E3C 003:002 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 1673ms total) +T1E3C 003:002 JLINK_WriteReg(R15 (PC), 0x20000066) returns 0x00 (0000ms, 1673ms total) +T1E3C 003:002 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1673ms total) +T1E3C 003:002 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 1673ms total) +T1E3C 003:002 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 1673ms total) +T1E3C 003:002 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1673ms total) +T1E3C 003:002 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000000E (0000ms, 1673ms total) +T1E3C 003:002 JLINK_Go() (0028ms, 1701ms total) +T1E3C 003:031 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0073ms, 1774ms total) +T1E3C 003:104 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 1701ms total) +T1E3C 003:104 JLINK_ClrBPEx(BPHandle = 0x0000000E) returns 0x00 (0000ms, 1701ms total) +T1E3C 003:104 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1701ms total) +T1E3C 003:161 JLINK_WriteMem(0x20000000, 0x0170 Bytes, ...) -- Data: 00 BE 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... -- CPU_WriteMem(368 bytes @ 0x20000000) returns 0x170 (0097ms, 1798ms total) +T1E3C 003:258 JLINK_WriteReg(R0, 0x08000000) returns 0x00 (0000ms, 1798ms total) +T1E3C 003:258 JLINK_WriteReg(R1, 0x02DC6C00) returns 0x00 (0000ms, 1798ms total) +T1E3C 003:258 JLINK_WriteReg(R2, 0x00000002) returns 0x00 (0000ms, 1798ms total) +T1E3C 003:258 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 1798ms total) +T1E3C 003:258 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 1798ms total) +T1E3C 003:258 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 1798ms total) +T1E3C 003:258 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 1798ms total) +T1E3C 003:258 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 1798ms total) +T1E3C 003:258 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0001ms, 1799ms total) +T1E3C 003:259 JLINK_WriteReg(R9, 0x2000016C) returns 0x00 (0000ms, 1799ms total) +T1E3C 003:259 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 1799ms total) +T1E3C 003:259 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 1799ms total) +T1E3C 003:259 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 1799ms total) +T1E3C 003:259 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 1799ms total) +T1E3C 003:259 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 1799ms total) +T1E3C 003:259 JLINK_WriteReg(R15 (PC), 0x20000038) returns 0x00 (0000ms, 1799ms total) +T1E3C 003:259 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 1799ms total) +T1E3C 003:259 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 1799ms total) +T1E3C 003:259 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 1799ms total) +T1E3C 003:259 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 1799ms total) +T1E3C 003:259 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) -- CPU_ReadMem(2 bytes @ 0x20000000) returns 0x0000000F (0005ms, 1804ms total) +T1E3C 003:264 JLINK_Go() -- CPU_WriteMem(2 bytes @ 0x20000000) (0034ms, 1838ms total) +T1E3C 003:298 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0073ms, 1911ms total) +T1E3C 003:371 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 1838ms total) +T1E3C 003:371 JLINK_ClrBPEx(BPHandle = 0x0000000F) returns 0x00 (0000ms, 1838ms total) +T1E3C 003:371 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1838ms total) +T1E3C 003:371 JLINK_WriteMem(0x20000170, 0x0290 Bytes, ...) -- Data: 90 06 00 20 BD 03 00 08 B9 01 00 08 BB 01 00 08 ... -- CPU_WriteMem(656 bytes @ 0x20000170) returns 0x290 (0163ms, 2001ms total) +T1E3C 003:534 JLINK_WriteMem(0x20000400, 0x0170 Bytes, ...) -- Data: 0C BD 10 B5 41 48 00 68 01 21 08 43 3F 49 08 60 ... -- CPU_WriteMem(368 bytes @ 0x20000400) returns 0x170 (0096ms, 2097ms total) +T1E3C 003:630 JLINK_WriteReg(R0, 0x08000000) returns 0x00 (0000ms, 2097ms total) +T1E3C 003:630 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 2097ms total) +T1E3C 003:630 JLINK_WriteReg(R2, 0x20000170) returns 0x00 (0000ms, 2097ms total) +T1E3C 003:630 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 2097ms total) +T1E3C 003:630 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 2097ms total) +T1E3C 003:630 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 2097ms total) +T1E3C 003:630 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 2097ms total) +T1E3C 003:630 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 2097ms total) +T1E3C 003:630 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 2097ms total) +T1E3C 003:630 JLINK_WriteReg(R9, 0x2000016C) returns 0x00 (0000ms, 2097ms total) +T1E3C 003:630 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 2097ms total) +T1E3C 003:630 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 2097ms total) +T1E3C 003:630 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 2097ms total) +T1E3C 003:630 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0001ms, 2098ms total) +T1E3C 003:631 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 2098ms total) +T1E3C 003:631 JLINK_WriteReg(R15 (PC), 0x200000FA) returns 0x00 (0000ms, 2098ms total) +T1E3C 003:631 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 2098ms total) +T1E3C 003:631 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 2098ms total) +T1E3C 003:631 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 2098ms total) +T1E3C 003:631 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 2098ms total) +T1E3C 003:631 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000010 (0000ms, 2098ms total) +T1E3C 003:631 JLINK_Go() (0026ms, 2124ms total) +T1E3C 003:657 JLINK_IsHalted() returns FALSE (0007ms, 2131ms total) +T1E3C 003:695 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0072ms, 2196ms total) +T1E3C 003:767 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0001ms, 2125ms total) +T1E3C 003:768 JLINK_ClrBPEx(BPHandle = 0x00000010) returns 0x00 (0000ms, 2125ms total) +T1E3C 003:768 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 2125ms total) +T1E3C 003:768 JLINK_WriteMem(0x20000170, 0x0290 Bytes, ...) -- Data: 00 90 01 21 68 46 01 71 00 21 81 71 C1 71 03 21 ... -- CPU_WriteMem(656 bytes @ 0x20000170) returns 0x290 (0163ms, 2288ms total) +T1E3C 003:931 JLINK_WriteMem(0x20000400, 0x0170 Bytes, ...) -- Data: 4E 00 B5 40 86 68 35 43 85 60 85 88 01 26 8E 40 ... -- CPU_WriteMem(368 bytes @ 0x20000400) returns 0x170 (0096ms, 2384ms total) +T1E3C 004:027 JLINK_WriteReg(R0, 0x08000400) returns 0x00 (0000ms, 2384ms total) +T1E3C 004:027 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 2384ms total) +T1E3C 004:027 JLINK_WriteReg(R2, 0x20000170) returns 0x00 (0000ms, 2384ms total) +T1E3C 004:027 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 2384ms total) +T1E3C 004:027 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 2384ms total) +T1E3C 004:027 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 2384ms total) +T1E3C 004:027 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 2384ms total) +T1E3C 004:027 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 2384ms total) +T1E3C 004:027 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 2384ms total) +T1E3C 004:027 JLINK_WriteReg(R9, 0x2000016C) returns 0x00 (0000ms, 2384ms total) +T1E3C 004:027 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 2384ms total) +T1E3C 004:027 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 2384ms total) +T1E3C 004:027 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 2384ms total) +T1E3C 004:027 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 2384ms total) +T1E3C 004:027 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 2384ms total) +T1E3C 004:027 JLINK_WriteReg(R15 (PC), 0x200000FA) returns 0x00 (0000ms, 2384ms total) +T1E3C 004:027 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 2384ms total) +T1E3C 004:027 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 2384ms total) +T1E3C 004:027 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 2384ms total) +T1E3C 004:027 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 2384ms total) +T1E3C 004:027 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000011 (0000ms, 2384ms total) +T1E3C 004:027 JLINK_Go() (0029ms, 2413ms total) +T1E3C 004:056 JLINK_IsHalted() returns FALSE (0007ms, 2420ms total) +T1E3C 004:074 JLINK_IsHalted() returns FALSE (0007ms, 2420ms total) +T1E3C 004:083 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0073ms, 2486ms total) +T1E3C 004:156 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 2413ms total) +T1E3C 004:156 JLINK_ClrBPEx(BPHandle = 0x00000011) returns 0x00 (0000ms, 2413ms total) +T1E3C 004:156 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 2413ms total) +T1E3C 004:156 JLINK_WriteMem(0x20000170, 0x0290 Bytes, ...) -- Data: EE 49 48 60 08 46 C0 6A 00 09 00 01 C8 62 08 46 ... -- CPU_WriteMem(656 bytes @ 0x20000170) returns 0x290 (0163ms, 2576ms total) +T1E3C 004:319 JLINK_WriteMem(0x20000400, 0x0170 Bytes, ...) -- Data: 51 60 11 46 49 68 82 B2 11 43 48 4A 51 60 11 46 ... -- CPU_WriteMem(368 bytes @ 0x20000400) returns 0x170 (0096ms, 2672ms total) +T1E3C 004:415 JLINK_WriteReg(R0, 0x08000800) returns 0x00 (0000ms, 2672ms total) +T1E3C 004:415 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 2672ms total) +T1E3C 004:415 JLINK_WriteReg(R2, 0x20000170) returns 0x00 (0000ms, 2672ms total) +T1E3C 004:415 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 2672ms total) +T1E3C 004:415 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 2672ms total) +T1E3C 004:415 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 2672ms total) +T1E3C 004:415 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 2672ms total) +T1E3C 004:415 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 2672ms total) +T1E3C 004:415 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 2672ms total) +T1E3C 004:415 JLINK_WriteReg(R9, 0x2000016C) returns 0x00 (0000ms, 2672ms total) +T1E3C 004:415 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 2672ms total) +T1E3C 004:415 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 2672ms total) +T1E3C 004:415 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 2672ms total) +T1E3C 004:415 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 2672ms total) +T1E3C 004:415 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0001ms, 2673ms total) +T1E3C 004:416 JLINK_WriteReg(R15 (PC), 0x200000FA) returns 0x00 (0000ms, 2673ms total) +T1E3C 004:416 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 2673ms total) +T1E3C 004:416 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 2673ms total) +T1E3C 004:416 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 2673ms total) +T1E3C 004:416 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 2673ms total) +T1E3C 004:416 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000012 (0000ms, 2673ms total) +T1E3C 004:416 JLINK_Go() (0028ms, 2701ms total) +T1E3C 004:444 JLINK_IsHalted() returns FALSE (0007ms, 2708ms total) +T1E3C 004:460 JLINK_IsHalted() returns FALSE (0006ms, 2707ms total) +T1E3C 004:468 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0072ms, 2773ms total) +T1E3C 004:540 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 2701ms total) +T1E3C 004:540 JLINK_ClrBPEx(BPHandle = 0x00000012) returns 0x00 (0000ms, 2701ms total) +T1E3C 004:540 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 2701ms total) +T1E3C 004:540 JLINK_WriteMem(0x20000170, 0x0290 Bytes, ...) -- Data: 6C 48 20 61 02 E0 01 20 C0 03 20 61 68 48 00 6B ... -- CPU_WriteMem(656 bytes @ 0x20000170) returns 0x290 (0163ms, 2864ms total) +T1E3C 004:703 JLINK_WriteMem(0x20000400, 0x0170 Bytes, ...) -- Data: 84 42 08 D1 01 21 48 04 FF F7 57 FF 00 21 01 20 ... -- CPU_WriteMem(368 bytes @ 0x20000400) returns 0x170 (0096ms, 2960ms total) +T1E3C 004:799 JLINK_WriteReg(R0, 0x08000C00) returns 0x00 (0000ms, 2960ms total) +T1E3C 004:799 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 2960ms total) +T1E3C 004:799 JLINK_WriteReg(R2, 0x20000170) returns 0x00 (0000ms, 2960ms total) +T1E3C 004:799 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 2960ms total) +T1E3C 004:799 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 2960ms total) +T1E3C 004:799 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 2960ms total) +T1E3C 004:799 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 2960ms total) +T1E3C 004:799 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 2960ms total) +T1E3C 004:799 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 2960ms total) +T1E3C 004:800 JLINK_WriteReg(R9, 0x2000016C) returns 0x00 (0000ms, 2961ms total) +T1E3C 004:800 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 2961ms total) +T1E3C 004:800 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 2961ms total) +T1E3C 004:800 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 2961ms total) +T1E3C 004:800 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 2961ms total) +T1E3C 004:800 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 2961ms total) +T1E3C 004:800 JLINK_WriteReg(R15 (PC), 0x200000FA) returns 0x00 (0000ms, 2961ms total) +T1E3C 004:800 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 2961ms total) +T1E3C 004:800 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 2961ms total) +T1E3C 004:800 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 2961ms total) +T1E3C 004:800 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 2961ms total) +T1E3C 004:800 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000013 (0000ms, 2961ms total) +T1E3C 004:800 JLINK_Go() (0029ms, 2990ms total) +T1E3C 004:829 JLINK_IsHalted() returns FALSE (0007ms, 2997ms total) +T1E3C 004:845 JLINK_IsHalted() returns FALSE (0005ms, 2995ms total) +T1E3C 004:853 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0073ms, 3063ms total) +T1E3C 004:926 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 2990ms total) +T1E3C 004:926 JLINK_ClrBPEx(BPHandle = 0x00000013) returns 0x00 (0000ms, 2990ms total) +T1E3C 004:926 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 2990ms total) +T1E3C 004:926 JLINK_WriteMem(0x20000170, 0x0290 Bytes, ...) -- Data: 8B 43 03 60 70 47 00 29 05 D0 02 68 01 23 DB 03 ... -- CPU_WriteMem(656 bytes @ 0x20000170) returns 0x290 (0163ms, 3153ms total) +T1E3C 005:090 JLINK_WriteMem(0x20000400, 0x0170 Bytes, ...) -- Data: 9B 03 1A 43 82 60 04 E0 82 68 01 23 9B 03 9A 43 ... -- CPU_WriteMem(368 bytes @ 0x20000400) returns 0x170 (0094ms, 3247ms total) +T1E3C 005:184 JLINK_WriteReg(R0, 0x08001000) returns 0x00 (0000ms, 3247ms total) +T1E3C 005:184 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 3247ms total) +T1E3C 005:184 JLINK_WriteReg(R2, 0x20000170) returns 0x00 (0001ms, 3248ms total) +T1E3C 005:185 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 3248ms total) +T1E3C 005:185 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 3248ms total) +T1E3C 005:185 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 3248ms total) +T1E3C 005:185 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 3248ms total) +T1E3C 005:185 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 3248ms total) +T1E3C 005:185 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 3248ms total) +T1E3C 005:185 JLINK_WriteReg(R9, 0x2000016C) returns 0x00 (0000ms, 3248ms total) +T1E3C 005:185 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 3248ms total) +T1E3C 005:185 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 3248ms total) +T1E3C 005:185 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 3248ms total) +T1E3C 005:185 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 3248ms total) +T1E3C 005:185 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 3248ms total) +T1E3C 005:185 JLINK_WriteReg(R15 (PC), 0x200000FA) returns 0x00 (0000ms, 3248ms total) +T1E3C 005:185 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 3248ms total) +T1E3C 005:185 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 3248ms total) +T1E3C 005:185 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 3248ms total) +T1E3C 005:185 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 3248ms total) +T1E3C 005:185 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000014 (0000ms, 3248ms total) +T1E3C 005:185 JLINK_Go() (0029ms, 3277ms total) +T1E3C 005:214 JLINK_IsHalted() returns FALSE (0007ms, 3284ms total) +T1E3C 005:229 JLINK_IsHalted() returns FALSE (0007ms, 3284ms total) +T1E3C 005:238 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0072ms, 3349ms total) +T1E3C 005:310 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 3277ms total) +T1E3C 005:310 JLINK_ClrBPEx(BPHandle = 0x00000014) returns 0x00 (0000ms, 3277ms total) +T1E3C 005:310 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 3277ms total) +T1E3C 005:311 JLINK_WriteMem(0x20000170, 0x0290 Bytes, ...) -- Data: 14 00 00 20 00 22 03 09 8B 42 2C D3 03 0A 8B 42 ... -- CPU_WriteMem(656 bytes @ 0x20000170) returns 0x290 (0162ms, 3440ms total) +T1E3C 005:473 JLINK_WriteMem(0x20000400, 0x0170 Bytes, ...) -- Data: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ... -- CPU_WriteMem(368 bytes @ 0x20000400) returns 0x170 (0097ms, 3537ms total) +T1E3C 005:570 JLINK_WriteReg(R0, 0x08001400) returns 0x00 (0000ms, 3537ms total) +T1E3C 005:570 JLINK_WriteReg(R1, 0x0000028C) returns 0x00 (0000ms, 3537ms total) +T1E3C 005:570 JLINK_WriteReg(R2, 0x20000170) returns 0x00 (0000ms, 3537ms total) +T1E3C 005:570 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 3537ms total) +T1E3C 005:570 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 3537ms total) +T1E3C 005:570 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 3537ms total) +T1E3C 005:570 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 3537ms total) +T1E3C 005:570 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 3537ms total) +T1E3C 005:570 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 3537ms total) +T1E3C 005:570 JLINK_WriteReg(R9, 0x2000016C) returns 0x00 (0000ms, 3537ms total) +T1E3C 005:570 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 3537ms total) +T1E3C 005:570 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 3537ms total) +T1E3C 005:570 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 3537ms total) +T1E3C 005:570 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 3537ms total) +T1E3C 005:570 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 3537ms total) +T1E3C 005:570 JLINK_WriteReg(R15 (PC), 0x200000FA) returns 0x00 (0000ms, 3537ms total) +T1E3C 005:570 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 3537ms total) +T1E3C 005:570 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 3537ms total) +T1E3C 005:570 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 3537ms total) +T1E3C 005:570 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 3537ms total) +T1E3C 005:570 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000015 (0000ms, 3537ms total) +T1E3C 005:570 JLINK_Go() (0028ms, 3565ms total) +T1E3C 005:598 JLINK_IsHalted() returns FALSE (0007ms, 3572ms total) +T1E3C 005:699 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0072ms, 3637ms total) +T1E3C 005:771 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0001ms, 3566ms total) +T1E3C 005:772 JLINK_ClrBPEx(BPHandle = 0x00000015) returns 0x00 (0000ms, 3566ms total) +T1E3C 005:772 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 3566ms total) +T1E3C 005:772 JLINK_WriteReg(R0, 0x00000002) returns 0x00 (0000ms, 3566ms total) +T1E3C 005:772 JLINK_WriteReg(R1, 0x0000028C) returns 0x00 (0000ms, 3566ms total) +T1E3C 005:772 JLINK_WriteReg(R2, 0x20000170) returns 0x00 (0000ms, 3566ms total) +T1E3C 005:772 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 3566ms total) +T1E3C 005:772 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 3566ms total) +T1E3C 005:772 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 3566ms total) +T1E3C 005:772 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 3566ms total) +T1E3C 005:772 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 3566ms total) +T1E3C 005:772 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 3566ms total) +T1E3C 005:772 JLINK_WriteReg(R9, 0x2000016C) returns 0x00 (0000ms, 3566ms total) +T1E3C 005:772 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 3566ms total) +T1E3C 005:772 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 3566ms total) +T1E3C 005:772 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 3566ms total) +T1E3C 005:772 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 3566ms total) +T1E3C 005:772 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 3566ms total) +T1E3C 005:772 JLINK_WriteReg(R15 (PC), 0x20000066) returns 0x00 (0000ms, 3566ms total) +T1E3C 005:772 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 3566ms total) +T1E3C 005:772 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 3566ms total) +T1E3C 005:772 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 3566ms total) +T1E3C 005:772 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 3566ms total) +T1E3C 005:772 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000016 (0000ms, 3566ms total) +T1E3C 005:772 JLINK_Go() (0029ms, 3595ms total) +T1E3C 005:801 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0073ms, 3668ms total) +T1E3C 005:874 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 3595ms total) +T1E3C 005:874 JLINK_ClrBPEx(BPHandle = 0x00000016) returns 0x00 (0000ms, 3595ms total) +T1E3C 005:874 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 3595ms total) +T1E3C 005:931 JLINK_WriteMem(0x20000000, 0x0170 Bytes, ...) -- Data: 00 BE 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... -- CPU_WriteMem(368 bytes @ 0x20000000) returns 0x170 (0096ms, 3691ms total) +T1E3C 006:027 JLINK_WriteReg(R0, 0x08000000) returns 0x00 (0000ms, 3691ms total) +T1E3C 006:027 JLINK_WriteReg(R1, 0x02DC6C00) returns 0x00 (0000ms, 3691ms total) +T1E3C 006:027 JLINK_WriteReg(R2, 0x00000003) returns 0x00 (0000ms, 3691ms total) +T1E3C 006:027 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 3691ms total) +T1E3C 006:027 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 3691ms total) +T1E3C 006:027 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 3691ms total) +T1E3C 006:027 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 3691ms total) +T1E3C 006:027 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 3691ms total) +T1E3C 006:027 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 3691ms total) +T1E3C 006:027 JLINK_WriteReg(R9, 0x2000016C) returns 0x00 (0000ms, 3691ms total) +T1E3C 006:027 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 3691ms total) +T1E3C 006:027 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 3691ms total) +T1E3C 006:027 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 3691ms total) +T1E3C 006:027 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 3691ms total) +T1E3C 006:027 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 3691ms total) +T1E3C 006:027 JLINK_WriteReg(R15 (PC), 0x20000038) returns 0x00 (0000ms, 3691ms total) +T1E3C 006:027 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 3691ms total) +T1E3C 006:027 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 3691ms total) +T1E3C 006:027 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 3691ms total) +T1E3C 006:027 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 3691ms total) +T1E3C 006:027 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) -- CPU_ReadMem(2 bytes @ 0x20000000) returns 0x00000017 (0007ms, 3698ms total) +T1E3C 006:035 JLINK_Go() -- CPU_WriteMem(2 bytes @ 0x20000000) (0033ms, 3731ms total) +T1E3C 006:068 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0072ms, 3803ms total) +T1E3C 006:141 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 3731ms total) +T1E3C 006:141 JLINK_ClrBPEx(BPHandle = 0x00000017) returns 0x00 (0000ms, 3731ms total) +T1E3C 006:141 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 3731ms total) +T1E3C 006:141 JLINK_WriteReg(R0, 0xFFFFFFFF) returns 0x00 (0000ms, 3731ms total) +T1E3C 006:141 JLINK_WriteReg(R1, 0x08000000) returns 0x00 (0000ms, 3731ms total) +T1E3C 006:141 JLINK_WriteReg(R2, 0x0000168C) returns 0x00 (0000ms, 3731ms total) +T1E3C 006:141 JLINK_WriteReg(R3, 0x04C11DB7) returns 0x00 (0000ms, 3731ms total) +T1E3C 006:141 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0001ms, 3732ms total) +T1E3C 006:142 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 3732ms total) +T1E3C 006:142 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 3732ms total) +T1E3C 006:142 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 3732ms total) +T1E3C 006:142 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 3732ms total) +T1E3C 006:142 JLINK_WriteReg(R9, 0x2000016C) returns 0x00 (0000ms, 3732ms total) +T1E3C 006:142 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 3732ms total) +T1E3C 006:142 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 3732ms total) +T1E3C 006:142 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 3732ms total) +T1E3C 006:142 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 3732ms total) +T1E3C 006:142 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 3732ms total) +T1E3C 006:142 JLINK_WriteReg(R15 (PC), 0x20000002) returns 0x00 (0000ms, 3732ms total) +T1E3C 006:142 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 3732ms total) +T1E3C 006:142 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 3732ms total) +T1E3C 006:142 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 3732ms total) +T1E3C 006:142 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 3732ms total) +T1E3C 006:142 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000018 (0000ms, 3732ms total) +T1E3C 006:142 JLINK_Go() (0029ms, 3761ms total) +T1E3C 006:171 JLINK_IsHalted() returns FALSE (0007ms, 3768ms total) +T1E3C 006:199 JLINK_IsHalted() returns FALSE (0007ms, 3768ms total) +T1E3C 006:209 JLINK_IsHalted() returns FALSE (0006ms, 3767ms total) +T1E3C 006:219 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0072ms, 3833ms total) +T1E3C 006:291 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 3761ms total) +T1E3C 006:291 JLINK_ClrBPEx(BPHandle = 0x00000018) returns 0x00 (0000ms, 3761ms total) +T1E3C 006:291 JLINK_ReadReg(R0) returns 0xD6B929BE (0000ms, 3761ms total) +T1E3C 006:292 JLINK_WriteReg(R0, 0x00000003) returns 0x00 (0000ms, 3761ms total) +T1E3C 006:292 JLINK_WriteReg(R1, 0x08000000) returns 0x00 (0000ms, 3761ms total) +T1E3C 006:292 JLINK_WriteReg(R2, 0x0000168C) returns 0x00 (0000ms, 3761ms total) +T1E3C 006:292 JLINK_WriteReg(R3, 0x04C11DB7) returns 0x00 (0000ms, 3761ms total) +T1E3C 006:292 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 3761ms total) +T1E3C 006:292 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 3761ms total) +T1E3C 006:292 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 3761ms total) +T1E3C 006:292 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 3761ms total) +T1E3C 006:292 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 3761ms total) +T1E3C 006:292 JLINK_WriteReg(R9, 0x2000016C) returns 0x00 (0000ms, 3761ms total) +T1E3C 006:292 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 3761ms total) +T1E3C 006:292 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 3761ms total) +T1E3C 006:292 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 3761ms total) +T1E3C 006:292 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 3761ms total) +T1E3C 006:292 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 3761ms total) +T1E3C 006:292 JLINK_WriteReg(R15 (PC), 0x20000066) returns 0x00 (0000ms, 3761ms total) +T1E3C 006:292 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 3761ms total) +T1E3C 006:292 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 3761ms total) +T1E3C 006:292 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 3761ms total) +T1E3C 006:292 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 3761ms total) +T1E3C 006:292 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000019 (0000ms, 3761ms total) +T1E3C 006:292 JLINK_Go() (0029ms, 3790ms total) +T1E3C 006:321 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0072ms, 3862ms total) +T1E3C 006:393 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 3790ms total) +T1E3C 006:393 JLINK_ClrBPEx(BPHandle = 0x00000019) returns 0x00 (0000ms, 3790ms total) +T1E3C 006:393 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 3790ms total) +T1E3C 006:612 JLINK_Close() -- CPU_ReadMem(2 bytes @ 0x20000000) -- CPU_WriteMem(2 bytes @ 0x20000000) >0x42 TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> (0033ms, 3823ms total) +T1E3C 006:612 (0034ms, 3824ms total) +T1E3C 006:612 Closed (0034ms, 3824ms total) diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/JLinkSettings.ini b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/JLinkSettings.ini new file mode 100644 index 0000000..f40a58f --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/JLinkSettings.ini @@ -0,0 +1,34 @@ +[BREAKPOINTS] +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 0 +Device="UNSPECIFIED" +[GENERAL] +WorkRAMSize = 0x00 +WorkRAMAddr = 0x00 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/RTE/_Stm32f030demo/RTE_Components.h b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/RTE/_Stm32f030demo/RTE_Components.h new file mode 100644 index 0000000..f0863d2 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/RTE/_Stm32f030demo/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'STM32F030Demo' + * Target: 'Stm32f030demo' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f0xx.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/STM32F030Demo.map b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/STM32F030Demo.map new file mode 100644 index 0000000..e0be45e --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/STM32F030Demo.map @@ -0,0 +1,279 @@ +Product: MDK-ARM Standard 5.10 +Component: ARM Compiler 5.04 update 1 (build 49) +Tool: armlink [5040049] + +============================================================================== + +Section Cross References + + main.o(.text) refers to delay.o(.text) for delay_init + main.o(.text) refers to led.o(.text) for LED_Init + main.o(.text) refers to usart1.o(.text) for USART1_Init + main.o(.text) refers to noretval__2printf.o(.text) for __2printf + main.o(.text) refers to main.o(.conststring) for .conststring + system_stm32f0xx.o(.text) refers to aeabi_sdiv.o(.text) for __aeabi_uidivmod + system_stm32f0xx.o(.text) refers to system_stm32f0xx.o(.data) for SystemCoreClock + startup_stm32f0xx.o(STACK) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32f0xx.o(HEAP) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32f0xx.o(RESET) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32f0xx.o(RESET) refers to startup_stm32f0xx.o(STACK) for __initial_sp + startup_stm32f0xx.o(RESET) refers to startup_stm32f0xx.o(.text) for Reset_Handler + startup_stm32f0xx.o(RESET) refers to stm32f0xx_it.o(.text) for NMI_Handler + startup_stm32f0xx.o(RESET) refers to usart1.o(.text) for USART1_IRQHandler + startup_stm32f0xx.o(.text) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32f0xx.o(.text) refers to system_stm32f0xx.o(.text) for SystemInit + startup_stm32f0xx.o(.text) refers to __main.o(!!!main) for __main + startup_stm32f0xx.o(.text) refers to startup_stm32f0xx.o(HEAP) for Heap_Mem + startup_stm32f0xx.o(.text) refers to startup_stm32f0xx.o(STACK) for Stack_Mem + led.o(.text) refers to stm32f0xx_rcc.o(.text) for RCC_AHBPeriphClockCmd + led.o(.text) refers to stm32f0xx_gpio.o(.text) for GPIO_Init + usart1.o(.emb_text) refers (Special) to use_no_semi_2.o(.text) for __use_no_semihosting + usart1.o(.text) refers (Special) to use_no_semi_2.o(.text) for __use_no_semihosting + usart1.o(.text) refers to stm32f0xx_rcc.o(.text) for RCC_AHBPeriphClockCmd + usart1.o(.text) refers to stm32f0xx_gpio.o(.text) for GPIO_PinAFConfig + usart1.o(.text) refers to stm32f0xx_usart.o(.text) for USART_Init + usart1.o(.text) refers to stm32f0xx_misc.o(.text) for NVIC_Init + usart1.o(.data) refers (Special) to use_no_semi_2.o(.text) for __use_no_semihosting + delay.o(.text) refers to stm32f0xx_misc.o(.text) for SysTick_CLKSourceConfig + delay.o(.text) refers to aeabi_sdiv.o(.text) for __aeabi_uidivmod + delay.o(.text) refers to system_stm32f0xx.o(.data) for SystemCoreClock + delay.o(.text) refers to delay.o(.data) for fac_us + stm32f0xx_gpio.o(.text) refers to stm32f0xx_rcc.o(.text) for RCC_AHBPeriphResetCmd + stm32f0xx_rcc.o(.text) refers to aeabi_sdiv.o(.text) for __aeabi_uidivmod + stm32f0xx_rcc.o(.text) refers to stm32f0xx_rcc.o(.data) for APBAHBPrescTable + stm32f0xx_usart.o(.text) refers to stm32f0xx_rcc.o(.text) for RCC_APB2PeriphResetCmd + stm32f0xx_usart.o(.text) refers to aeabi_sdiv.o(.text) for __aeabi_uidivmod + use_no_semi_2.o(.text) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi + __2printf.o(.text) refers to _printf_char_file.o(.text) for _printf_char_file + __2printf.o(.text) refers to usart1.o(.data) for __stdout + noretval__2printf.o(.text) refers to _printf_char_file.o(.text) for _printf_char_file + noretval__2printf.o(.text) refers to usart1.o(.data) for __stdout + __main.o(!!!main) refers to rtentry.o(.ARM.Collect$$rtentry$$00000000) for __rt_entry + rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for __rt_entry_li + rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for __rt_entry_main + rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to rtentry2.o(.ARM.Collect$$rtentry$$0000000C) for __rt_entry_postli_1 + rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to rtentry2.o(.ARM.Collect$$rtentry$$00000009) for __rt_entry_postsh_1 + rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to rtentry2.o(.ARM.Collect$$rtentry$$00000002) for __rt_entry_presh_1 + rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to rtentry4.o(.ARM.Collect$$rtentry$$00000004) for __rt_entry_sh + aeabi_idiv0_sigfpe.o(.text) refers to rt_div0.o(.text) for __rt_div0 + _printf_char_file.o(.text) refers to _printf_char_common.o(.text) for _printf_char_common + _printf_char_file.o(.text) refers to ferror.o(.text) for ferror + _printf_char_file.o(.text) refers to usart1.o(.text) for fputc + rtentry2.o(.ARM.Collect$$rtentry$$00000008) refers to boardinit2.o(.text) for _platform_post_stackheap_init + rtentry2.o(.ARM.Collect$$rtentry$$0000000A) refers to libinit.o(.ARM.Collect$$libinit$$00000000) for __rt_lib_init + rtentry2.o(.ARM.Collect$$rtentry$$0000000B) refers to boardinit3.o(.text) for _platform_post_lib_init + rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to main.o(.text) for main + rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to exit.o(.text) for exit + rtentry2.o(.ARM.exidx) refers to rtentry2.o(.ARM.Collect$$rtentry$$00000001) for .ARM.Collect$$rtentry$$00000001 + rtentry2.o(.ARM.exidx) refers to rtentry2.o(.ARM.Collect$$rtentry$$00000008) for .ARM.Collect$$rtentry$$00000008 + rtentry2.o(.ARM.exidx) refers to rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for .ARM.Collect$$rtentry$$0000000A + rtentry2.o(.ARM.exidx) refers to rtentry2.o(.ARM.Collect$$rtentry$$0000000B) for .ARM.Collect$$rtentry$$0000000B + rtentry2.o(.ARM.exidx) refers to rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for .ARM.Collect$$rtentry$$0000000D + rtentry4.o(.ARM.Collect$$rtentry$$00000004) refers to sys_stackheap_outer.o(.text) for __user_setup_stackheap + rtentry4.o(.ARM.exidx) refers to rtentry4.o(.ARM.Collect$$rtentry$$00000004) for .ARM.Collect$$rtentry$$00000004 + rt_div0.o(.text) refers to defsig_fpe_outer.o(.text) for __rt_SIGFPE + _printf_char_common.o(.text) refers to __printf_nopercent.o(.text) for __printf + sys_stackheap_outer.o(.text) refers to libspace.o(.text) for __user_perproc_libspace + sys_stackheap_outer.o(.text) refers to startup_stm32f0xx.o(.text) for __user_initial_stackheap + sys_stackheap_outer.o(__vectab_stack_and_reset_area) refers to tempstk.o(.text) for __temporary_stack_top + sys_stackheap_outer.o(__vectab_stack_and_reset_area) refers to __main.o(!!!main) for __main + exit.o(.text) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for __rt_exit + defsig_fpe_outer.o(.text) refers to defsig_fpe_inner.o(.text) for __rt_SIGFPE_inner + defsig_fpe_outer.o(.text) refers to defsig_exit.o(.text) for __sig_exit + defsig_fpe_formal.o(.text) refers to rt_raise.o(.text) for __rt_raise + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002C) for __rt_lib_init_alloca_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002A) for __rt_lib_init_argv_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000019) for __rt_lib_init_atexit_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001F) for __rt_lib_init_clock_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000030) for __rt_lib_init_cpp_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002E) for __rt_lib_init_exceptions_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000001) for __rt_lib_init_fp_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001D) for __rt_lib_init_fp_trap_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000021) for __rt_lib_init_getenv_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000008) for __rt_lib_init_heap_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000F) for __rt_lib_init_lc_collate_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000011) for __rt_lib_init_lc_ctype_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000013) for __rt_lib_init_lc_monetary_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000015) for __rt_lib_init_lc_numeric_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000017) for __rt_lib_init_lc_time_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000C) for __rt_lib_init_rand_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000031) for __rt_lib_init_return + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001B) for __rt_lib_init_signal_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000023) for __rt_lib_init_stdio_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000A) for __rt_lib_init_user_alloc_1 + libspace.o(.text) refers to libspace.o(.bss) for __libspace_start + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1 + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1 + rtexit.o(.ARM.exidx) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for .ARM.Collect$$rtexit$$00000000 + rt_raise.o(.text) refers to __raise.o(.text) for __raise + rt_raise.o(.text) refers to usart1.o(.text) for _sys_exit + defsig_exit.o(.text) refers to usart1.o(.text) for _sys_exit + defsig_fpe_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + libinit2.o(.ARM.Collect$$libinit$$0000000E) refers to libinit2.o(.ARM.Collect$$libinit$$0000000D) for .ARM.Collect$$libinit$$0000000D + libinit2.o(.ARM.Collect$$libinit$$00000010) refers to libinit2.o(.ARM.Collect$$libinit$$0000000D) for .ARM.Collect$$libinit$$0000000D + libinit2.o(.ARM.Collect$$libinit$$00000012) refers to libinit2.o(.ARM.Collect$$libinit$$0000000D) for .ARM.Collect$$libinit$$0000000D + libinit2.o(.ARM.Collect$$libinit$$00000014) refers to libinit2.o(.ARM.Collect$$libinit$$0000000D) for .ARM.Collect$$libinit$$0000000D + libinit2.o(.ARM.Collect$$libinit$$00000016) refers to libinit2.o(.ARM.Collect$$libinit$$0000000D) for .ARM.Collect$$libinit$$0000000D + libinit2.o(.ARM.Collect$$libinit$$00000024) refers to argv_veneer.o(.text) for __ARM_argv_veneer + libinit2.o(.ARM.Collect$$libinit$$00000025) refers to argv_veneer.o(.text) for __ARM_argv_veneer + rtexit2.o(.ARM.Collect$$rtexit$$00000003) refers to libshutdown.o(.ARM.Collect$$libshutdown$$00000000) for __rt_lib_shutdown + rtexit2.o(.ARM.Collect$$rtexit$$00000004) refers to usart1.o(.text) for _sys_exit + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000001) for .ARM.Collect$$rtexit$$00000001 + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for .ARM.Collect$$rtexit$$00000003 + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for .ARM.Collect$$rtexit$$00000004 + __raise.o(.text) refers to defsig.o(CL$$defsig) for __default_signal_handler + defsig_general.o(.text) refers to sys_wrch.o(.text) for _ttywrch + sys_wrch.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_wrch.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + defsig.o(CL$$defsig) refers to defsig_fpe_inner.o(.text) for __rt_SIGFPE_inner + defsig.o(CL$$defsig) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner + _get_argv_nomalloc.o(.text) refers (Special) to hrguard.o(.text) for __heap_region$guard + _get_argv_nomalloc.o(.text) refers to defsig_rtmem_outer.o(.text) for __rt_SIGRTMEM + _get_argv_nomalloc.o(.text) refers to sys_command.o(.text) for _sys_command_string + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000006) for __rt_lib_shutdown_fp_trap_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000E) for __rt_lib_shutdown_heap_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F) for __rt_lib_shutdown_return + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000009) for __rt_lib_shutdown_signal_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000003) for __rt_lib_shutdown_stdio_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000B) for __rt_lib_shutdown_user_alloc_1 + sys_command.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_command.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + defsig_abrt_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_rtred_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_rtmem_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_rtmem_outer.o(.text) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner + defsig_rtmem_outer.o(.text) refers to defsig_exit.o(.text) for __sig_exit + defsig_rtmem_formal.o(.text) refers to rt_raise.o(.text) for __rt_raise + defsig_stak_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_pvfn_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_cppl_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_segv_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_other.o(.text) refers to defsig_general.o(.text) for __default_signal_display + + +============================================================================== + +Removing Unused input sections from the image. + + Removing main.o(.emb_text), (8 bytes). + Removing stm32f0xx_it.o(.emb_text), (8 bytes). + Removing system_stm32f0xx.o(.emb_text), (8 bytes). + Removing led.o(.emb_text), (8 bytes). + Removing usart1.o(.emb_text), (8 bytes). + Removing delay.o(.emb_text), (8 bytes). + Removing stm32f0xx_gpio.o(.emb_text), (8 bytes). + Removing stm32f0xx_rcc.o(.emb_text), (8 bytes). + Removing stm32f0xx_misc.o(.emb_text), (8 bytes). + Removing stm32f0xx_usart.o(.emb_text), (8 bytes). + +10 unused section(s) (total 80 bytes) removed from the image. + +============================================================================== + +Memory Map of the image + + Image Entry point : 0x00000000 + + Load Region LR_1 (Base: 0x08000000, Size: 0x00001dbc, Max: 0xffffffff, ABSOLUTE) + + Execution Region ER_RO (Base: 0x08000000, Size: 0x00001d90, Max: 0xffffffff, ABSOLUTE) + + Base Addr Size Type Attr Idx E Section Name Object + + 0x08000000 0x000000c0 Data RO 111 RESET startup_stm32f0xx.o + 0x080000c0 0x00000008 Code RO 272 * !!!main c_p.l(__main.o) + 0x080000c8 0x00000002 Code RO 322 .ARM.Collect$$libinit$$00000000 c_p.l(libinit.o) + 0x080000ca 0x00000004 Code RO 335 .ARM.Collect$$libinit$$00000001 c_p.l(libinit2.o) + 0x080000ce 0x00000000 Code RO 339 .ARM.Collect$$libinit$$00000008 c_p.l(libinit2.o) + 0x080000ce 0x00000000 Code RO 341 .ARM.Collect$$libinit$$0000000A c_p.l(libinit2.o) + 0x080000ce 0x00000000 Code RO 343 .ARM.Collect$$libinit$$0000000C c_p.l(libinit2.o) + 0x080000ce 0x00000000 Code RO 346 .ARM.Collect$$libinit$$0000000F c_p.l(libinit2.o) + 0x080000ce 0x00000000 Code RO 348 .ARM.Collect$$libinit$$00000011 c_p.l(libinit2.o) + 0x080000ce 0x00000000 Code RO 350 .ARM.Collect$$libinit$$00000013 c_p.l(libinit2.o) + 0x080000ce 0x00000000 Code RO 352 .ARM.Collect$$libinit$$00000015 c_p.l(libinit2.o) + 0x080000ce 0x00000000 Code RO 354 .ARM.Collect$$libinit$$00000017 c_p.l(libinit2.o) + 0x080000ce 0x00000000 Code RO 356 .ARM.Collect$$libinit$$00000019 c_p.l(libinit2.o) + 0x080000ce 0x00000000 Code RO 358 .ARM.Collect$$libinit$$0000001B c_p.l(libinit2.o) + 0x080000ce 0x00000000 Code RO 360 .ARM.Collect$$libinit$$0000001D c_p.l(libinit2.o) + 0x080000ce 0x00000000 Code RO 362 .ARM.Collect$$libinit$$0000001F c_p.l(libinit2.o) + 0x080000ce 0x00000000 Code RO 364 .ARM.Collect$$libinit$$00000021 c_p.l(libinit2.o) + 0x080000ce 0x00000000 Code RO 366 .ARM.Collect$$libinit$$00000023 c_p.l(libinit2.o) + 0x080000ce 0x00000000 Code RO 370 .ARM.Collect$$libinit$$0000002A c_p.l(libinit2.o) + 0x080000ce 0x00000000 Code RO 372 .ARM.Collect$$libinit$$0000002C c_p.l(libinit2.o) + 0x080000ce 0x00000000 Code RO 374 .ARM.Collect$$libinit$$0000002E c_p.l(libinit2.o) + 0x080000ce 0x00000000 Code RO 376 .ARM.Collect$$libinit$$00000030 c_p.l(libinit2.o) + 0x080000ce 0x00000002 Code RO 377 .ARM.Collect$$libinit$$00000031 c_p.l(libinit2.o) + 0x080000d0 0x00000002 Code RO 403 .ARM.Collect$$libshutdown$$00000000 c_p.l(libshutdown.o) + 0x080000d2 0x00000000 Code RO 431 .ARM.Collect$$libshutdown$$00000003 c_p.l(libshutdown2.o) + 0x080000d2 0x00000000 Code RO 434 .ARM.Collect$$libshutdown$$00000006 c_p.l(libshutdown2.o) + 0x080000d2 0x00000000 Code RO 437 .ARM.Collect$$libshutdown$$00000009 c_p.l(libshutdown2.o) + 0x080000d2 0x00000000 Code RO 439 .ARM.Collect$$libshutdown$$0000000B c_p.l(libshutdown2.o) + 0x080000d2 0x00000000 Code RO 442 .ARM.Collect$$libshutdown$$0000000E c_p.l(libshutdown2.o) + 0x080000d2 0x00000002 Code RO 443 .ARM.Collect$$libshutdown$$0000000F c_p.l(libshutdown2.o) + 0x080000d4 0x00000000 Code RO 276 .ARM.Collect$$rtentry$$00000000 c_p.l(rtentry.o) + 0x080000d4 0x00000000 Code RO 284 .ARM.Collect$$rtentry$$00000002 c_p.l(rtentry2.o) + 0x080000d4 0x00000006 Code RO 296 .ARM.Collect$$rtentry$$00000004 c_p.l(rtentry4.o) + 0x080000da 0x00000000 Code RO 286 .ARM.Collect$$rtentry$$00000009 c_p.l(rtentry2.o) + 0x080000da 0x00000004 Code RO 287 .ARM.Collect$$rtentry$$0000000A c_p.l(rtentry2.o) + 0x080000de 0x00000000 Code RO 289 .ARM.Collect$$rtentry$$0000000C c_p.l(rtentry2.o) + 0x080000de 0x00000008 Code RO 290 .ARM.Collect$$rtentry$$0000000D c_p.l(rtentry2.o) + 0x080000e6 0x00000002 Code RO 327 .ARM.Collect$$rtexit$$00000000 c_p.l(rtexit.o) + 0x080000e8 0x00000000 Code RO 379 .ARM.Collect$$rtexit$$00000002 c_p.l(rtexit2.o) + 0x080000e8 0x00000004 Code RO 380 .ARM.Collect$$rtexit$$00000003 c_p.l(rtexit2.o) + 0x080000ec 0x00000006 Code RO 381 .ARM.Collect$$rtexit$$00000004 c_p.l(rtexit2.o) + 0x080000f2 0x00000002 PAD + 0x080000f4 0x000005fc Code RO 2 .text main.o + 0x080006f0 0x0000000c Code RO 69 .text stm32f0xx_it.o + 0x080006fc 0x000001f8 Code RO 88 .text system_stm32f0xx.o + 0x080008f4 0x00000038 Code RO 112 * .text startup_stm32f0xx.o + 0x0800092c 0x0000002a Code RO 117 .text led.o + 0x08000956 0x00000002 PAD + 0x08000958 0x000000e0 Code RO 152 .text usart1.o + 0x08000a38 0x000000d4 Code RO 175 .text delay.o + 0x08000b0c 0x000001f0 Code RO 193 .text stm32f0xx_gpio.o + 0x08000cfc 0x000005f8 Code RO 209 .text stm32f0xx_rcc.o + 0x080012f4 0x000000b4 Code RO 227 .text stm32f0xx_misc.o + 0x080013a8 0x00000574 Code RO 243 .text stm32f0xx_usart.o + 0x0800191c 0x00000002 Code RO 260 .text c_p.l(use_no_semi_2.o) + 0x0800191e 0x00000002 PAD + 0x08001920 0x0000001c Code RO 264 .text c_p.l(noretval__2printf.o) + 0x0800193c 0x0000015a Code RO 266 .text c_p.l(aeabi_sdiv.o) + 0x08001a96 0x00000006 Code RO 270 .text c_p.l(heapauxi.o) + 0x08001a9c 0x00000002 Code RO 274 .text c_p.l(use_no_semi.o) + 0x08001a9e 0x00000002 PAD + 0x08001aa0 0x00000028 Code RO 281 .text c_p.l(_printf_char_file.o) + 0x08001ac8 0x00000030 Code RO 300 .text c_p.l(_printf_char_common.o) + 0x08001af8 0x00000008 Code RO 302 .text c_p.l(ferror.o) + 0x08001b00 0x0000003e Code RO 306 .text c_p.l(sys_stackheap_outer.o) + 0x08001b3e 0x00000024 Code RO 309 .text c_p.l(__printf_nopercent.o) + 0x08001b62 0x0000000c Code RO 311 .text c_p.l(exit.o) + 0x08001b6e 0x00000002 PAD + 0x08001b70 0x00000008 Code RO 323 .text c_p.l(libspace.o) + 0x08001b78 0x00000215 Data RO 3 .conststring main.o + 0x08001d8d 0x00000003 PAD + 0x08001d90 0x00000000 Data RO 444 Region$$Table anon$$obj.o + + + Execution Region ER_RW (Base: 0x20000000, Size: 0x0000002c, Max: 0xffffffff, ABSOLUTE) + + Base Addr Size Type Attr Idx E Section Name Object + + 0x20000000 0x00000014 Data RW 89 .data system_stm32f0xx.o + 0x20000014 0x00000004 Data RW 153 .data usart1.o + 0x20000018 0x00000004 Data RW 176 .data delay.o + 0x2000001c 0x00000010 Data RW 210 .data stm32f0xx_rcc.o + + + Execution Region ER_ZI (Base: 0x2000002c, Size: 0x00000664, Max: 0xffffffff, ABSOLUTE) + + Base Addr Size Type Attr Idx E Section Name Object + + 0x2000002c 0x00000060 Zero RW 324 .bss c_p.l(libspace.o) + 0x2000008c 0x00000004 PAD + 0x20000090 0x00000200 Zero RW 110 HEAP startup_stm32f0xx.o + 0x20000290 0x00000400 Zero RW 109 STACK startup_stm32f0xx.o + diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/STM32F030Demo.uvgui.Administrator b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/STM32F030Demo.uvgui.Administrator new file mode 100644 index 0000000..3ecd038 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/STM32F030Demo.uvgui.Administrator @@ -0,0 +1,1367 @@ + + + + -5.1 + +
    ### uVision Project, (C) Keil Software
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    ### uVision Project, (C) Keil Software
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STM32F030串口 UART/JC144 STM32F030串口 UART/User/STM32F030Demo.uvopt b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/STM32F030Demo.uvopt new file mode 100644 index 0000000..0a07415 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/STM32F030Demo.uvopt @@ -0,0 +1,352 @@ + + + + 1.0 + +
    ### uVision Project, (C) Keil Software
    + + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Stm32f030demo + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + + 0 + STM32F0-Discovery Web Page (STM32F0-Discovery) + http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1848/PF253215 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 6 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U58009527 -O14 -S5 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F0xx_16.FLM -FS08000000 -FL04000 -FP0($$Device:STM32F030F4$Flash\STM32F0xx_16.FLM) + + + 0 + UL2CM3 + -S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F0xx_16 -FS08000000 -FL04000 -FP0($$Device:STM32F030F4$Flash\STM32F0xx_16.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + USER + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 1 + 0 + 0 + 0 + .\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + .\stm32f0xx_it.c + stm32f0xx_it.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + .\system_stm32f0xx.c + system_stm32f0xx.c + 0 + 0 + + + + + CORE + 0 + 0 + 0 + 0 + + 2 + 4 + 2 + 0 + 0 + 0 + 0 + ..\CORE\startup_stm32f0xx.s + startup_stm32f0xx.s + 0 + 0 + + + + + HARDWARE + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + 0 + ..\HARDWARE\led.c + led.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + 0 + ..\HARDWARE\USART1.c + USART1.c + 0 + 0 + + + + + SYSTEM + 0 + 0 + 0 + 0 + + 4 + 7 + 1 + 0 + 0 + 0 + 0 + ..\SYSTEM\delay.c + delay.c + 0 + 0 + + + + + STM32F03x_FWLib + 1 + 0 + 0 + 0 + + 5 + 8 + 1 + 0 + 0 + 0 + 0 + ..\STM32F03x_FWLib\src\stm32f0xx_gpio.c + stm32f0xx_gpio.c + 0 + 0 + + + 5 + 9 + 1 + 0 + 0 + 0 + 0 + ..\STM32F03x_FWLib\src\stm32f0xx_rcc.c + stm32f0xx_rcc.c + 0 + 0 + + + 5 + 10 + 1 + 0 + 0 + 0 + 0 + ..\STM32F03x_FWLib\src\stm32f0xx_misc.c + stm32f0xx_misc.c + 0 + 0 + + + 5 + 11 + 1 + 0 + 0 + 0 + 0 + ..\STM32F03x_FWLib\src\stm32f0xx_usart.c + stm32f0xx_usart.c + 0 + 0 + + + +     diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/STM32F030Demo.uvoptx b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/STM32F030Demo.uvoptx new file mode 100644 index 0000000..1b40fef --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/STM32F030Demo.uvoptx @@ -0,0 +1,351 @@ + + + + 1.0 + +
    ### uVision Project, (C) Keil Software
    + + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Stm32f030demo + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F0xx_16 -FS08000000 -FL04000 -FP0($$Device:STM32F030F4$CMSIS\Flash\STM32F0xx_16.FLM)) + + + 0 + JL2CM3 + -U58009527 -O14 -S5 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F0xx_16.FLM -FS08000000 -FL04000 -FP0($$Device:STM32F030F4$CMSIS\Flash\STM32F0xx_16.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 2 + 10000000 + + + + + + USER + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + .\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + .\stm32f0xx_it.c + stm32f0xx_it.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + .\system_stm32f0xx.c + system_stm32f0xx.c + 0 + 0 + + + + + CORE + 1 + 0 + 0 + 0 + + 2 + 4 + 2 + 0 + 0 + 0 + ..\CORE\startup_stm32f0xx.s + startup_stm32f0xx.s + 0 + 0 + + + + + HARDWARE + 0 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\HARDWARE\USART1.c + USART1.c + 0 + 0 + + + + + SYSTEM + 0 + 0 + 0 + 0 + + 4 + 6 + 1 + 1 + 0 + 0 + ..\SYSTEM\delay.c + delay.c + 0 + 0 + + + + + STM32F03x_FWLib + 0 + 0 + 0 + 0 + + 5 + 7 + 1 + 0 + 0 + 0 + ..\STM32F03x_FWLib\src\stm32f0xx_gpio.c + stm32f0xx_gpio.c + 0 + 0 + + + 5 + 8 + 1 + 0 + 0 + 0 + ..\STM32F03x_FWLib\src\stm32f0xx_rcc.c + stm32f0xx_rcc.c + 0 + 0 + + + 5 + 9 + 1 + 0 + 0 + 0 + ..\STM32F03x_FWLib\src\stm32f0xx_misc.c + stm32f0xx_misc.c + 0 + 0 + + + 5 + 10 + 1 + 0 + 0 + 0 + ..\STM32F03x_FWLib\src\stm32f0xx_usart.c + stm32f0xx_usart.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + +     diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/STM32F030Demo.uvproj.saved_uv4 b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/STM32F030Demo.uvproj.saved_uv4 new file mode 100644 index 0000000..56651af --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/STM32F030Demo.uvproj.saved_uv4 @@ -0,0 +1,501 @@ + + + + 1.1 + +
    ### uVision Project, (C) Keil Software
    + + + + Stm32f030demo + 0x4 + ARM-ADS + + + STM32F030F4 + STMicroelectronics + IROM(0x08000000,0x4000) IRAM(0x20000000,0x1000) CPUTYPE("Cortex-M0") CLOCK(48000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F0xx_16 -FS08000000 -FL04000 -FP0($$Device:STM32F030F4$Flash\STM32F0xx_16.FLM)) + 7305 + $$Device:STM32F030F4$Device\Include\stm32f0xx.h + + + + + + + + + + $$Device:STM32F030F4$SVD\STM32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + ..\OBJ\ + STM32F030Demo + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + + 0 + 6 + + + + + + + + + + + + + + Segger\JL2CM3.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x1000 + + + 1 + 0x8000000 + 0x4000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x4000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x1000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_STDPERIPH_DRIVER STM32F0XX + + ..\CORE;..\HARDWARE;..\STM32F03x_FWLib\inc;..\STM32F03x_FWLib\src;..\User;..\SYSTEM + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + USER + + + main.c + 1 + .\main.c + + + stm32f0xx_it.c + 1 + .\stm32f0xx_it.c + + + system_stm32f0xx.c + 1 + .\system_stm32f0xx.c + + + + + CORE + + + startup_stm32f0xx.s + 2 + ..\CORE\startup_stm32f0xx.s + + + + + HARDWARE + + + led.c + 1 + ..\HARDWARE\led.c + + + USART1.c + 1 + ..\HARDWARE\USART1.c + + + USART1_API.c + 1 + ..\HARDWARE\USART1_API.c + + + Key.c + 1 + ..\HARDWARE\Key.c + + + + + SYSTEM + + + delay.c + 1 + ..\SYSTEM\delay.c + + + + + STM32F03x_FWLib + + + stm32f0xx_gpio.c + 1 + ..\STM32F03x_FWLib\src\stm32f0xx_gpio.c + + + stm32f0xx_rcc.c + 1 + ..\STM32F03x_FWLib\src\stm32f0xx_rcc.c + + + stm32f0xx_misc.c + 1 + ..\STM32F03x_FWLib\src\stm32f0xx_misc.c + + + stm32f0xx_usart.c + 1 + ..\STM32F03x_FWLib\src\stm32f0xx_usart.c + + + + + + + +     diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/STM32F030Demo.uvprojx b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/STM32F030Demo.uvprojx new file mode 100644 index 0000000..4e5f863 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/STM32F030Demo.uvprojx @@ -0,0 +1,476 @@ + + + + 2.1 + +
    ### uVision Project, (C) Keil Software
    + + + + Stm32f030demo + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + STM32F030F4 + STMicroelectronics + Keil.STM32F0xx_DFP.2.0.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00001000) IROM(0x08000000,0x00004000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F0xx_16 -FS08000000 -FL04000 -FP0($$Device:STM32F030F4$CMSIS\Flash\STM32F0xx_16.FLM)) + 7305 + $$Device:STM32F030F4$Drivers\CMSIS\Device\ST\STM32F0xx\Include\stm32f0xx.h + + + + + + + -DSTM32F030 + + + $$Device:STM32F030F4$CMSIS\SVD\STM32F0x0.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + ..\OBJ\ + TEST + 1 + 0 + 1 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x1000 + + + 1 + 0x8000000 + 0x4000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x4000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x1000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + USE_STDPERIPH_DRIVER STM32F0XX + + ..\CORE;..\HARDWARE;..\STM32F03x_FWLib\inc;..\STM32F03x_FWLib\src;..\User;..\SYSTEM + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + USER + + + main.c + 1 + .\main.c + + + stm32f0xx_it.c + 1 + .\stm32f0xx_it.c + + + system_stm32f0xx.c + 1 + .\system_stm32f0xx.c + + + + + CORE + + + startup_stm32f0xx.s + 2 + ..\CORE\startup_stm32f0xx.s + + + + + HARDWARE + + + USART1.c + 1 + ..\HARDWARE\USART1.c + + + + + SYSTEM + + + delay.c + 1 + ..\SYSTEM\delay.c + + + + + STM32F03x_FWLib + + + stm32f0xx_gpio.c + 1 + ..\STM32F03x_FWLib\src\stm32f0xx_gpio.c + + + stm32f0xx_rcc.c + 1 + ..\STM32F03x_FWLib\src\stm32f0xx_rcc.c + + + stm32f0xx_misc.c + 1 + ..\STM32F03x_FWLib\src\stm32f0xx_misc.c + + + stm32f0xx_usart.c + 1 + ..\STM32F03x_FWLib\src\stm32f0xx_usart.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + +     diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/STM32F030Demo_Stm32f030demo.dep b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/STM32F030Demo_Stm32f030demo.dep new file mode 100644 index 0000000..39bc23d --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/STM32F030Demo_Stm32f030demo.dep @@ -0,0 +1,162 @@ +Dependencies for Project 'STM32F030Demo', Target 'Stm32f030demo': (DO NOT MODIFY !) +F (.\main.c)(0x5D68CEEB)(-c --cpu Cortex-M0 -g -O0 --apcs=interwork -I..\CORE -I..\HARDWARE -I..\STM32F03x_FWLib\inc -I..\STM32F03x_FWLib\src -I..\User -I..\SYSTEM -I "E:\SSJ Ŀ\SSJ Ŀ\\ʾ\\JC018_ STM32F030 UART -\JC018 STM32F030 UART\User\RTE" -I C:\Keil_v5\ARM\CMSIS\4.1.0\CMSIS\Include -D_RTE_ -DUSE_STDPERIPH_DRIVER -DSTM32F0XX -o ..\obj\main.o --omf_browse ..\obj\main.crf --depend ..\obj\main.d) +I (stm32f0xx.h)(0x5C0F2083) +I (..\CORE\core_cm0.h)(0x574D3404) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44) +I (..\CORE\core_cmInstr.h)(0x574D3404) +I (..\CORE\core_cmFunc.h)(0x574D3404) +I (system_stm32f0xx.h)(0x574D3404) +I (stm32f0xx_conf.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_gpio.h)(0x574D3404) +I (..\User\stm32f0xx.h)(0x5C0F2083) +I (..\STM32F03x_FWLib\inc\stm32f0xx_rcc.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_usart.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_misc.h)(0x574D3404) +I (..\SYSTEM\delay.h)(0x574D3404) +I (..\HARDWARE\led.h)(0x5D15B711) +I (..\HARDWARE\USART1.h)(0x574D3404) +I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44) +I (..\HARDWARE\Key.h)(0x574D3404) +F (.\stm32f0xx_it.c)(0x574D3404)(-c --cpu Cortex-M0 -g -O0 --apcs=interwork -I..\CORE -I..\HARDWARE -I..\STM32F03x_FWLib\inc -I..\STM32F03x_FWLib\src -I..\User -I..\SYSTEM -I "E:\SSJ Ŀ\SSJ Ŀ\\ʾ\\JC018_ STM32F030 UART -\JC018 STM32F030 UART\User\RTE" -I C:\Keil_v5\ARM\CMSIS\4.1.0\CMSIS\Include -D_RTE_ -DUSE_STDPERIPH_DRIVER -DSTM32F0XX -o ..\obj\stm32f0xx_it.o --omf_browse ..\obj\stm32f0xx_it.crf --depend ..\obj\stm32f0xx_it.d) +I (stm32f0xx_it.h)(0x574D3404) +I (stm32f0xx.h)(0x5C0F2083) +I (..\CORE\core_cm0.h)(0x574D3404) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44) +I (..\CORE\core_cmInstr.h)(0x574D3404) +I (..\CORE\core_cmFunc.h)(0x574D3404) +I (system_stm32f0xx.h)(0x574D3404) +I (stm32f0xx_conf.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_gpio.h)(0x574D3404) +I (..\User\stm32f0xx.h)(0x5C0F2083) +I (..\STM32F03x_FWLib\inc\stm32f0xx_rcc.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_usart.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_misc.h)(0x574D3404) +F (.\system_stm32f0xx.c)(0x574D3404)(-c --cpu Cortex-M0 -g -O0 --apcs=interwork -I..\CORE -I..\HARDWARE -I..\STM32F03x_FWLib\inc -I..\STM32F03x_FWLib\src -I..\User -I..\SYSTEM -I "E:\SSJ Ŀ\SSJ Ŀ\\ʾ\\JC018_ STM32F030 UART -\JC018 STM32F030 UART\User\RTE" -I C:\Keil_v5\ARM\CMSIS\4.1.0\CMSIS\Include -D_RTE_ -DUSE_STDPERIPH_DRIVER -DSTM32F0XX -o ..\obj\system_stm32f0xx.o --omf_browse ..\obj\system_stm32f0xx.crf --depend ..\obj\system_stm32f0xx.d) +I (stm32f0xx.h)(0x5C0F2083) +I (..\CORE\core_cm0.h)(0x574D3404) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44) +I (..\CORE\core_cmInstr.h)(0x574D3404) +I (..\CORE\core_cmFunc.h)(0x574D3404) +I (system_stm32f0xx.h)(0x574D3404) +I (stm32f0xx_conf.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_gpio.h)(0x574D3404) +I (..\User\stm32f0xx.h)(0x5C0F2083) +I (..\STM32F03x_FWLib\inc\stm32f0xx_rcc.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_usart.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_misc.h)(0x574D3404) +F (..\CORE\startup_stm32f0xx.s)(0x574D3404)(--cpu Cortex-M0 -g --apcs=interwork -I "E:\SSJ Ŀ\SSJ Ŀ\\ʾ\\JC018_ STM32F030 UART -\JC018 STM32F030 UART\User\RTE" -I C:\Keil_v5\ARM\CMSIS\4.1.0\CMSIS\Include --list .\startup_stm32f0xx.lst --xref -o ..\obj\startup_stm32f0xx.o --depend ..\obj\startup_stm32f0xx.d) +F (..\HARDWARE\led.c)(0x5D15B711)(-c --cpu Cortex-M0 -g -O0 --apcs=interwork -I..\CORE -I..\HARDWARE -I..\STM32F03x_FWLib\inc -I..\STM32F03x_FWLib\src -I..\User -I..\SYSTEM -I "E:\SSJ Ŀ\SSJ Ŀ\\ʾ\\JC018_ STM32F030 UART -\JC018 STM32F030 UART\User\RTE" -I C:\Keil_v5\ARM\CMSIS\4.1.0\CMSIS\Include -D_RTE_ -DUSE_STDPERIPH_DRIVER -DSTM32F0XX -o ..\obj\led.o --omf_browse ..\obj\led.crf --depend ..\obj\led.d) +I (..\HARDWARE\LED.h)(0x5D15B711) +I (..\User\stm32f0xx.h)(0x5C0F2083) +I (..\CORE\core_cm0.h)(0x574D3404) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44) +I (..\CORE\core_cmInstr.h)(0x574D3404) +I (..\CORE\core_cmFunc.h)(0x574D3404) +I (..\User\system_stm32f0xx.h)(0x574D3404) +I (..\User\stm32f0xx_conf.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_gpio.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_rcc.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_usart.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_misc.h)(0x574D3404) +F (..\HARDWARE\USART1.c)(0x5D15B711)(-c --cpu Cortex-M0 -g -O0 --apcs=interwork -I..\CORE -I..\HARDWARE -I..\STM32F03x_FWLib\inc -I..\STM32F03x_FWLib\src -I..\User -I..\SYSTEM -I "E:\SSJ Ŀ\SSJ Ŀ\\ʾ\\JC018_ STM32F030 UART -\JC018 STM32F030 UART\User\RTE" -I C:\Keil_v5\ARM\CMSIS\4.1.0\CMSIS\Include -D_RTE_ -DUSE_STDPERIPH_DRIVER -DSTM32F0XX -o ..\obj\usart1.o --omf_browse ..\obj\usart1.crf --depend ..\obj\usart1.d) +I (..\HARDWARE\USART1.h)(0x574D3404) +I (..\User\stm32f0xx.h)(0x5C0F2083) +I (..\CORE\core_cm0.h)(0x574D3404) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44) +I (..\CORE\core_cmInstr.h)(0x574D3404) +I (..\CORE\core_cmFunc.h)(0x574D3404) +I (..\User\system_stm32f0xx.h)(0x574D3404) +I (..\User\stm32f0xx_conf.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_gpio.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_rcc.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_usart.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_misc.h)(0x574D3404) +I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44) +F (..\HARDWARE\USART1_API.c)(0x574D3404)(-c --cpu Cortex-M0 -g -O0 --apcs=interwork -I..\CORE -I..\HARDWARE -I..\STM32F03x_FWLib\inc -I..\STM32F03x_FWLib\src -I..\User -I..\SYSTEM -I "E:\SSJ Ŀ\SSJ Ŀ\\ʾ\\JC018_ STM32F030 UART -\JC018 STM32F030 UART\User\RTE" -I C:\Keil_v5\ARM\CMSIS\4.1.0\CMSIS\Include -D_RTE_ -DUSE_STDPERIPH_DRIVER -DSTM32F0XX -o ..\obj\usart1_api.o --omf_browse ..\obj\usart1_api.crf --depend ..\obj\usart1_api.d) +I (..\HARDWARE\USART1.h)(0x574D3404) +I (..\User\stm32f0xx.h)(0x5C0F2083) +I (..\CORE\core_cm0.h)(0x574D3404) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44) +I (..\CORE\core_cmInstr.h)(0x574D3404) +I (..\CORE\core_cmFunc.h)(0x574D3404) +I (..\User\system_stm32f0xx.h)(0x574D3404) +I (..\User\stm32f0xx_conf.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_gpio.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_rcc.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_usart.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_misc.h)(0x574D3404) +I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x53463A44) +F (..\HARDWARE\Key.c)(0x5D15B711)(-c --cpu Cortex-M0 -g -O0 --apcs=interwork -I..\CORE -I..\HARDWARE -I..\STM32F03x_FWLib\inc -I..\STM32F03x_FWLib\src -I..\User -I..\SYSTEM -I "E:\SSJ Ŀ\SSJ Ŀ\\ʾ\\JC018_ STM32F030 UART -\JC018 STM32F030 UART\User\RTE" -I C:\Keil_v5\ARM\CMSIS\4.1.0\CMSIS\Include -D_RTE_ -DUSE_STDPERIPH_DRIVER -DSTM32F0XX -o ..\obj\key.o --omf_browse ..\obj\key.crf --depend ..\obj\key.d) +I (..\User\stm32f0xx.h)(0x5C0F2083) +I (..\CORE\core_cm0.h)(0x574D3404) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44) +I (..\CORE\core_cmInstr.h)(0x574D3404) +I (..\CORE\core_cmFunc.h)(0x574D3404) +I (..\User\system_stm32f0xx.h)(0x574D3404) +I (..\User\stm32f0xx_conf.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_gpio.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_rcc.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_usart.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_misc.h)(0x574D3404) +I (..\SYSTEM\delay.h)(0x574D3404) +F (..\SYSTEM\delay.c)(0x5D15B711)(-c --cpu Cortex-M0 -g -O0 --apcs=interwork -I..\CORE -I..\HARDWARE -I..\STM32F03x_FWLib\inc -I..\STM32F03x_FWLib\src -I..\User -I..\SYSTEM -I "E:\SSJ Ŀ\SSJ Ŀ\\ʾ\\JC018_ STM32F030 UART -\JC018 STM32F030 UART\User\RTE" -I C:\Keil_v5\ARM\CMSIS\4.1.0\CMSIS\Include -D_RTE_ -DUSE_STDPERIPH_DRIVER -DSTM32F0XX -o ..\obj\delay.o --omf_browse ..\obj\delay.crf --depend ..\obj\delay.d) +I (..\SYSTEM\delay.h)(0x574D3404) +I (..\User\stm32f0xx.h)(0x5C0F2083) +I (..\CORE\core_cm0.h)(0x574D3404) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44) +I (..\CORE\core_cmInstr.h)(0x574D3404) +I (..\CORE\core_cmFunc.h)(0x574D3404) +I (..\User\system_stm32f0xx.h)(0x574D3404) +I (..\User\stm32f0xx_conf.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_gpio.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_rcc.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_usart.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_misc.h)(0x574D3404) +F (..\STM32F03x_FWLib\src\stm32f0xx_gpio.c)(0x574D3404)(-c --cpu Cortex-M0 -g -O0 --apcs=interwork -I..\CORE -I..\HARDWARE -I..\STM32F03x_FWLib\inc -I..\STM32F03x_FWLib\src -I..\User -I..\SYSTEM -I "E:\SSJ Ŀ\SSJ Ŀ\\ʾ\\JC018_ STM32F030 UART -\JC018 STM32F030 UART\User\RTE" -I C:\Keil_v5\ARM\CMSIS\4.1.0\CMSIS\Include -D_RTE_ -DUSE_STDPERIPH_DRIVER -DSTM32F0XX -o ..\obj\stm32f0xx_gpio.o --omf_browse ..\obj\stm32f0xx_gpio.crf --depend ..\obj\stm32f0xx_gpio.d) +I (..\STM32F03x_FWLib\inc\stm32f0xx_gpio.h)(0x574D3404) +I (..\User\stm32f0xx.h)(0x5C0F2083) +I (..\CORE\core_cm0.h)(0x574D3404) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44) +I (..\CORE\core_cmInstr.h)(0x574D3404) +I (..\CORE\core_cmFunc.h)(0x574D3404) +I (..\User\system_stm32f0xx.h)(0x574D3404) +I (..\User\stm32f0xx_conf.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_rcc.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_usart.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_misc.h)(0x574D3404) +F (..\STM32F03x_FWLib\src\stm32f0xx_rcc.c)(0x574D3404)(-c --cpu Cortex-M0 -g -O0 --apcs=interwork -I..\CORE -I..\HARDWARE -I..\STM32F03x_FWLib\inc -I..\STM32F03x_FWLib\src -I..\User -I..\SYSTEM -I "E:\SSJ Ŀ\SSJ Ŀ\\ʾ\\JC018_ STM32F030 UART -\JC018 STM32F030 UART\User\RTE" -I C:\Keil_v5\ARM\CMSIS\4.1.0\CMSIS\Include -D_RTE_ -DUSE_STDPERIPH_DRIVER -DSTM32F0XX -o ..\obj\stm32f0xx_rcc.o --omf_browse ..\obj\stm32f0xx_rcc.crf --depend ..\obj\stm32f0xx_rcc.d) +I (..\STM32F03x_FWLib\inc\stm32f0xx_rcc.h)(0x574D3404) +I (..\User\stm32f0xx.h)(0x5C0F2083) +I (..\CORE\core_cm0.h)(0x574D3404) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44) +I (..\CORE\core_cmInstr.h)(0x574D3404) +I (..\CORE\core_cmFunc.h)(0x574D3404) +I (..\User\system_stm32f0xx.h)(0x574D3404) +I (..\User\stm32f0xx_conf.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_gpio.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_usart.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_misc.h)(0x574D3404) +F (..\STM32F03x_FWLib\src\stm32f0xx_misc.c)(0x574D3404)(-c --cpu Cortex-M0 -g -O0 --apcs=interwork -I..\CORE -I..\HARDWARE -I..\STM32F03x_FWLib\inc -I..\STM32F03x_FWLib\src -I..\User -I..\SYSTEM -I "E:\SSJ Ŀ\SSJ Ŀ\\ʾ\\JC018_ STM32F030 UART -\JC018 STM32F030 UART\User\RTE" -I C:\Keil_v5\ARM\CMSIS\4.1.0\CMSIS\Include -D_RTE_ -DUSE_STDPERIPH_DRIVER -DSTM32F0XX -o ..\obj\stm32f0xx_misc.o --omf_browse ..\obj\stm32f0xx_misc.crf --depend ..\obj\stm32f0xx_misc.d) +I (..\STM32F03x_FWLib\inc\stm32f0xx_misc.h)(0x574D3404) +I (..\User\stm32f0xx.h)(0x5C0F2083) +I (..\CORE\core_cm0.h)(0x574D3404) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44) +I (..\CORE\core_cmInstr.h)(0x574D3404) +I (..\CORE\core_cmFunc.h)(0x574D3404) +I (..\User\system_stm32f0xx.h)(0x574D3404) +I (..\User\stm32f0xx_conf.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_gpio.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_rcc.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_usart.h)(0x574D3404) +F (..\STM32F03x_FWLib\src\stm32f0xx_usart.c)(0x574D3404)(-c --cpu Cortex-M0 -g -O0 --apcs=interwork -I..\CORE -I..\HARDWARE -I..\STM32F03x_FWLib\inc -I..\STM32F03x_FWLib\src -I..\User -I..\SYSTEM -I "E:\SSJ Ŀ\SSJ Ŀ\\ʾ\\JC018_ STM32F030 UART -\JC018 STM32F030 UART\User\RTE" -I C:\Keil_v5\ARM\CMSIS\4.1.0\CMSIS\Include -D_RTE_ -DUSE_STDPERIPH_DRIVER -DSTM32F0XX -o ..\obj\stm32f0xx_usart.o --omf_browse ..\obj\stm32f0xx_usart.crf --depend ..\obj\stm32f0xx_usart.d) +I (..\STM32F03x_FWLib\inc\stm32f0xx_usart.h)(0x574D3404) +I (..\User\stm32f0xx.h)(0x5C0F2083) +I (..\CORE\core_cm0.h)(0x574D3404) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x53463A44) +I (..\CORE\core_cmInstr.h)(0x574D3404) +I (..\CORE\core_cmFunc.h)(0x574D3404) +I (..\User\system_stm32f0xx.h)(0x574D3404) +I (..\User\stm32f0xx_conf.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_gpio.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_rcc.h)(0x574D3404) +I (..\STM32F03x_FWLib\inc\stm32f0xx_misc.h)(0x574D3404) diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/STM32F030Demo_uvopt.bak b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/STM32F030Demo_uvopt.bak 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    ### uVision Project, (C) Keil Software
    + + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Stm32f030demo + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + + 0 + Quick Start Guide (STM32F030-Discovery) + d:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Boards/ST/STM32F030-Discovery/Documents/32F030DISCOVERY_QSG.pdf + + + 1 + Data Brief (STM32F030-Discovery) + d:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Boards/ST/STM32F030-Discovery/Documents/DM00092305.pdf + + + 2 + Schematics (STM32F030-Discovery) + d:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Boards/ST/STM32F030-Discovery/Documents/MB1134.pdf + + + 3 + STM32F030-Discovery Web Page (STM32F030-Discovery) + http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1848/PF259100 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 6 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U58009527 -O14 -S5 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F0xx_16.FLM -FS08000000 -FL04000 -FP0($$Device:STM32F030F4$Flash\STM32F0xx_16.FLM) + + + 0 + UL2CM3 + -S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F0xx_16 -FS08000000 -FL04000 -FP0($$Device:STM32F030F4$Flash\STM32F0xx_16.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + USER + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 1 + 0 + 0 + 0 + .\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + .\stm32f0xx_it.c + stm32f0xx_it.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + .\system_stm32f0xx.c + system_stm32f0xx.c + 0 + 0 + + + + + CORE + 0 + 0 + 0 + 0 + + 2 + 4 + 2 + 0 + 0 + 0 + 0 + ..\CORE\startup_stm32f0xx.s + startup_stm32f0xx.s + 0 + 0 + + + + + HARDWARE + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + 0 + ..\HARDWARE\led.c + led.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + 0 + ..\HARDWARE\USART1.c + USART1.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + 0 + ..\HARDWARE\USART1_API.c + USART1_API.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + 0 + ..\HARDWARE\Key.c + Key.c + 0 + 0 + + + + + SYSTEM + 0 + 0 + 0 + 0 + + 4 + 9 + 1 + 1 + 0 + 0 + 0 + ..\SYSTEM\delay.c + delay.c + 0 + 0 + + + + + STM32F03x_FWLib + 1 + 0 + 0 + 0 + + 5 + 10 + 1 + 0 + 0 + 0 + 0 + ..\STM32F03x_FWLib\src\stm32f0xx_gpio.c + stm32f0xx_gpio.c + 0 + 0 + + + 5 + 11 + 1 + 0 + 0 + 0 + 0 + ..\STM32F03x_FWLib\src\stm32f0xx_rcc.c + stm32f0xx_rcc.c + 0 + 0 + + + 5 + 12 + 1 + 0 + 0 + 0 + 0 + ..\STM32F03x_FWLib\src\stm32f0xx_misc.c + stm32f0xx_misc.c + 0 + 0 + + + 5 + 13 + 1 + 0 + 0 + 0 + 0 + ..\STM32F03x_FWLib\src\stm32f0xx_usart.c + stm32f0xx_usart.c + 0 + 0 + + + +     diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/STM32F030Demo_uvoptx.bak b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/STM32F030Demo_uvoptx.bak new file mode 100644 index 0000000..30a6e90 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/STM32F030Demo_uvoptx.bak @@ -0,0 +1,386 @@ + + + + 1.0 + +
    ### uVision Project, (C) Keil Software
    + + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Stm32f030demo + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + + 0 + STM32F0-Discovery Web Page (STM32F0-Discovery) + http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1848/PF253215 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 6 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F0xx_16 -FS08000000 -FL04000 -FP0($$Device:STM32F030F4$CMSIS\Flash\STM32F0xx_16.FLM)) + + + 0 + JL2CM3 + -U58009527 -O14 -S5 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F0xx_16.FLM -FS08000000 -FL04000 -FP0($$Device:STM32F030F4$CMSIS\Flash\STM32F0xx_16.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + USER + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 1 + 0 + 0 + .\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 1 + 0 + 0 + .\stm32f0xx_it.c + stm32f0xx_it.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 1 + 0 + 0 + .\system_stm32f0xx.c + system_stm32f0xx.c + 0 + 0 + + + + + CORE + 0 + 0 + 0 + 0 + + 2 + 4 + 2 + 0 + 1 + 0 + 0 + ..\CORE\startup_stm32f0xx.s + startup_stm32f0xx.s + 0 + 0 + + + + + HARDWARE + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 1 + 0 + 0 + ..\HARDWARE\led.c + led.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 1 + 0 + 0 + ..\HARDWARE\USART1.c + USART1.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 1 + 0 + 0 + ..\HARDWARE\USART1_API.c + USART1_API.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 1 + 0 + 0 + ..\HARDWARE\Key.c + Key.c + 0 + 0 + + + + + SYSTEM + 0 + 0 + 0 + 0 + + 4 + 9 + 1 + 1 + 1 + 0 + 0 + ..\SYSTEM\delay.c + delay.c + 0 + 0 + + + + + STM32F03x_FWLib + 1 + 0 + 0 + 0 + + 5 + 10 + 1 + 0 + 1 + 0 + 0 + ..\STM32F03x_FWLib\src\stm32f0xx_gpio.c + stm32f0xx_gpio.c + 0 + 0 + + + 5 + 11 + 1 + 0 + 1 + 0 + 0 + ..\STM32F03x_FWLib\src\stm32f0xx_rcc.c + stm32f0xx_rcc.c + 0 + 0 + + + 5 + 12 + 1 + 0 + 1 + 0 + 0 + ..\STM32F03x_FWLib\src\stm32f0xx_misc.c + stm32f0xx_misc.c + 0 + 0 + + + 5 + 13 + 1 + 0 + 1 + 0 + 0 + ..\STM32F03x_FWLib\src\stm32f0xx_usart.c + stm32f0xx_usart.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + +     diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/STM32F030Demo_uvproj.bak b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/STM32F030Demo_uvproj.bak new file mode 100644 index 0000000..0b81ac6 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/STM32F030Demo_uvproj.bak @@ -0,0 +1,488 @@ + + + + 1.1 + +
    ### uVision Project, (C) Keil Software
    + + + + Stm32f030demo + 0x4 + ARM-ADS + + + STM32F030F4 + STMicroelectronics + IROM(0x08000000,0x4000) IRAM(0x20000000,0x1000) CPUTYPE("Cortex-M0") CLOCK(48000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F0xx_16 -FS08000000 -FL04000 -FP0($$Device:STM32F030F4$Flash\STM32F0xx_16.FLM)) + 7305 + $$Device:STM32F030F4$Device\Include\stm32f0xx.h + + + + + + + + + + $$Device:STM32F030F4$SVD\STM32F030.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + ..\OBJ\ + STM32F030Demo + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + + 0 + 6 + + + + + + + + + + + + + + Segger\JL2CM3.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x1000 + + + 1 + 0x8000000 + 0x4000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x4000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x1000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + USE_STDPERIPH_DRIVER STM32F0XX + + ..\CORE;..\HARDWARE;..\STM32F03x_FWLib\inc;..\STM32F03x_FWLib\src;..\User;..\SYSTEM + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + USER + + + main.c + 1 + .\main.c + + + stm32f0xx_it.c + 1 + .\stm32f0xx_it.c + + + system_stm32f0xx.c + 1 + .\system_stm32f0xx.c + + + + + CORE + + + startup_stm32f0xx.s + 2 + ..\CORE\startup_stm32f0xx.s + + + + + HARDWARE + + + led.c + 1 + ..\HARDWARE\led.c + + + USART1.c + 1 + ..\HARDWARE\USART1.c + + + + + SYSTEM + + + delay.c + 1 + ..\SYSTEM\delay.c + + + + + STM32F03x_FWLib + + + stm32f0xx_gpio.c + 1 + ..\STM32F03x_FWLib\src\stm32f0xx_gpio.c + + + stm32f0xx_rcc.c + 1 + ..\STM32F03x_FWLib\src\stm32f0xx_rcc.c + + + stm32f0xx_misc.c + 1 + ..\STM32F03x_FWLib\src\stm32f0xx_misc.c + + + stm32f0xx_usart.c + 1 + ..\STM32F03x_FWLib\src\stm32f0xx_usart.c + + + + + + + +     diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/STM32F030Demo_uvprojx.bak b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/STM32F030Demo_uvprojx.bak new file mode 100644 index 0000000..67c26dc --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/STM32F030Demo_uvprojx.bak @@ -0,0 +1,491 @@ + + + + 2.1 + +
    ### uVision Project, (C) Keil Software
    + + + + Stm32f030demo + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + STM32F030F4 + STMicroelectronics + Keil.STM32F0xx_DFP.2.0.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00001000) IROM(0x08000000,0x00004000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F0xx_16 -FS08000000 -FL04000 -FP0($$Device:STM32F030F4$CMSIS\Flash\STM32F0xx_16.FLM)) + 7305 + $$Device:STM32F030F4$Drivers\CMSIS\Device\ST\STM32F0xx\Include\stm32f0xx.h + + + + + + + -DSTM32F030 + + + $$Device:STM32F030F4$CMSIS\SVD\STM32F0x0.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + ..\OBJ\ + STM32F030Demo + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x1000 + + + 1 + 0x8000000 + 0x4000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x4000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x1000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + USE_STDPERIPH_DRIVER STM32F0XX + + ..\CORE;..\HARDWARE;..\STM32F03x_FWLib\inc;..\STM32F03x_FWLib\src;..\User;..\SYSTEM + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + USER + + + main.c + 1 + .\main.c + + + stm32f0xx_it.c + 1 + .\stm32f0xx_it.c + + + system_stm32f0xx.c + 1 + .\system_stm32f0xx.c + + + + + CORE + + + startup_stm32f0xx.s + 2 + ..\CORE\startup_stm32f0xx.s + + + + + HARDWARE + + + led.c + 1 + ..\HARDWARE\led.c + + + USART1.c + 1 + ..\HARDWARE\USART1.c + + + USART1_API.c + 1 + ..\HARDWARE\USART1_API.c + + + Key.c + 1 + ..\HARDWARE\Key.c + + + + + SYSTEM + + + delay.c + 1 + ..\SYSTEM\delay.c + + + + + STM32F03x_FWLib + + + stm32f0xx_gpio.c + 1 + ..\STM32F03x_FWLib\src\stm32f0xx_gpio.c + + + stm32f0xx_rcc.c + 1 + ..\STM32F03x_FWLib\src\stm32f0xx_rcc.c + + + stm32f0xx_misc.c + 1 + ..\STM32F03x_FWLib\src\stm32f0xx_misc.c + + + stm32f0xx_usart.c + 1 + ..\STM32F03x_FWLib\src\stm32f0xx_usart.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + +     diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/TEST.map b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/TEST.map new file mode 100644 index 0000000..1cec9f2 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/TEST.map @@ -0,0 +1,896 @@ +Component: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed] + +============================================================================== + +Section Cross References + + main.o(.text) refers to _printf_pad.o(.text) for _printf_pre_padding + main.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + main.o(.text) refers to _printf_d.o(.ARM.Collect$$_printf_percent$$00000009) for _printf_d + main.o(.text) refers to _printf_dec.o(.text) for _printf_int_dec + main.o(.text) refers to delay.o(.text) for delay_init + main.o(.text) refers to usart1.o(.text) for USART1_Init + main.o(.text) refers to noretval__2sprintf.o(.text) for __2sprintf + system_stm32f0xx.o(.text) refers to aeabi_sdiv.o(.text) for __aeabi_uidivmod + system_stm32f0xx.o(.text) refers to system_stm32f0xx.o(.data) for SystemCoreClock + startup_stm32f0xx.o(STACK) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32f0xx.o(HEAP) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32f0xx.o(RESET) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32f0xx.o(RESET) refers to startup_stm32f0xx.o(STACK) for __initial_sp + startup_stm32f0xx.o(RESET) refers to startup_stm32f0xx.o(.text) for Reset_Handler + startup_stm32f0xx.o(RESET) refers to stm32f0xx_it.o(.text) for NMI_Handler + startup_stm32f0xx.o(RESET) refers to usart1.o(.text) for USART1_IRQHandler + startup_stm32f0xx.o(.text) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32f0xx.o(.text) refers to system_stm32f0xx.o(.text) for SystemInit + startup_stm32f0xx.o(.text) refers to __main.o(!!!main) for __main + startup_stm32f0xx.o(.text) refers to startup_stm32f0xx.o(HEAP) for Heap_Mem + startup_stm32f0xx.o(.text) refers to startup_stm32f0xx.o(STACK) for Stack_Mem + usart1.o(.emb_text) refers (Special) to use_no_semi_2.o(.text) for __use_no_semihosting + usart1.o(.text) refers (Special) to use_no_semi_2.o(.text) for __use_no_semihosting + usart1.o(.text) refers to stm32f0xx_rcc.o(.text) for RCC_AHBPeriphClockCmd + usart1.o(.text) refers to stm32f0xx_gpio.o(.text) for GPIO_PinAFConfig + usart1.o(.text) refers to stm32f0xx_usart.o(.text) for USART_Init + usart1.o(.text) refers to stm32f0xx_misc.o(.text) for NVIC_Init + usart1.o(.text) refers to usart1.o(.data) for ok + usart1.o(.text) refers to usart1.o(.bss) for rch + usart1.o(.bss) refers (Special) to use_no_semi_2.o(.text) for __use_no_semihosting + usart1.o(.data) refers (Special) to use_no_semi_2.o(.text) for __use_no_semihosting + delay.o(.text) refers to stm32f0xx_misc.o(.text) for SysTick_CLKSourceConfig + delay.o(.text) refers to aeabi_sdiv.o(.text) for __aeabi_uidivmod + delay.o(.text) refers to system_stm32f0xx.o(.data) for SystemCoreClock + delay.o(.text) refers to delay.o(.data) for fac_us + stm32f0xx_gpio.o(.text) refers to stm32f0xx_rcc.o(.text) for RCC_AHBPeriphResetCmd + stm32f0xx_rcc.o(.text) refers to aeabi_sdiv.o(.text) for __aeabi_uidivmod + stm32f0xx_rcc.o(.text) refers to stm32f0xx_rcc.o(.data) for APBAHBPrescTable + stm32f0xx_usart.o(.text) refers to stm32f0xx_rcc.o(.text) for RCC_APB2PeriphResetCmd + stm32f0xx_usart.o(.text) refers to aeabi_sdiv.o(.text) for __aeabi_uidivmod + use_no_semi_2.o(.text) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi + __2sprintf.o(.text) refers to _printf_char_common.o(.text) for _printf_char_common + __2sprintf.o(.text) refers to _sputc.o(.text) for _sputc + noretval__2sprintf.o(.text) refers to _printf_char_common.o(.text) for _printf_char_common + noretval__2sprintf.o(.text) refers to _sputc.o(.text) for _sputc + __printf.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + _printf_dec.o(.text) refers to rtudiv10.o(.text) for __rt_udiv10 + _printf_dec.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + __printf_flags.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags.o(.text) refers to __printf_flags.o(.constdata) for .constdata + __printf_ss.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_ss.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_ss.o(.text) refers to __printf_flags_ss.o(.constdata) for .constdata + __printf_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit + __printf_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit + __printf_flags_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_wp.o(.text) refers to __printf_flags_wp.o(.constdata) for .constdata + __printf_ss_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit + __printf_ss_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_ss_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit + __printf_flags_ss_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_ss_wp.o(.text) refers to __printf_flags_ss_wp.o(.constdata) for .constdata + _printf_d.o(.ARM.Collect$$_printf_percent$$00000009) refers (Weak) to _printf_dec.o(.text) for _printf_int_dec + _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) refers (Special) to _printf_percent_end.o(.ARM.Collect$$_printf_percent$$00000017) for _printf_percent_end + __main.o(!!!main) refers to __rtentry.o(.ARM.Collect$$rtentry$$00000000) for __rt_entry + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for __rt_entry_li + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for __rt_entry_main + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000C) for __rt_entry_postli_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000009) for __rt_entry_postsh_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000002) for __rt_entry_presh_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for __rt_entry_sh + aeabi_idiv0_sigfpe.o(.text) refers to rt_div0.o(.text) for __rt_div0 + _printf_intcommon.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_intcommon.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_intcommon.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_post_padding + _printf_char_common.o(.text) refers to __printf_wp.o(.text) for __printf + __rtentry2.o(.ARM.Collect$$rtentry$$00000008) refers to boardinit2.o(.text) for _platform_post_stackheap_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) refers to libinit.o(.ARM.Collect$$libinit$$00000000) for __rt_lib_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) refers to boardinit3.o(.text) for _platform_post_lib_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to main.o(.text) for main + __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to exit.o(.text) for exit + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000001) for .ARM.Collect$$rtentry$$00000001 + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000008) for .ARM.Collect$$rtentry$$00000008 + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for .ARM.Collect$$rtentry$$0000000A + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) for .ARM.Collect$$rtentry$$0000000B + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for .ARM.Collect$$rtentry$$0000000D + __rtentry4.o(.ARM.Collect$$rtentry$$00000004) refers to sys_stackheap_outer.o(.text) for __user_setup_stackheap + __rtentry4.o(.ARM.exidx) refers to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for .ARM.Collect$$rtentry$$00000004 + rt_div0.o(.text) refers to defsig_fpe_outer.o(.text) for __rt_SIGFPE + sys_stackheap_outer.o(.text) refers to libspace.o(.text) for __user_perproc_libspace + sys_stackheap_outer.o(.text) refers to startup_stm32f0xx.o(.text) for __user_initial_stackheap + sys_stackheap_outer.o(__vectab_stack_and_reset_area) refers to tempstk.o(.text) for __temporary_stack_top + sys_stackheap_outer.o(__vectab_stack_and_reset_area) refers to __main.o(!!!main) for __main + exit.o(.text) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for __rt_exit + defsig_fpe_outer.o(.text) refers to defsig_fpe_inner.o(.text) for __rt_SIGFPE_inner + defsig_fpe_outer.o(.text) refers to defsig_exit.o(.text) for __sig_exit + defsig_fpe_formal.o(.text) refers to rt_raise.o(.text) for __rt_raise + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002E) for __rt_lib_init_alloca_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002C) for __rt_lib_init_argv_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001B) for __rt_lib_init_atexit_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000021) for __rt_lib_init_clock_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000032) for __rt_lib_init_cpp_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000030) for __rt_lib_init_exceptions_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000002) for __rt_lib_init_fp_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001F) for __rt_lib_init_fp_trap_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000023) for __rt_lib_init_getenv_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000A) for __rt_lib_init_heap_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000011) for __rt_lib_init_lc_collate_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000013) for __rt_lib_init_lc_ctype_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000015) for __rt_lib_init_lc_monetary_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000017) for __rt_lib_init_lc_numeric_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000019) for __rt_lib_init_lc_time_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000004) for __rt_lib_init_preinit_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000E) for __rt_lib_init_rand_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000033) for __rt_lib_init_return + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001D) for __rt_lib_init_signal_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000025) for __rt_lib_init_stdio_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000C) for __rt_lib_init_user_alloc_1 + libspace.o(.text) refers to libspace.o(.bss) for __libspace_start + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1 + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1 + rtexit.o(.ARM.exidx) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for .ARM.Collect$$rtexit$$00000000 + rt_raise.o(.text) refers to __raise.o(.text) for __raise + rt_raise.o(.text) refers to usart1.o(.text) for _sys_exit + defsig_exit.o(.text) refers to usart1.o(.text) for _sys_exit + defsig_fpe_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + libinit2.o(.ARM.Collect$$libinit$$00000010) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000012) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000014) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000016) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000018) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000026) refers to argv_veneer.o(.text) for __ARM_argv_veneer + libinit2.o(.ARM.Collect$$libinit$$00000027) refers to argv_veneer.o(.text) for __ARM_argv_veneer + rtexit2.o(.ARM.Collect$$rtexit$$00000003) refers to libshutdown.o(.ARM.Collect$$libshutdown$$00000000) for __rt_lib_shutdown + rtexit2.o(.ARM.Collect$$rtexit$$00000004) refers to usart1.o(.text) for _sys_exit + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000001) for .ARM.Collect$$rtexit$$00000001 + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for .ARM.Collect$$rtexit$$00000003 + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for .ARM.Collect$$rtexit$$00000004 + __raise.o(.text) refers to defsig.o(CL$$defsig) for __default_signal_handler + defsig_general.o(.text) refers to sys_wrch.o(.text) for _ttywrch + sys_wrch.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_wrch.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + defsig.o(CL$$defsig) refers to defsig_fpe_inner.o(.text) for __rt_SIGFPE_inner + defsig.o(CL$$defsig) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner + _get_argv_nomalloc.o(.text) refers (Special) to hrguard.o(.text) for __heap_region$guard + _get_argv_nomalloc.o(.text) refers to defsig_rtmem_outer.o(.text) for __rt_SIGRTMEM + _get_argv_nomalloc.o(.text) refers to sys_command.o(.text) for _sys_command_string + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000002) for __rt_lib_shutdown_cpp_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000007) for __rt_lib_shutdown_fp_trap_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F) for __rt_lib_shutdown_heap_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000010) for __rt_lib_shutdown_return + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A) for __rt_lib_shutdown_signal_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000004) for __rt_lib_shutdown_stdio_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C) for __rt_lib_shutdown_user_alloc_1 + sys_command.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_command.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + defsig_abrt_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_rtred_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_rtmem_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_rtmem_outer.o(.text) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner + defsig_rtmem_outer.o(.text) refers to defsig_exit.o(.text) for __sig_exit + defsig_rtmem_formal.o(.text) refers to rt_raise.o(.text) for __rt_raise + defsig_stak_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_pvfn_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_cppl_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_segv_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_other.o(.text) refers to defsig_general.o(.text) for __default_signal_display + + +============================================================================== + +Removing Unused input sections from the image. + + Removing main.o(.emb_text), (8 bytes). + Removing stm32f0xx_it.o(.emb_text), (8 bytes). + Removing system_stm32f0xx.o(.emb_text), (8 bytes). + Removing usart1.o(.emb_text), (8 bytes). + Removing delay.o(.emb_text), (8 bytes). + Removing stm32f0xx_gpio.o(.emb_text), (8 bytes). + Removing stm32f0xx_rcc.o(.emb_text), (8 bytes). + Removing stm32f0xx_misc.o(.emb_text), (8 bytes). + Removing stm32f0xx_usart.o(.emb_text), (8 bytes). + +9 unused section(s) (total 72 bytes) removed from the image. + +============================================================================== + +Image Symbol Table + + Local Symbols + + Symbol Name Value Ov Type Size Object(Section) + + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit3.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit2.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit1.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardshut.o ABSOLUTE + ../clib/angel/handlers.s 0x00000000 Number 0 __scatter_zi.o ABSOLUTE + ../clib/angel/handlers.s 0x00000000 Number 0 __scatter_copy.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry2.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 rtexit2.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry4.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 rtexit.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 rt_raise.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 aeabi_idiv0_sigfpe.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 aeabi_idiv0.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 rt_div0.o ABSOLUTE + ../clib/angel/scatterp.s 0x00000000 Number 0 __scatter.o ABSOLUTE + ../clib/angel/startup.s 0x00000000 Number 0 __main.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 libspace.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 tempstk.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 use_no_semi_2.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 indicate_semi.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 use_no_semi.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 sys_stackheap_outer.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_command.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_wrch.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 no_argv.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 _get_argv_nomalloc.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 argv_veneer.o ABSOLUTE + ../clib/division.c 0x00000000 Number 0 rtudiv10.o ABSOLUTE + ../clib/division.s 0x00000000 Number 0 aeabi_sdiv.o ABSOLUTE + ../clib/division.s 0x00000000 Number 0 aeabi_sdiv_div0.o ABSOLUTE + ../clib/heapalloc.c 0x00000000 Number 0 hrguard.o ABSOLUTE + ../clib/heapaux.c 0x00000000 Number 0 heapauxi.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libinit.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libinit2.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libshutdown.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libshutdown2.o ABSOLUTE + ../clib/misc.s 0x00000000 Number 0 printf_stubs.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_ss.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_flags_ss.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_wp.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_flags_wp.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_flags_ss_wp.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_intcommon.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_char_common.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_nopercent.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _sputc.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __2sprintf.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 noretval__2sprintf.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_ss_wp.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_pad.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_dec.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_flags.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_d.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_percent.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_percent_end.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_fpe_formal.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_segv_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_stak_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtmem_formal.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtmem_outer.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_other.o 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__arm_preinit_ - Undefined Weak Reference + __cpp_initialize__aeabi_ - Undefined Weak Reference + __cxa_finalize - Undefined Weak Reference + __rt_locale - Undefined Weak Reference + __sigvec_lookup - Undefined Weak Reference + _atexit_init - Undefined Weak Reference + _call_atexit_fns - Undefined Weak Reference + _clock_init - Undefined Weak Reference + _fp_trap_init - Undefined Weak Reference + _fp_trap_shutdown - Undefined Weak Reference + _get_lc_collate - Undefined Weak Reference + _get_lc_ctype - Undefined Weak Reference + _get_lc_monetary - Undefined Weak Reference + _get_lc_numeric - Undefined Weak Reference + _get_lc_time - Undefined Weak Reference + _getenv_init - Undefined Weak Reference + _handle_redirection - Undefined Weak Reference + _init_alloc - Undefined Weak Reference + _init_user_alloc - Undefined Weak Reference + _initio - Undefined Weak Reference + _printf_truncate_signed - Undefined Weak Reference + _printf_truncate_unsigned - Undefined Weak Reference + _rand_init - Undefined Weak Reference + _signal_finish - Undefined Weak Reference + _signal_init - Undefined Weak Reference + _terminate_alloc - Undefined Weak Reference + _terminate_user_alloc - Undefined Weak Reference + _terminateio - Undefined Weak Reference + __Vectors_Size 0x000000c0 Number 0 startup_stm32f0xx.o ABSOLUTE + __Vectors 0x08000000 Data 4 startup_stm32f0xx.o(RESET) + __Vectors_End 0x080000c0 Data 0 startup_stm32f0xx.o(RESET) + __main 0x080000c1 Thumb Code 8 __main.o(!!!main) + __scatterload 0x080000c9 Thumb Code 0 __scatter.o(!!!scatter) + __scatterload_rt2 0x080000c9 Thumb Code 52 __scatter.o(!!!scatter) + __scatterload_rt2_thumb_only 0x080000c9 Thumb Code 0 __scatter.o(!!!scatter) + __scatterload_null 0x080000d9 Thumb Code 0 __scatter.o(!!!scatter) + __scatterload_copy 0x08000105 Thumb Code 26 __scatter_copy.o(!!handler_copy) + __scatterload_zeroinit 0x08000121 Thumb Code 28 __scatter_zi.o(!!handler_zi) + _printf_percent 0x0800013d Thumb Code 0 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DMA1_Channel4_5_IRQHandler 0x08000aab Thumb Code 0 startup_stm32f0xx.o(.text) + EXTI0_1_IRQHandler 0x08000aab Thumb Code 0 startup_stm32f0xx.o(.text) + EXTI2_3_IRQHandler 0x08000aab Thumb Code 0 startup_stm32f0xx.o(.text) + EXTI4_15_IRQHandler 0x08000aab Thumb Code 0 startup_stm32f0xx.o(.text) + FLASH_IRQHandler 0x08000aab Thumb Code 0 startup_stm32f0xx.o(.text) + I2C1_IRQHandler 0x08000aab Thumb Code 0 startup_stm32f0xx.o(.text) + I2C2_IRQHandler 0x08000aab Thumb Code 0 startup_stm32f0xx.o(.text) + PVD_IRQHandler 0x08000aab Thumb Code 0 startup_stm32f0xx.o(.text) + RCC_IRQHandler 0x08000aab Thumb Code 0 startup_stm32f0xx.o(.text) + RTC_IRQHandler 0x08000aab Thumb Code 0 startup_stm32f0xx.o(.text) + SPI1_IRQHandler 0x08000aab Thumb Code 0 startup_stm32f0xx.o(.text) + SPI2_IRQHandler 0x08000aab Thumb Code 0 startup_stm32f0xx.o(.text) + TIM14_IRQHandler 0x08000aab Thumb Code 0 startup_stm32f0xx.o(.text) + TIM15_IRQHandler 0x08000aab Thumb Code 0 startup_stm32f0xx.o(.text) + TIM16_IRQHandler 0x08000aab Thumb Code 0 startup_stm32f0xx.o(.text) + TIM17_IRQHandler 0x08000aab Thumb Code 0 startup_stm32f0xx.o(.text) + TIM1_BRK_UP_TRG_COM_IRQHandler 0x08000aab Thumb Code 0 startup_stm32f0xx.o(.text) + TIM1_CC_IRQHandler 0x08000aab Thumb Code 0 startup_stm32f0xx.o(.text) + TIM2_IRQHandler 0x08000aab Thumb Code 0 startup_stm32f0xx.o(.text) + TIM3_IRQHandler 0x08000aab Thumb Code 0 startup_stm32f0xx.o(.text) + TIM6_DAC_IRQHandler 0x08000aab Thumb Code 0 startup_stm32f0xx.o(.text) + TS_IRQHandler 0x08000aab Thumb Code 0 startup_stm32f0xx.o(.text) + USART2_IRQHandler 0x08000aab Thumb Code 0 startup_stm32f0xx.o(.text) + WWDG_IRQHandler 0x08000aab Thumb Code 0 startup_stm32f0xx.o(.text) + __user_initial_stackheap 0x08000aad Thumb Code 0 startup_stm32f0xx.o(.text) + _sys_exit 0x08000ad1 Thumb Code 4 usart1.o(.text) + fputc 0x08000ad5 Thumb Code 22 usart1.o(.text) + USART1_Init 0x08000aeb Thumb Code 168 usart1.o(.text) + UartGet 0x08000b93 Thumb Code 26 usart1.o(.text) + CheckBusy 0x08000bad Thumb Code 24 usart1.o(.text) + get_var 0x08000bc5 Thumb Code 76 usart1.o(.text) + getch 0x08000c11 Thumb Code 186 usart1.o(.text) + GetValue 0x08000ccb Thumb Code 608 usart1.o(.text) + UartSend 0x08000f2b Thumb Code 44 usart1.o(.text) + USART1_IRQHandler 0x08000f57 Thumb Code 32 usart1.o(.text) + delay_init 0x08000f89 Thumb Code 44 delay.o(.text) + delay_us 0x08000fb5 Thumb Code 74 delay.o(.text) + delay_ms 0x08000fff Thumb Code 74 delay.o(.text) + GPIO_DeInit 0x0800105d Thumb Code 132 stm32f0xx_gpio.o(.text) + GPIO_Init 0x080010e1 Thumb Code 144 stm32f0xx_gpio.o(.text) + GPIO_StructInit 0x08001171 Thumb Code 20 stm32f0xx_gpio.o(.text) + GPIO_PinLockConfig 0x08001185 Thumb Code 34 stm32f0xx_gpio.o(.text) + GPIO_ReadInputDataBit 0x080011a7 Thumb Code 20 stm32f0xx_gpio.o(.text) + GPIO_ReadInputData 0x080011bb Thumb Code 6 stm32f0xx_gpio.o(.text) + GPIO_ReadOutputDataBit 0x080011c1 Thumb Code 20 stm32f0xx_gpio.o(.text) + GPIO_ReadOutputData 0x080011d5 Thumb Code 6 stm32f0xx_gpio.o(.text) + GPIO_SetBits 0x080011db Thumb Code 4 stm32f0xx_gpio.o(.text) + GPIO_ResetBits 0x080011df Thumb Code 4 stm32f0xx_gpio.o(.text) + GPIO_WriteBit 0x080011e3 Thumb Code 12 stm32f0xx_gpio.o(.text) + GPIO_Write 0x080011ef Thumb Code 4 stm32f0xx_gpio.o(.text) + GPIO_PinAFConfig 0x080011f3 Thumb Code 68 stm32f0xx_gpio.o(.text) + RCC_DeInit 0x0800124d Thumb Code 104 stm32f0xx_rcc.o(.text) + RCC_HSEConfig 0x080012b5 Thumb Code 12 stm32f0xx_rcc.o(.text) + RCC_GetFlagStatus 0x080012c1 Thumb Code 68 stm32f0xx_rcc.o(.text) + RCC_WaitForHSEStartUp 0x08001305 Thumb Code 60 stm32f0xx_rcc.o(.text) + RCC_AdjustHSICalibrationValue 0x08001341 Thumb Code 26 stm32f0xx_rcc.o(.text) + RCC_HSICmd 0x0800135b Thumb Code 32 stm32f0xx_rcc.o(.text) + RCC_AdjustHSI14CalibrationValue 0x0800137b Thumb Code 26 stm32f0xx_rcc.o(.text) + RCC_HSI14Cmd 0x08001395 Thumb Code 32 stm32f0xx_rcc.o(.text) + RCC_HSI14ADCRequestCmd 0x080013b5 Thumb Code 32 stm32f0xx_rcc.o(.text) + RCC_LSEConfig 0x080013d5 Thumb Code 34 stm32f0xx_rcc.o(.text) + RCC_LSEDriveConfig 0x080013f7 Thumb Code 22 stm32f0xx_rcc.o(.text) + RCC_LSICmd 0x0800140d Thumb Code 32 stm32f0xx_rcc.o(.text) + RCC_PLLConfig 0x0800142d Thumb Code 30 stm32f0xx_rcc.o(.text) + RCC_PLLCmd 0x0800144b Thumb Code 36 stm32f0xx_rcc.o(.text) + RCC_PREDIV1Config 0x0800146f Thumb Code 24 stm32f0xx_rcc.o(.text) + RCC_ClockSecuritySystemCmd 0x08001487 Thumb Code 36 stm32f0xx_rcc.o(.text) + RCC_MCOConfig 0x080014ab Thumb Code 6 stm32f0xx_rcc.o(.text) + RCC_SYSCLKConfig 0x080014b1 Thumb Code 24 stm32f0xx_rcc.o(.text) + RCC_GetSYSCLKSource 0x080014c9 Thumb Code 10 stm32f0xx_rcc.o(.text) + RCC_HCLKConfig 0x080014d3 Thumb Code 28 stm32f0xx_rcc.o(.text) + RCC_PCLKConfig 0x080014ef Thumb Code 30 stm32f0xx_rcc.o(.text) + RCC_ADCCLKConfig 0x0800150d Thumb Code 52 stm32f0xx_rcc.o(.text) + RCC_CECCLKConfig 0x08001541 Thumb Code 22 stm32f0xx_rcc.o(.text) + RCC_I2CCLKConfig 0x08001557 Thumb Code 22 stm32f0xx_rcc.o(.text) + RCC_USARTCLKConfig 0x0800156d Thumb Code 22 stm32f0xx_rcc.o(.text) + RCC_GetClocksFreq 0x08001583 Thumb Code 368 stm32f0xx_rcc.o(.text) + RCC_RTCCLKConfig 0x080016f3 Thumb Code 12 stm32f0xx_rcc.o(.text) + RCC_RTCCLKCmd 0x080016ff Thumb Code 36 stm32f0xx_rcc.o(.text) + RCC_BackupResetCmd 0x08001723 Thumb Code 36 stm32f0xx_rcc.o(.text) + RCC_AHBPeriphClockCmd 0x08001747 Thumb Code 28 stm32f0xx_rcc.o(.text) + RCC_APB2PeriphClockCmd 0x08001763 Thumb Code 28 stm32f0xx_rcc.o(.text) + RCC_APB1PeriphClockCmd 0x0800177f Thumb Code 28 stm32f0xx_rcc.o(.text) + RCC_AHBPeriphResetCmd 0x0800179b Thumb Code 28 stm32f0xx_rcc.o(.text) + RCC_APB2PeriphResetCmd 0x080017b7 Thumb Code 28 stm32f0xx_rcc.o(.text) + RCC_APB1PeriphResetCmd 0x080017d3 Thumb Code 28 stm32f0xx_rcc.o(.text) + RCC_ITConfig 0x080017ef Thumb Code 28 stm32f0xx_rcc.o(.text) + RCC_ClearFlag 0x0800180b Thumb Code 16 stm32f0xx_rcc.o(.text) + RCC_GetITStatus 0x0800181b Thumb Code 22 stm32f0xx_rcc.o(.text) + RCC_ClearITPendingBit 0x08001831 Thumb Code 6 stm32f0xx_rcc.o(.text) + NVIC_Init 0x08001845 Thumb Code 106 stm32f0xx_misc.o(.text) + NVIC_SystemLPConfig 0x080018af Thumb Code 28 stm32f0xx_misc.o(.text) + SysTick_CLKSourceConfig 0x080018cb Thumb Code 32 stm32f0xx_misc.o(.text) + USART_DeInit 0x080018f9 Thumb Code 56 stm32f0xx_usart.o(.text) + USART_Init 0x08001931 Thumb Code 234 stm32f0xx_usart.o(.text) + USART_StructInit 0x08001a1b Thumb Code 24 stm32f0xx_usart.o(.text) + USART_ClockInit 0x08001a33 Thumb Code 36 stm32f0xx_usart.o(.text) + USART_ClockStructInit 0x08001a57 Thumb Code 12 stm32f0xx_usart.o(.text) + USART_Cmd 0x08001a63 Thumb Code 24 stm32f0xx_usart.o(.text) + USART_DirectionModeCmd 0x08001a7b Thumb Code 20 stm32f0xx_usart.o(.text) + USART_OverSampling8Cmd 0x08001a8f Thumb Code 28 stm32f0xx_usart.o(.text) + USART_OneBitMethodCmd 0x08001aab Thumb Code 28 stm32f0xx_usart.o(.text) + USART_MSBFirstCmd 0x08001ac7 Thumb Code 28 stm32f0xx_usart.o(.text) + USART_DataInvCmd 0x08001ae3 Thumb Code 28 stm32f0xx_usart.o(.text) + USART_InvPinCmd 0x08001aff Thumb Code 20 stm32f0xx_usart.o(.text) + USART_SWAPPinCmd 0x08001b13 Thumb Code 28 stm32f0xx_usart.o(.text) + USART_ReceiverTimeOutCmd 0x08001b2f Thumb Code 28 stm32f0xx_usart.o(.text) + USART_SetReceiverTimeOut 0x08001b4b Thumb Code 16 stm32f0xx_usart.o(.text) + USART_SetPrescaler 0x08001b5b Thumb Code 18 stm32f0xx_usart.o(.text) + USART_STOPModeCmd 0x08001b6d Thumb Code 24 stm32f0xx_usart.o(.text) + USART_StopModeWakeUpSourceConfig 0x08001b85 Thumb Code 18 stm32f0xx_usart.o(.text) + USART_AutoBaudRateCmd 0x08001b97 Thumb Code 28 stm32f0xx_usart.o(.text) + USART_AutoBaudRateConfig 0x08001bb3 Thumb Code 18 stm32f0xx_usart.o(.text) + USART_AutoBaudRateNewRequest 0x08001bc5 Thumb Code 12 stm32f0xx_usart.o(.text) + USART_SendData 0x08001bd1 Thumb Code 8 stm32f0xx_usart.o(.text) + USART_ReceiveData 0x08001bd9 Thumb Code 10 stm32f0xx_usart.o(.text) + USART_SetAddress 0x08001be3 Thumb Code 18 stm32f0xx_usart.o(.text) + USART_MuteModeCmd 0x08001bf5 Thumb Code 28 stm32f0xx_usart.o(.text) + USART_MuteModeWakeUpConfig 0x08001c11 Thumb Code 18 stm32f0xx_usart.o(.text) + USART_AddressDetectionConfig 0x08001c23 Thumb Code 16 stm32f0xx_usart.o(.text) + USART_LINBreakDetectLengthConfig 0x08001c33 Thumb Code 16 stm32f0xx_usart.o(.text) + USART_LINCmd 0x08001c43 Thumb Code 28 stm32f0xx_usart.o(.text) + USART_HalfDuplexCmd 0x08001c5f Thumb Code 24 stm32f0xx_usart.o(.text) + USART_SetGuardTime 0x08001c77 Thumb Code 16 stm32f0xx_usart.o(.text) + USART_SmartCardCmd 0x08001c87 Thumb Code 24 stm32f0xx_usart.o(.text) + USART_SmartCardNACKCmd 0x08001c9f Thumb Code 24 stm32f0xx_usart.o(.text) + USART_SetAutoRetryCount 0x08001cb7 Thumb Code 20 stm32f0xx_usart.o(.text) + USART_SetBlockLength 0x08001ccb Thumb Code 30 stm32f0xx_usart.o(.text) + USART_IrDAConfig 0x08001ce9 Thumb Code 16 stm32f0xx_usart.o(.text) + USART_IrDACmd 0x08001cf9 Thumb Code 24 stm32f0xx_usart.o(.text) + USART_DECmd 0x08001d11 Thumb Code 28 stm32f0xx_usart.o(.text) + USART_DEPolarityConfig 0x08001d2d Thumb Code 18 stm32f0xx_usart.o(.text) + USART_SetDEAssertionTime 0x08001d3f Thumb Code 20 stm32f0xx_usart.o(.text) + USART_SetDEDeassertionTime 0x08001d53 Thumb Code 20 stm32f0xx_usart.o(.text) + USART_DMACmd 0x08001d67 Thumb Code 20 stm32f0xx_usart.o(.text) + USART_DMAReceptionErrorConfig 0x08001d7b Thumb Code 18 stm32f0xx_usart.o(.text) + USART_ITConfig 0x08001d8d Thumb Code 66 stm32f0xx_usart.o(.text) + USART_RequestCmd 0x08001dcf Thumb Code 20 stm32f0xx_usart.o(.text) + USART_OverrunDetectionConfig 0x08001de3 Thumb Code 18 stm32f0xx_usart.o(.text) + USART_GetFlagStatus 0x08001df5 Thumb Code 20 stm32f0xx_usart.o(.text) + USART_ClearFlag 0x08001e09 Thumb Code 4 stm32f0xx_usart.o(.text) + USART_GetITStatus 0x08001e0d Thumb Code 78 stm32f0xx_usart.o(.text) + USART_ClearITPendingBit 0x08001e5b Thumb Code 18 stm32f0xx_usart.o(.text) + __use_no_semihosting 0x08001e6d Thumb Code 2 use_no_semi_2.o(.text) + __2sprintf 0x08001e71 Thumb Code 36 noretval__2sprintf.o(.text) + _printf_pre_padding 0x08001e99 Thumb Code 44 _printf_pad.o(.text) + _printf_post_padding 0x08001ec5 Thumb Code 34 _printf_pad.o(.text) + _printf_int_dec 0x08001ee9 Thumb Code 90 _printf_dec.o(.text) + __printf 0x08001f55 Thumb Code 270 __printf_wp.o(.text) + __aeabi_uidiv 0x08002063 Thumb Code 0 aeabi_sdiv.o(.text) + __aeabi_uidivmod 0x08002063 Thumb Code 20 aeabi_sdiv.o(.text) + __aeabi_idiv 0x08002077 Thumb Code 0 aeabi_sdiv.o(.text) + __aeabi_idivmod 0x08002077 Thumb Code 326 aeabi_sdiv.o(.text) + __use_two_region_memory 0x080021bd Thumb Code 2 heapauxi.o(.text) + __rt_heap_escrow$2region 0x080021bf Thumb Code 2 heapauxi.o(.text) + __rt_heap_expand$2region 0x080021c1 Thumb Code 2 heapauxi.o(.text) + __I$use$semihosting 0x080021c3 Thumb Code 0 use_no_semi.o(.text) + __use_no_semihosting_swi 0x080021c3 Thumb Code 2 use_no_semi.o(.text) + _printf_int_common 0x080021c5 Thumb Code 176 _printf_intcommon.o(.text) + _printf_char_common 0x0800227f Thumb Code 32 _printf_char_common.o(.text) + _sputc 0x080022a5 Thumb Code 10 _sputc.o(.text) + __rt_udiv10 0x080022af Thumb Code 40 rtudiv10.o(.text) + __user_setup_stackheap 0x080022d7 Thumb Code 62 sys_stackheap_outer.o(.text) + exit 0x08002315 Thumb Code 16 exit.o(.text) + __user_libspace 0x08002325 Thumb Code 8 libspace.o(.text) + __user_perproc_libspace 0x08002325 Thumb Code 0 libspace.o(.text) + __user_perthread_libspace 0x08002325 Thumb Code 0 libspace.o(.text) + _is_digit 0x0800232d Thumb Code 14 __printf_wp.o(i._is_digit) + Region$$Table$$Base 0x0800233c Number 0 anon$$obj.o(Region$$Table) + Region$$Table$$Limit 0x0800235c Number 0 anon$$obj.o(Region$$Table) + SystemCoreClock 0x20000000 Data 4 system_stm32f0xx.o(.data) + AHBPrescTable 0x20000004 Data 16 system_stm32f0xx.o(.data) + __stdout 0x20000014 Data 4 usart1.o(.data) + i 0x20000018 Data 1 usart1.o(.data) + p 0x20000019 Data 1 usart1.o(.data) + cmd 0x2000001a Data 1 usart1.o(.data) + cmdok 0x2000001b Data 1 usart1.o(.data) + ok 0x2000001c Data 1 usart1.o(.data) + val 0x2000001d Data 4 usart1.o(.data) + RX_BUF 0x20000021 Data 4 usart1.o(.data) + rx_flag_finished 0x20000025 Data 1 usart1.o(.data) + rx_count 0x20000026 Data 1 usart1.o(.data) + rch 0x2000003c Data 15 usart1.o(.bss) + __libspace_start 0x2000004c Data 96 libspace.o(.bss) + __temporary_stack_top$libspace 0x200000ac Data 0 libspace.o(.bss) + + + +============================================================================== + +Memory Map of the image + + Image Entry point : 0x08000a99 + + Load Region LR_1 (Base: 0x08000000, Size: 0x00002398, Max: 0xffffffff, ABSOLUTE) + + Execution Region ER_RO (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x0000235c, Max: 0xffffffff, ABSOLUTE) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x08000000 0x08000000 0x000000c0 Data RO 111 RESET startup_stm32f0xx.o + 0x080000c0 0x080000c0 0x00000008 Code RO 282 * !!!main c_p.l(__main.o) + 0x080000c8 0x080000c8 0x0000003c Code RO 460 !!!scatter c_p.l(__scatter.o) + 0x08000104 0x08000104 0x0000001a Code RO 462 !!handler_copy c_p.l(__scatter_copy.o) + 0x0800011e 0x0800011e 0x00000002 PAD + 0x08000120 0x08000120 0x0000001c Code RO 464 !!handler_zi c_p.l(__scatter_zi.o) + 0x0800013c 0x0800013c 0x00000002 Code RO 275 .ARM.Collect$$_printf_percent$$00000000 c_p.l(_printf_percent.o) + 0x0800013e 0x0800013e 0x0000000a Code RO 274 .ARM.Collect$$_printf_percent$$00000009 c_p.l(_printf_d.o) + 0x08000148 0x08000148 0x00000004 Code RO 297 .ARM.Collect$$_printf_percent$$00000017 c_p.l(_printf_percent_end.o) + 0x0800014c 0x0800014c 0x00000002 Code RO 333 .ARM.Collect$$libinit$$00000000 c_p.l(libinit.o) + 0x0800014e 0x0800014e 0x00000000 Code RO 347 .ARM.Collect$$libinit$$00000002 c_p.l(libinit2.o) + 0x0800014e 0x0800014e 0x00000000 Code RO 349 .ARM.Collect$$libinit$$00000004 c_p.l(libinit2.o) + 0x0800014e 0x0800014e 0x00000000 Code RO 352 .ARM.Collect$$libinit$$0000000A c_p.l(libinit2.o) + 0x0800014e 0x0800014e 0x00000000 Code RO 354 .ARM.Collect$$libinit$$0000000C c_p.l(libinit2.o) + 0x0800014e 0x0800014e 0x00000000 Code RO 356 .ARM.Collect$$libinit$$0000000E c_p.l(libinit2.o) + 0x0800014e 0x0800014e 0x00000000 Code RO 359 .ARM.Collect$$libinit$$00000011 c_p.l(libinit2.o) + 0x0800014e 0x0800014e 0x00000000 Code RO 361 .ARM.Collect$$libinit$$00000013 c_p.l(libinit2.o) + 0x0800014e 0x0800014e 0x00000000 Code RO 363 .ARM.Collect$$libinit$$00000015 c_p.l(libinit2.o) + 0x0800014e 0x0800014e 0x00000000 Code RO 365 .ARM.Collect$$libinit$$00000017 c_p.l(libinit2.o) + 0x0800014e 0x0800014e 0x00000000 Code RO 367 .ARM.Collect$$libinit$$00000019 c_p.l(libinit2.o) + 0x0800014e 0x0800014e 0x00000000 Code RO 369 .ARM.Collect$$libinit$$0000001B c_p.l(libinit2.o) + 0x0800014e 0x0800014e 0x00000000 Code RO 371 .ARM.Collect$$libinit$$0000001D c_p.l(libinit2.o) + 0x0800014e 0x0800014e 0x00000000 Code RO 373 .ARM.Collect$$libinit$$0000001F c_p.l(libinit2.o) + 0x0800014e 0x0800014e 0x00000000 Code RO 375 .ARM.Collect$$libinit$$00000021 c_p.l(libinit2.o) + 0x0800014e 0x0800014e 0x00000000 Code RO 377 .ARM.Collect$$libinit$$00000023 c_p.l(libinit2.o) + 0x0800014e 0x0800014e 0x00000000 Code RO 379 .ARM.Collect$$libinit$$00000025 c_p.l(libinit2.o) + 0x0800014e 0x0800014e 0x00000000 Code RO 383 .ARM.Collect$$libinit$$0000002C c_p.l(libinit2.o) + 0x0800014e 0x0800014e 0x00000000 Code RO 385 .ARM.Collect$$libinit$$0000002E c_p.l(libinit2.o) + 0x0800014e 0x0800014e 0x00000000 Code RO 387 .ARM.Collect$$libinit$$00000030 c_p.l(libinit2.o) + 0x0800014e 0x0800014e 0x00000000 Code RO 389 .ARM.Collect$$libinit$$00000032 c_p.l(libinit2.o) + 0x0800014e 0x0800014e 0x00000002 Code RO 390 .ARM.Collect$$libinit$$00000033 c_p.l(libinit2.o) + 0x08000150 0x08000150 0x00000002 Code RO 416 .ARM.Collect$$libshutdown$$00000000 c_p.l(libshutdown.o) + 0x08000152 0x08000152 0x00000000 Code RO 443 .ARM.Collect$$libshutdown$$00000002 c_p.l(libshutdown2.o) + 0x08000152 0x08000152 0x00000000 Code RO 445 .ARM.Collect$$libshutdown$$00000004 c_p.l(libshutdown2.o) + 0x08000152 0x08000152 0x00000000 Code RO 448 .ARM.Collect$$libshutdown$$00000007 c_p.l(libshutdown2.o) + 0x08000152 0x08000152 0x00000000 Code RO 451 .ARM.Collect$$libshutdown$$0000000A c_p.l(libshutdown2.o) + 0x08000152 0x08000152 0x00000000 Code RO 453 .ARM.Collect$$libshutdown$$0000000C c_p.l(libshutdown2.o) + 0x08000152 0x08000152 0x00000000 Code RO 456 .ARM.Collect$$libshutdown$$0000000F c_p.l(libshutdown2.o) + 0x08000152 0x08000152 0x00000002 Code RO 457 .ARM.Collect$$libshutdown$$00000010 c_p.l(libshutdown2.o) + 0x08000154 0x08000154 0x00000000 Code RO 286 .ARM.Collect$$rtentry$$00000000 c_p.l(__rtentry.o) + 0x08000154 0x08000154 0x00000000 Code RO 301 .ARM.Collect$$rtentry$$00000002 c_p.l(__rtentry2.o) + 0x08000154 0x08000154 0x00000006 Code RO 313 .ARM.Collect$$rtentry$$00000004 c_p.l(__rtentry4.o) + 0x0800015a 0x0800015a 0x00000000 Code RO 303 .ARM.Collect$$rtentry$$00000009 c_p.l(__rtentry2.o) + 0x0800015a 0x0800015a 0x00000004 Code RO 304 .ARM.Collect$$rtentry$$0000000A c_p.l(__rtentry2.o) + 0x0800015e 0x0800015e 0x00000000 Code RO 306 .ARM.Collect$$rtentry$$0000000C c_p.l(__rtentry2.o) + 0x0800015e 0x0800015e 0x00000008 Code RO 307 .ARM.Collect$$rtentry$$0000000D c_p.l(__rtentry2.o) + 0x08000166 0x08000166 0x00000002 Code RO 338 .ARM.Collect$$rtexit$$00000000 c_p.l(rtexit.o) + 0x08000168 0x08000168 0x00000000 Code RO 392 .ARM.Collect$$rtexit$$00000002 c_p.l(rtexit2.o) + 0x08000168 0x08000168 0x00000004 Code RO 393 .ARM.Collect$$rtexit$$00000003 c_p.l(rtexit2.o) + 0x0800016c 0x0800016c 0x00000006 Code RO 394 .ARM.Collect$$rtexit$$00000004 c_p.l(rtexit2.o) + 0x08000172 0x08000172 0x00000002 PAD + 0x08000174 0x08000174 0x00000720 Code RO 2 .text main.o + 0x08000894 0x08000894 0x0000000c Code RO 69 .text stm32f0xx_it.o + 0x080008a0 0x080008a0 0x000001f8 Code RO 88 .text system_stm32f0xx.o + 0x08000a98 0x08000a98 0x00000038 Code RO 112 * .text startup_stm32f0xx.o + 0x08000ad0 0x08000ad0 0x000004b8 Code RO 117 .text usart1.o + 0x08000f88 0x08000f88 0x000000d4 Code RO 157 .text delay.o + 0x0800105c 0x0800105c 0x000001f0 Code RO 175 .text stm32f0xx_gpio.o + 0x0800124c 0x0800124c 0x000005f8 Code RO 191 .text stm32f0xx_rcc.o + 0x08001844 0x08001844 0x000000b4 Code RO 209 .text stm32f0xx_misc.o + 0x080018f8 0x080018f8 0x00000574 Code RO 225 .text stm32f0xx_usart.o + 0x08001e6c 0x08001e6c 0x00000002 Code RO 242 .text c_p.l(use_no_semi_2.o) + 0x08001e6e 0x08001e6e 0x00000002 PAD + 0x08001e70 0x08001e70 0x00000028 Code RO 246 .text c_p.l(noretval__2sprintf.o) + 0x08001e98 0x08001e98 0x0000004e Code RO 250 .text c_p.l(_printf_pad.o) + 0x08001ee6 0x08001ee6 0x00000002 PAD + 0x08001ee8 0x08001ee8 0x0000006c Code RO 252 .text c_p.l(_printf_dec.o) + 0x08001f54 0x08001f54 0x0000010e Code RO 262 .text c_p.l(__printf_wp.o) + 0x08002062 0x08002062 0x0000015a Code RO 276 .text c_p.l(aeabi_sdiv.o) + 0x080021bc 0x080021bc 0x00000006 Code RO 280 .text c_p.l(heapauxi.o) + 0x080021c2 0x080021c2 0x00000002 Code RO 284 .text c_p.l(use_no_semi.o) + 0x080021c4 0x080021c4 0x000000b0 Code RO 291 .text c_p.l(_printf_intcommon.o) + 0x08002274 0x08002274 0x00000030 Code RO 293 .text c_p.l(_printf_char_common.o) + 0x080022a4 0x080022a4 0x0000000a Code RO 295 .text c_p.l(_sputc.o) + 0x080022ae 0x080022ae 0x00000028 Code RO 298 .text c_p.l(rtudiv10.o) + 0x080022d6 0x080022d6 0x0000003e Code RO 319 .text c_p.l(sys_stackheap_outer.o) + 0x08002314 0x08002314 0x00000010 Code RO 322 .text c_p.l(exit.o) + 0x08002324 0x08002324 0x00000008 Code RO 334 .text c_p.l(libspace.o) + 0x0800232c 0x0800232c 0x0000000e Code RO 264 i._is_digit c_p.l(__printf_wp.o) + 0x0800233a 0x0800233a 0x00000002 PAD + 0x0800233c 0x0800233c 0x00000020 Data RO 458 Region$$Table anon$$obj.o + + + Execution Region ER_RW (Exec base: 0x20000000, Load base: 0x0800235c, Size: 0x0000003c, Max: 0xffffffff, ABSOLUTE) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x20000000 0x0800235c 0x00000014 Data RW 89 .data system_stm32f0xx.o + 0x20000014 0x08002370 0x00000013 Data RW 119 .data usart1.o + 0x20000027 0x08002383 0x00000001 PAD + 0x20000028 0x08002384 0x00000004 Data RW 158 .data delay.o + 0x2000002c 0x08002388 0x00000010 Data RW 192 .data stm32f0xx_rcc.o + + + Execution Region ER_ZI (Exec base: 0x2000003c, Load base: 0x08002398, Size: 0x00000674, Max: 0xffffffff, ABSOLUTE) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x2000003c - 0x0000000f Zero RW 118 .bss usart1.o + 0x2000004b 0x08002398 0x00000001 PAD + 0x2000004c - 0x00000060 Zero RW 335 .bss c_p.l(libspace.o) + 0x200000ac 0x08002398 0x00000004 PAD + 0x200000b0 - 0x00000200 Zero RW 110 HEAP startup_stm32f0xx.o + 0x200002b0 - 0x00000400 Zero RW 109 STACK startup_stm32f0xx.o + + +============================================================================== + +Image component sizes + + + Code (inc. data) RO Data RW Data ZI Data Debug Object Name + + 212 20 0 4 0 1163 delay.o + 1824 1084 0 0 0 29971 main.o + 56 26 192 0 1536 680 startup_stm32f0xx.o + 496 22 0 0 0 3865 stm32f0xx_gpio.o + 12 0 0 0 0 847 stm32f0xx_it.o + 180 14 0 0 0 1480 stm32f0xx_misc.o + 1528 42 0 16 0 8782 stm32f0xx_rcc.o + 1396 12 0 0 0 12231 stm32f0xx_usart.o + 504 34 0 20 0 1815 system_stm32f0xx.o + 1208 68 0 19 15 89466 usart1.o + + ---------------------------------------------------------------------- + 7416 1322 224 60 1552 150300 Object Totals + 0 0 32 0 0 0 (incl. Generated) + 0 0 0 1 1 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name + + 8 0 0 0 0 68 __main.o + 284 0 0 0 0 136 __printf_wp.o + 0 0 0 0 0 0 __rtentry.o + 12 0 0 0 0 0 __rtentry2.o + 6 0 0 0 0 0 __rtentry4.o + 60 8 0 0 0 0 __scatter.o + 26 0 0 0 0 0 __scatter_copy.o + 28 0 0 0 0 0 __scatter_zi.o + 48 6 0 0 0 88 _printf_char_common.o + 10 0 0 0 0 0 _printf_d.o + 108 18 0 0 0 76 _printf_dec.o + 176 0 0 0 0 84 _printf_intcommon.o + 78 0 0 0 0 100 _printf_pad.o + 2 0 0 0 0 0 _printf_percent.o + 4 0 0 0 0 0 _printf_percent_end.o + 10 0 0 0 0 60 _sputc.o + 346 0 0 0 0 92 aeabi_sdiv.o + 16 0 0 0 0 68 exit.o + 6 0 0 0 0 136 heapauxi.o + 2 0 0 0 0 0 libinit.o + 2 0 0 0 0 0 libinit2.o + 2 0 0 0 0 0 libshutdown.o + 2 0 0 0 0 0 libshutdown2.o + 8 4 0 0 96 68 libspace.o + 40 4 0 0 0 84 noretval__2sprintf.o + 2 0 0 0 0 0 rtexit.o + 10 0 0 0 0 0 rtexit2.o + 40 0 0 0 0 60 rtudiv10.o + 62 0 0 0 0 80 sys_stackheap_outer.o + 2 0 0 0 0 68 use_no_semi.o + 2 0 0 0 0 68 use_no_semi_2.o + + ---------------------------------------------------------------------- + 1412 40 0 0 100 1336 Library Totals + 10 0 0 0 4 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Name + + 1402 40 0 0 96 1336 c_p.l + + ---------------------------------------------------------------------- + 1412 40 0 0 100 1336 Library Totals + + ---------------------------------------------------------------------- + +============================================================================== + + + Code (inc. data) RO Data RW Data ZI Data Debug + + 8828 1362 224 60 1652 150428 Grand Totals + 8828 1362 224 60 1652 150428 ELF Image Totals + 8828 1362 224 60 0 0 ROM Totals + +============================================================================== + + Total RO Size (Code + RO Data) 9052 ( 8.84kB) + Total RW Size (RW Data + ZI Data) 1712 ( 1.67kB) + Total ROM Size (Code + RO Data + RW Data) 9112 ( 8.90kB) + +============================================================================== + diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/include.h b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/include.h new file mode 100644 index 0000000..a552530 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/include.h @@ -0,0 +1,6 @@ +#ifndef _INCLUDE_H_ +#define _INCLUDE_H_ +#include "delay.h" +#include "led.h" + +#endif diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/keilkill.bat b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/keilkill.bat new file mode 100644 index 0000000..55fe6bd --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/keilkill.bat @@ -0,0 +1,17 @@ +del *.crf /s +del *.d /s +del *.o /s +del *.htm /s +del *.tra /s +del *.axf /s +del *.lnp /s + +del *.plg /s +del *.iex /s +del *.map /s +del *.dep /s +del *.bak /s +del *.lst /s +del *.uvopt/s +del *.uvgui.*/s +exit diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/main.c b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/main.c new file mode 100644 index 0000000..5f4ecf8 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/main.c @@ -0,0 +1,262 @@ +#include "stm32f0xx.h" +#include "delay.h" +#include "led.h" +#include "USART1.h" +#include "Key.h" + +/////////////////////////////////////////////////////////////////////////////////////////////////////// +//ڼ֤/ӽJCϵмɴģ +//STM32F030 +//ӽƼ@̲ +//˾վ:www.sun-lcm.com +//Ա꣺https://shop151604432.taobao.com +//ҵ꣺https://sundisplay2008.1688.com +//ҵ֧֣ mobile:13509671256 QQ:3167153224 +//֧֣ QQ:3085638545 +//޸:2015/09/18 +//汾V1.0 +//ȨУؾ +//Copyright(C) ӽƼ޹˾ 2015-2021 +//All rights reserved +//****************************************************************************************************** +//V1.0޸˵ +// +///////////////////////////////////////////////////////////////////////////////////////////////////////// + +extern unsigned char val[]; + +///////////////////////////////////////////////////////////////////////////////////// +// +//1.߷ʽ TX-->TX RX->RX +//2.ϵΪʹģҪȴ1ӣ֤ģܹijʼ +//3.ڳʼ ģĬΪ 115200 8λλ 1ʼλ 1ֹͣλ żУ +//4.ָָΪ"ָ;\r\n" "ָ1;ָ2;...ָn;\r\n" +//5.ָȴģشġOK\r\n ͨʱķʽȷָָִ +////////////////////////////////////////////////////////////////////////////////////// + +int main(void) +{ + unsigned char i,k; + unsigned char ret; + char buf[128]; + delay_init();//ʱʼ + delay_ms(1000);//ȴ1S + USART1_Init(115200); //ڳʼ + //printf("STM32F030F4P6 USART TEST\r\n"); + + for(;;) //ѭִ + { + delay_ms(500); + + for(i=0;i<7;i++) + { + sprintf(buf,"DIR(1);FSIMG(%2d,0,0,128,128,0);\r\n",2097152+128*128*2*i);//ڣ0,0λȡ8ͼƬһŴӵַ2097152ʼͼƬС128x128ģʽ0ʾʾ + UartSend(buf);//ַָ + CheckBusy(); //ȴģִ꣬ҲǼģ鷢ͻ"OK\r\n" + + } + delay_ms(1200); + + UartSend("DIR(1);CLR(0);DC16(10,5,'ӽƼ',4);\r\n"); // ʾɫΪɫûɫ(10,5)Ϊ,Ļʾ͸'ӽƼ'ĸ,СΪ16,4Ϊɫɫ + CheckBusy(); + + UartSend("PL(0,30,127,30,15);\r\n");//ֱĻϵ(0,30)λõĵͣ127,30λõĵðɫ(15)ֱ + CheckBusy(); + //delay_ms(800); + + UartSend("PL(0,30,127,30,15);\r\n");//ֱͬ + CheckBusy(); + //delay_ms(800); + + UartSend("PL(0,127,127,127,15);\r\n");//ֱͬ + CheckBusy(); + //delay_ms(800); + + UartSend("PL(0,75,127,75,15);\r\n");//ֱͬ + CheckBusy(); + //delay_ms(800); + + UartSend("PL(0,30,0,127,15);\r\n");//ֱͬ + CheckBusy(); + //delay_ms(800); + + UartSend("PL(65,30,65,127,15);\r\n");//ֱͬ + CheckBusy(); + //delay_ms(800); + + UartSend("PL(127,30,127,127,15);\r\n");//ֱͬ + CheckBusy(); + //delay_ms(800); + UartSend("CIR(32,50,15,1);\r\n"); //(32,50)ΪԲ 15Ϊ뾶úɫһԲ ,1Ϊɫɫ + CheckBusy(); + UartSend("CIRF(42,50,15,2);\r\n"); //(42,50)ΪԲ 15Ϊ뾶ɫһԲ, ,2Ϊɫɫ + CheckBusy(); + //delay_ms(800); + + UartSend("BOXF(80,39,110,60,3);\r\n");//Խ(80,39)(110,60) ,3Ϊɫɫ + CheckBusy(); + + UartSend("BOX(90,39,120,60,1);\r\n");//Խ(90,39)(120,60)߿ ,1Ϊɫɫ + CheckBusy(); + + UartSend("PS(40,90,2);\r\n");//Ļ(40,90) λɫһ,2Ϊɫɫ + CheckBusy(); + + UartSend("PL(15,105,60,105,1);\r\n");//ֱͬ + CheckBusy(); + + UartSend("CIR(90,105,15,1);\r\n"); //Բͬ + CheckBusy(); + + UartSend("PS(120,105,24);\r\n");//ͬ + CheckBusy(); + delay_ms(1600); + + UartSend("DIR(1);CLR(0);DC16(10,5,'ӽƼ',4);\r\n");//ˢͬ + CheckBusy(); + + UartSend("PL(0,30,127,30,15);\r\n");//ֱͬ + CheckBusy(); + //delay_ms(800); + + UartSend("PL(0,127,127,127,15);\r\n");//ֱͬ + CheckBusy(); + //delay_ms(800); + + UartSend("PL(0,75,127,75,15);\r\n");//ֱͬ + CheckBusy(); + //delay_ms(800); + + UartSend("PL(0,30,0,127,15);\r\n");//ֱͬ + CheckBusy(); + //delay_ms(800); + + UartSend("PL(65,30,65,127,15);\r\n");//ֱͬ + CheckBusy(); + //delay_ms(800); + + UartSend("PL(127,30,127,127,15);\r\n");//ֱͬ + CheckBusy(); + //delay_ms(800); + + UartSend("DC16(10,45,'ABC',3);\r\n");//ˢͬ + CheckBusy(); + + UartSend("SBC(15);DCV16(40,45,'ABC',0);\r\n"); //úɫ(40,45)Ϊ,Ļʾɫɫ'ABC'ĸĸ,СΪ16,0Ϊɫɫ + CheckBusy(); + + UartSend("DC24(80,40,'123',2);\r\n"); //ˢͬ + CheckBusy(); +// UartSend("SBC(4);DCV24(120,40,'123',0);\r\n"); //ˢƵɫͬ +// CheckBusy(); + + UartSend("DCV32(3,85,'',2);\r\n"); //ˢͬ + CheckBusy(); + + UartSend("SBC(1);DC24(75,85,'й',1);\r\n"); //ˢͬ + CheckBusy(); + delay_ms(1600); + + + UartSend("CLR(0);DIR(1);FSIMG(2326528,0,0,128,128,0);\r\n"); //ʾ(0,0)λʾַΪ2326528ͼƬ,ͼƬĿ128 ߶128ģʽ0ʾʾ + CheckBusy(); + UartSend("DC24(5,0,'2019-08-20 ',15);\r\n");//ˢͬ + CheckBusy(); + UartSend("DC16(5,35,' ڶ',15);\r\n");//ˢͬ + CheckBusy(); + + UartSend("DC16(60,35,' 20 ',15);\r\n");//ˢͬ + CheckBusy(); + + UartSend("PL(0,30,128,30,15);\r\n");//ֱͬ + CheckBusy(); + + k=0; + for(k=0;k<=60;k++) + { + sprintf(buf,"SBC(15);DCV16(105,35,'%d',1);\r\n",k);//ˢ16仯0-60 + k=k+1; + delay_ms(100); + UartSend(buf); + CheckBusy(); + } + + k=0; + for(k=0;k<=50;k++) + { + sprintf(buf,"SBC(15);DCV16(15,70,'%d',1);\r\n",k);//ˢ16仯0-50 + k=k+1; + delay_ms(100); + UartSend(buf); + CheckBusy(); + + sprintf(buf,"SBC(15);DCV16(52,70,'%d',1);\r\n",k);//ˢ16仯0-50 + k=k+1; + delay_ms(100); + UartSend(buf); + CheckBusy(); + + sprintf(buf,"SBC(15);DCV16(95,70,'%d',1);\r\n",k);//ˢ16仯0-50 + k=k+1; + delay_ms(100); + UartSend(buf); + CheckBusy(); + } + + delay_ms(1600); + + UartSend("CLR(0);DIR(1);FSIMG(2359296,0,0,128,128,0);\r\n");//ˢͼƬָͬ + CheckBusy(); + + { + k=40; + { + sprintf(buf,"DCV16(47,60,'ȣ80 ',1);BL(%2d);\r\n",k);//ˢ16壬ȱkת"BL(k);\r\n"ַָΧ0Ϊ 255Ϊ + UartSend(buf); + CheckBusy(); + delay_ms(1000); + } + } + + { + k=127; + { + sprintf(buf,"DCV16(47,60,'ȣ50 ',1);BL(%2d);\r\n",k);//ˢ16壬ȱkת"BL(k);\r\n"ַָΧ0Ϊ 255Ϊ + UartSend(buf); + CheckBusy(); + delay_ms(1000); + } + } + + { + k=200; + { + sprintf(buf,"DCV16(47,60,'ȣ20 ',1);BL(%2d);\r\n",k);//ˢ16壬ȱkת"BL(k);\r\n"ַָΧ0Ϊ 255Ϊ + UartSend(buf); + CheckBusy(); + delay_ms(1000); + + } + } + + { + k=0; + { + sprintf(buf,"DCV16(47,60,'ȣ100',1);BL(%2d);\r\n",k);//ˢ16壬ȱkת"BL(k);\r\n"ַָΧ0Ϊ 255Ϊ + UartSend(buf); + CheckBusy(); + delay_ms(1000); + } + } + delay_ms(1600); + + UartSend("DIR(1);CLR(61);DC24(5,50,'ʾ',15);\r\n"); //ˢͬ + CheckBusy(); + delay_ms(1600); + } + } + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/startup_stm32f0xx.lst b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/startup_stm32f0xx.lst new file mode 100644 index 0000000..c1bf813 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/startup_stm32f0xx.lst @@ -0,0 +1,943 @@ + + + +ARM Macro Assembler Page 1 + + + 1 00000000 ;******************** (C) COPYRIGHT 2012 STMicroelectron + ics ******************** + 2 00000000 ;* File Name : startup_stm32f0xx.s + 3 00000000 ;* Author : MCD Application Team + 4 00000000 ;* Version : V1.0.0 + 5 00000000 ;* Date : 23-March-2012 + 6 00000000 ;* Description : STM32F0xx Devices vector table f + or MDK-ARM toolchain. + 7 00000000 ;* This module performs: + 8 00000000 ;* - Set the initial SP + 9 00000000 ;* - Set the initial PC == Reset_Ha + ndler + 10 00000000 ;* - Set the vector table entries w + ith the exceptions ISR address + 11 00000000 ;* - Branches to __main in the C li + brary (which eventually + 12 00000000 ;* calls main()). + 13 00000000 ;* After Reset the CortexM0 process + or is in Thread mode, + 14 00000000 ;* priority is Privileged, and the + Stack is set to Main. + 15 00000000 ;* <<< Use Configuration Wizard in Context Menu >>> + 16 00000000 ;******************************************************* + ************************ + 17 00000000 ; @attention + 18 00000000 ; + 19 00000000 ; Licensed under MCD-ST Liberty SW License Agreement V2 + , (the "License"); + 20 00000000 ; You may not use this file except in compliance with t + he License. + 21 00000000 ; You may obtain a copy of the License at: + 22 00000000 ; + 23 00000000 ; http://www.st.com/software_license_agreement_l + iberty_v2 + 24 00000000 ; + 25 00000000 ; Unless required by applicable law or agreed to in wri + ting, software + 26 00000000 ; distributed under the License is distributed on an "A + S IS" BASIS, + 27 00000000 ; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + express or implied. + 28 00000000 ; See the License for the specific language governing p + ermissions and + 29 00000000 ; limitations under the License. + 30 00000000 ; + 31 00000000 ;******************************************************* + ************************ + 32 00000000 ; + 33 00000000 ; Amount of memory (in bytes) allocated for Stack + 34 00000000 ; Tailor this value to your application needs + 35 00000000 ; Stack Configuration + 36 00000000 ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + 37 00000000 ; + 38 00000000 + 39 00000000 00000400 + Stack_Size + EQU 0x00000400 + 40 00000000 + 41 00000000 AREA STACK, NOINIT, READWRITE, ALIGN + + + +ARM Macro Assembler Page 2 + + +=3 + 42 00000000 Stack_Mem + SPACE Stack_Size + 43 00000400 __initial_sp + 44 00000400 + 45 00000400 + 46 00000400 ; Heap Configuration + 47 00000400 ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + 48 00000400 ; + 49 00000400 + 50 00000400 00000200 + Heap_Size + EQU 0x00000200 + 51 00000400 + 52 00000400 AREA HEAP, NOINIT, READWRITE, ALIGN= +3 + 53 00000000 __heap_base + 54 00000000 Heap_Mem + SPACE Heap_Size + 55 00000200 __heap_limit + 56 00000200 + 57 00000200 PRESERVE8 + 58 00000200 THUMB + 59 00000200 + 60 00000200 + 61 00000200 ; Vector Table Mapped to Address 0 at Reset + 62 00000200 AREA RESET, DATA, READONLY + 63 00000000 EXPORT __Vectors + 64 00000000 EXPORT __Vectors_End + 65 00000000 EXPORT __Vectors_Size + 66 00000000 + 67 00000000 00000000 + __Vectors + DCD __initial_sp ; Top of Stack + 68 00000004 00000000 DCD Reset_Handler ; Reset Handler + 69 00000008 00000000 DCD NMI_Handler ; NMI Handler + 70 0000000C 00000000 DCD HardFault_Handler ; Hard Fault + Handler + 71 00000010 00000000 DCD 0 ; Reserved + 72 00000014 00000000 DCD 0 ; Reserved + 73 00000018 00000000 DCD 0 ; Reserved + 74 0000001C 00000000 DCD 0 ; Reserved + 75 00000020 00000000 DCD 0 ; Reserved + 76 00000024 00000000 DCD 0 ; Reserved + 77 00000028 00000000 DCD 0 ; Reserved + 78 0000002C 00000000 DCD SVC_Handler ; SVCall Handler + 79 00000030 00000000 DCD 0 ; Reserved + 80 00000034 00000000 DCD 0 ; Reserved + 81 00000038 00000000 DCD PendSV_Handler ; PendSV Handler + + 82 0000003C 00000000 DCD SysTick_Handler + ; SysTick Handler + 83 00000040 + 84 00000040 ; External Interrupts + 85 00000040 00000000 DCD WWDG_IRQHandler + ; Window Watchdog + 86 00000044 00000000 DCD PVD_IRQHandler ; PVD through EX + TI Line detect + 87 00000048 00000000 DCD RTC_IRQHandler ; RTC through EX + + + +ARM Macro Assembler Page 3 + + + TI Line + 88 0000004C 00000000 DCD FLASH_IRQHandler ; FLASH + 89 00000050 00000000 DCD RCC_IRQHandler ; RCC + 90 00000054 00000000 DCD EXTI0_1_IRQHandler + ; EXTI Line 0 and 1 + + 91 00000058 00000000 DCD EXTI2_3_IRQHandler + ; EXTI Line 2 and 3 + + 92 0000005C 00000000 DCD EXTI4_15_IRQHandler + ; EXTI Line 4 to 15 + + 93 00000060 00000000 DCD TS_IRQHandler ; TS + 94 00000064 00000000 DCD DMA1_Channel1_IRQHandler + ; DMA1 Channel 1 + 95 00000068 00000000 DCD DMA1_Channel2_3_IRQHandler ; DM + A1 Channel 2 and Ch + annel 3 + 96 0000006C 00000000 DCD DMA1_Channel4_5_IRQHandler ; DM + A1 Channel 4 and Ch + annel 5 + 97 00000070 00000000 DCD ADC1_COMP_IRQHandler ; ADC1, CO + MP1 and COMP2 + 98 00000074 00000000 DCD TIM1_BRK_UP_TRG_COM_IRQHandler + ; TIM1 Break, Updat + e, Trigger and Comm + utation + 99 00000078 00000000 DCD TIM1_CC_IRQHandler ; TIM1 Captu + re Compare + 100 0000007C 00000000 DCD TIM2_IRQHandler ; TIM2 + 101 00000080 00000000 DCD TIM3_IRQHandler ; TIM3 + 102 00000084 00000000 DCD TIM6_DAC_IRQHandler + ; TIM6 and DAC + 103 00000088 00000000 DCD 0 ; Reserved + 104 0000008C 00000000 DCD TIM14_IRQHandler ; TIM14 + 105 00000090 00000000 DCD TIM15_IRQHandler ; TIM15 + 106 00000094 00000000 DCD TIM16_IRQHandler ; TIM16 + 107 00000098 00000000 DCD TIM17_IRQHandler ; TIM17 + 108 0000009C 00000000 DCD I2C1_IRQHandler ; I2C1 + 109 000000A0 00000000 DCD I2C2_IRQHandler ; I2C2 + 110 000000A4 00000000 DCD SPI1_IRQHandler ; SPI1 + 111 000000A8 00000000 DCD SPI2_IRQHandler ; SPI2 + 112 000000AC 00000000 DCD USART1_IRQHandler ; USART1 + 113 000000B0 00000000 DCD USART2_IRQHandler ; USART2 + 114 000000B4 00000000 DCD 0 ; Reserved + 115 000000B8 00000000 DCD CEC_IRQHandler ; CEC + 116 000000BC 00000000 DCD 0 ; Reserved + 117 000000C0 + 118 000000C0 __Vectors_End + 119 000000C0 + 120 000000C0 000000C0 + __Vectors_Size + EQU __Vectors_End - __Vectors + 121 000000C0 + 122 000000C0 AREA |.text|, CODE, READONLY + 123 00000000 + 124 00000000 ; Reset handler routine + 125 00000000 Reset_Handler + PROC + + + +ARM Macro Assembler Page 4 + + + 126 00000000 EXPORT Reset_Handler [ +WEAK] + 127 00000000 IMPORT __main + 128 00000000 IMPORT SystemInit + 129 00000000 4807 LDR R0, =SystemInit + 130 00000002 4780 BLX R0 + 131 00000004 4807 LDR R0, =__main + 132 00000006 4700 BX R0 + 133 00000008 ENDP + 134 00000008 + 135 00000008 ; Dummy Exception Handlers (infinite loops which can be + modified) + 136 00000008 + 137 00000008 NMI_Handler + PROC + 138 00000008 EXPORT NMI_Handler +[WEAK] + 139 00000008 E7FE B . + 140 0000000A ENDP + 142 0000000A HardFault_Handler + PROC + 143 0000000A EXPORT HardFault_Handler +[WEAK] + 144 0000000A E7FE B . + 145 0000000C ENDP + 146 0000000C SVC_Handler + PROC + 147 0000000C EXPORT SVC_Handler +[WEAK] + 148 0000000C E7FE B . + 149 0000000E ENDP + 150 0000000E PendSV_Handler + PROC + 151 0000000E EXPORT PendSV_Handler +[WEAK] + 152 0000000E E7FE B . + 153 00000010 ENDP + 154 00000010 SysTick_Handler + PROC + 155 00000010 EXPORT SysTick_Handler +[WEAK] + 156 00000010 E7FE B . + 157 00000012 ENDP + 158 00000012 + 159 00000012 Default_Handler + PROC + 160 00000012 + 161 00000012 EXPORT WWDG_IRQHandler +[WEAK] + 162 00000012 EXPORT PVD_IRQHandler +[WEAK] + 163 00000012 EXPORT RTC_IRQHandler +[WEAK] + 164 00000012 EXPORT FLASH_IRQHandler +[WEAK] + 165 00000012 EXPORT RCC_IRQHandler +[WEAK] + 166 00000012 EXPORT EXTI0_1_IRQHandler +[WEAK] + + + +ARM Macro Assembler Page 5 + + + 167 00000012 EXPORT EXTI2_3_IRQHandler +[WEAK] + 168 00000012 EXPORT EXTI4_15_IRQHandler +[WEAK] + 169 00000012 EXPORT TS_IRQHandler +[WEAK] + 170 00000012 EXPORT DMA1_Channel1_IRQHandler +[WEAK] + 171 00000012 EXPORT DMA1_Channel2_3_IRQHandler +[WEAK] + 172 00000012 EXPORT DMA1_Channel4_5_IRQHandler +[WEAK] + 173 00000012 EXPORT ADC1_COMP_IRQHandler +[WEAK] + 174 00000012 EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler +[WEAK] + 175 00000012 EXPORT TIM1_CC_IRQHandler +[WEAK] + 176 00000012 EXPORT TIM2_IRQHandler +[WEAK] + 177 00000012 EXPORT TIM3_IRQHandler +[WEAK] + 178 00000012 EXPORT TIM6_DAC_IRQHandler +[WEAK] + 179 00000012 EXPORT TIM14_IRQHandler +[WEAK] + 180 00000012 EXPORT TIM15_IRQHandler +[WEAK] + 181 00000012 EXPORT TIM16_IRQHandler +[WEAK] + 182 00000012 EXPORT TIM17_IRQHandler +[WEAK] + 183 00000012 EXPORT I2C1_IRQHandler +[WEAK] + 184 00000012 EXPORT I2C2_IRQHandler +[WEAK] + 185 00000012 EXPORT SPI1_IRQHandler +[WEAK] + 186 00000012 EXPORT SPI2_IRQHandler +[WEAK] + 187 00000012 EXPORT USART1_IRQHandler +[WEAK] + 188 00000012 EXPORT USART2_IRQHandler +[WEAK] + 189 00000012 EXPORT CEC_IRQHandler +[WEAK] + 190 00000012 + 191 00000012 + 192 00000012 WWDG_IRQHandler + 193 00000012 PVD_IRQHandler + 194 00000012 RTC_IRQHandler + 195 00000012 FLASH_IRQHandler + 196 00000012 RCC_IRQHandler + 197 00000012 EXTI0_1_IRQHandler + 198 00000012 EXTI2_3_IRQHandler + 199 00000012 EXTI4_15_IRQHandler + 200 00000012 TS_IRQHandler + 201 00000012 DMA1_Channel1_IRQHandler + 202 00000012 DMA1_Channel2_3_IRQHandler + + + +ARM Macro Assembler Page 6 + + + 203 00000012 DMA1_Channel4_5_IRQHandler + 204 00000012 ADC1_COMP_IRQHandler + 205 00000012 TIM1_BRK_UP_TRG_COM_IRQHandler + 206 00000012 TIM1_CC_IRQHandler + 207 00000012 TIM2_IRQHandler + 208 00000012 TIM3_IRQHandler + 209 00000012 TIM6_DAC_IRQHandler + 210 00000012 TIM14_IRQHandler + 211 00000012 TIM15_IRQHandler + 212 00000012 TIM16_IRQHandler + 213 00000012 TIM17_IRQHandler + 214 00000012 I2C1_IRQHandler + 215 00000012 I2C2_IRQHandler + 216 00000012 SPI1_IRQHandler + 217 00000012 SPI2_IRQHandler + 218 00000012 USART1_IRQHandler + 219 00000012 USART2_IRQHandler + 220 00000012 CEC_IRQHandler + 221 00000012 + 222 00000012 E7FE B . + 223 00000014 + 224 00000014 ENDP + 225 00000014 + 226 00000014 ALIGN + 227 00000014 + 228 00000014 ;******************************************************* + ************************ + 229 00000014 ; User Stack and Heap initialization + 230 00000014 ;******************************************************* + ************************ + 231 00000014 IF :DEF:__MICROLIB + 238 00000014 + 239 00000014 IMPORT __use_two_region_memory + 240 00000014 EXPORT __user_initial_stackheap + 241 00000014 + 242 00000014 __user_initial_stackheap + 243 00000014 + 244 00000014 4804 LDR R0, = Heap_Mem + 245 00000016 4905 LDR R1, =(Stack_Mem + Stack_Size) + 246 00000018 4A05 LDR R2, = (Heap_Mem + Heap_Size) + 247 0000001A 4B06 LDR R3, = Stack_Mem + 248 0000001C 4770 BX LR + 249 0000001E + 250 0000001E 00 00 ALIGN + 251 00000020 + 252 00000020 ENDIF + 253 00000020 + 254 00000020 END + 00000000 + 00000000 + 00000000 + 00000400 + 00000200 + 00000000 +Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M0 --apcs=interw +ork --depend=..\obj\startup_stm32f0xx.d -o..\obj\startup_stm32f0xx.o -I.\RTE\_S +tm32f030demo -IF:\tool_setup\ARM\CMSIS\5.3.0\CMSIS\Include -IF:\tool_setup\Keil +\STM32F0xx_DFP\2.0.0\Drivers\CMSIS\Device\ST\STM32F0xx\Include --predefine="__U +VISION_VERSION SETA 525" --predefine="_RTE_ SETA 1" --predefine="STM32F030x6 SE + + + +ARM Macro Assembler Page 7 + + +TA 1" --list=.\startup_stm32f0xx.lst ..\CORE\startup_stm32f0xx.s + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +STACK 00000000 + +Symbol: STACK + Definitions + At line 41 in file ..\CORE\startup_stm32f0xx.s + Uses + None +Comment: STACK unused +Stack_Mem 00000000 + +Symbol: Stack_Mem + Definitions + At line 42 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 245 in file ..\CORE\startup_stm32f0xx.s + At line 247 in file ..\CORE\startup_stm32f0xx.s + +__initial_sp 00000400 + +Symbol: __initial_sp + Definitions + At line 43 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 67 in file ..\CORE\startup_stm32f0xx.s +Comment: __initial_sp used once +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +HEAP 00000000 + +Symbol: HEAP + Definitions + At line 52 in file ..\CORE\startup_stm32f0xx.s + Uses + None +Comment: HEAP unused +Heap_Mem 00000000 + +Symbol: Heap_Mem + Definitions + At line 54 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 244 in file ..\CORE\startup_stm32f0xx.s + At line 246 in file ..\CORE\startup_stm32f0xx.s + +__heap_base 00000000 + +Symbol: __heap_base + Definitions + At line 53 in file ..\CORE\startup_stm32f0xx.s + Uses + None +Comment: __heap_base unused +__heap_limit 00000200 + +Symbol: __heap_limit + Definitions + At line 55 in file ..\CORE\startup_stm32f0xx.s + Uses + None +Comment: __heap_limit unused +4 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +RESET 00000000 + +Symbol: RESET + Definitions + At line 62 in file ..\CORE\startup_stm32f0xx.s + Uses + None +Comment: RESET unused +__Vectors 00000000 + +Symbol: __Vectors + Definitions + At line 67 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 63 in file ..\CORE\startup_stm32f0xx.s + At line 120 in file ..\CORE\startup_stm32f0xx.s + +__Vectors_End 000000C0 + +Symbol: __Vectors_End + Definitions + At line 118 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 64 in file ..\CORE\startup_stm32f0xx.s + At line 120 in file ..\CORE\startup_stm32f0xx.s + +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +.text 00000000 + +Symbol: .text + Definitions + At line 122 in file ..\CORE\startup_stm32f0xx.s + Uses + None +Comment: .text unused +ADC1_COMP_IRQHandler 00000012 + +Symbol: ADC1_COMP_IRQHandler + Definitions + At line 204 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 97 in file ..\CORE\startup_stm32f0xx.s + At line 173 in file ..\CORE\startup_stm32f0xx.s + +CEC_IRQHandler 00000012 + +Symbol: CEC_IRQHandler + Definitions + At line 220 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 115 in file ..\CORE\startup_stm32f0xx.s + At line 189 in file ..\CORE\startup_stm32f0xx.s + +DMA1_Channel1_IRQHandler 00000012 + +Symbol: DMA1_Channel1_IRQHandler + Definitions + At line 201 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 94 in file ..\CORE\startup_stm32f0xx.s + At line 170 in file ..\CORE\startup_stm32f0xx.s + +DMA1_Channel2_3_IRQHandler 00000012 + +Symbol: DMA1_Channel2_3_IRQHandler + Definitions + At line 202 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 95 in file ..\CORE\startup_stm32f0xx.s + At line 171 in file ..\CORE\startup_stm32f0xx.s + +DMA1_Channel4_5_IRQHandler 00000012 + +Symbol: DMA1_Channel4_5_IRQHandler + Definitions + At line 203 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 96 in file ..\CORE\startup_stm32f0xx.s + At line 172 in file ..\CORE\startup_stm32f0xx.s + +Default_Handler 00000012 + +Symbol: Default_Handler + Definitions + At line 159 in file ..\CORE\startup_stm32f0xx.s + Uses + + + +ARM Macro Assembler Page 2 Alphabetic symbol ordering +Relocatable symbols + + None +Comment: Default_Handler unused +EXTI0_1_IRQHandler 00000012 + +Symbol: EXTI0_1_IRQHandler + Definitions + At line 197 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 90 in file ..\CORE\startup_stm32f0xx.s + At line 166 in file ..\CORE\startup_stm32f0xx.s + +EXTI2_3_IRQHandler 00000012 + +Symbol: EXTI2_3_IRQHandler + Definitions + At line 198 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 91 in file ..\CORE\startup_stm32f0xx.s + At line 167 in file ..\CORE\startup_stm32f0xx.s + +EXTI4_15_IRQHandler 00000012 + +Symbol: EXTI4_15_IRQHandler + Definitions + At line 199 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 92 in file ..\CORE\startup_stm32f0xx.s + At line 168 in file ..\CORE\startup_stm32f0xx.s + +FLASH_IRQHandler 00000012 + +Symbol: FLASH_IRQHandler + Definitions + At line 195 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 88 in file ..\CORE\startup_stm32f0xx.s + At line 164 in file ..\CORE\startup_stm32f0xx.s + +HardFault_Handler 0000000A + +Symbol: HardFault_Handler + Definitions + At line 142 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 70 in file ..\CORE\startup_stm32f0xx.s + At line 143 in file ..\CORE\startup_stm32f0xx.s + +I2C1_IRQHandler 00000012 + +Symbol: I2C1_IRQHandler + Definitions + At line 214 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 108 in file ..\CORE\startup_stm32f0xx.s + At line 183 in file ..\CORE\startup_stm32f0xx.s + +I2C2_IRQHandler 00000012 + +Symbol: I2C2_IRQHandler + + + +ARM Macro Assembler Page 3 Alphabetic symbol ordering +Relocatable symbols + + Definitions + At line 215 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 109 in file ..\CORE\startup_stm32f0xx.s + At line 184 in file ..\CORE\startup_stm32f0xx.s + +NMI_Handler 00000008 + +Symbol: NMI_Handler + Definitions + At line 137 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 69 in file ..\CORE\startup_stm32f0xx.s + At line 138 in file ..\CORE\startup_stm32f0xx.s + +PVD_IRQHandler 00000012 + +Symbol: PVD_IRQHandler + Definitions + At line 193 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 86 in file ..\CORE\startup_stm32f0xx.s + At line 162 in file ..\CORE\startup_stm32f0xx.s + +PendSV_Handler 0000000E + +Symbol: PendSV_Handler + Definitions + At line 150 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 81 in file ..\CORE\startup_stm32f0xx.s + At line 151 in file ..\CORE\startup_stm32f0xx.s + +RCC_IRQHandler 00000012 + +Symbol: RCC_IRQHandler + Definitions + At line 196 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 89 in file ..\CORE\startup_stm32f0xx.s + At line 165 in file ..\CORE\startup_stm32f0xx.s + +RTC_IRQHandler 00000012 + +Symbol: RTC_IRQHandler + Definitions + At line 194 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 87 in file ..\CORE\startup_stm32f0xx.s + At line 163 in file ..\CORE\startup_stm32f0xx.s + +Reset_Handler 00000000 + +Symbol: Reset_Handler + Definitions + At line 125 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 68 in file ..\CORE\startup_stm32f0xx.s + At line 126 in file ..\CORE\startup_stm32f0xx.s + + + +ARM Macro Assembler Page 4 Alphabetic symbol ordering +Relocatable symbols + + +SPI1_IRQHandler 00000012 + +Symbol: SPI1_IRQHandler + Definitions + At line 216 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 110 in file ..\CORE\startup_stm32f0xx.s + At line 185 in file ..\CORE\startup_stm32f0xx.s + +SPI2_IRQHandler 00000012 + +Symbol: SPI2_IRQHandler + Definitions + At line 217 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 111 in file ..\CORE\startup_stm32f0xx.s + At line 186 in file ..\CORE\startup_stm32f0xx.s + +SVC_Handler 0000000C + +Symbol: SVC_Handler + Definitions + At line 146 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 78 in file ..\CORE\startup_stm32f0xx.s + At line 147 in file ..\CORE\startup_stm32f0xx.s + +SysTick_Handler 00000010 + +Symbol: SysTick_Handler + Definitions + At line 154 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 82 in file ..\CORE\startup_stm32f0xx.s + At line 155 in file ..\CORE\startup_stm32f0xx.s + +TIM14_IRQHandler 00000012 + +Symbol: TIM14_IRQHandler + Definitions + At line 210 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 104 in file ..\CORE\startup_stm32f0xx.s + At line 179 in file ..\CORE\startup_stm32f0xx.s + +TIM15_IRQHandler 00000012 + +Symbol: TIM15_IRQHandler + Definitions + At line 211 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 105 in file ..\CORE\startup_stm32f0xx.s + At line 180 in file ..\CORE\startup_stm32f0xx.s + +TIM16_IRQHandler 00000012 + +Symbol: TIM16_IRQHandler + Definitions + + + +ARM Macro Assembler Page 5 Alphabetic symbol ordering +Relocatable symbols + + At line 212 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 106 in file ..\CORE\startup_stm32f0xx.s + At line 181 in file ..\CORE\startup_stm32f0xx.s + +TIM17_IRQHandler 00000012 + +Symbol: TIM17_IRQHandler + Definitions + At line 213 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 107 in file ..\CORE\startup_stm32f0xx.s + At line 182 in file ..\CORE\startup_stm32f0xx.s + +TIM1_BRK_UP_TRG_COM_IRQHandler 00000012 + +Symbol: TIM1_BRK_UP_TRG_COM_IRQHandler + Definitions + At line 205 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 98 in file ..\CORE\startup_stm32f0xx.s + At line 174 in file ..\CORE\startup_stm32f0xx.s + +TIM1_CC_IRQHandler 00000012 + +Symbol: TIM1_CC_IRQHandler + Definitions + At line 206 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 99 in file ..\CORE\startup_stm32f0xx.s + At line 175 in file ..\CORE\startup_stm32f0xx.s + +TIM2_IRQHandler 00000012 + +Symbol: TIM2_IRQHandler + Definitions + At line 207 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 100 in file ..\CORE\startup_stm32f0xx.s + At line 176 in file ..\CORE\startup_stm32f0xx.s + +TIM3_IRQHandler 00000012 + +Symbol: TIM3_IRQHandler + Definitions + At line 208 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 101 in file ..\CORE\startup_stm32f0xx.s + At line 177 in file ..\CORE\startup_stm32f0xx.s + +TIM6_DAC_IRQHandler 00000012 + +Symbol: TIM6_DAC_IRQHandler + Definitions + At line 209 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 102 in file ..\CORE\startup_stm32f0xx.s + At line 178 in file ..\CORE\startup_stm32f0xx.s + + + + +ARM Macro Assembler Page 6 Alphabetic symbol ordering +Relocatable symbols + +TS_IRQHandler 00000012 + +Symbol: TS_IRQHandler + Definitions + At line 200 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 93 in file ..\CORE\startup_stm32f0xx.s + At line 169 in file ..\CORE\startup_stm32f0xx.s + +USART1_IRQHandler 00000012 + +Symbol: USART1_IRQHandler + Definitions + At line 218 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 112 in file ..\CORE\startup_stm32f0xx.s + At line 187 in file ..\CORE\startup_stm32f0xx.s + +USART2_IRQHandler 00000012 + +Symbol: USART2_IRQHandler + Definitions + At line 219 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 113 in file ..\CORE\startup_stm32f0xx.s + At line 188 in file ..\CORE\startup_stm32f0xx.s + +WWDG_IRQHandler 00000012 + +Symbol: WWDG_IRQHandler + Definitions + At line 192 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 85 in file ..\CORE\startup_stm32f0xx.s + At line 161 in file ..\CORE\startup_stm32f0xx.s + +__user_initial_stackheap 00000014 + +Symbol: __user_initial_stackheap + Definitions + At line 242 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 240 in file ..\CORE\startup_stm32f0xx.s +Comment: __user_initial_stackheap used once +38 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Absolute symbols + +Heap_Size 00000200 + +Symbol: Heap_Size + Definitions + At line 50 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 54 in file ..\CORE\startup_stm32f0xx.s + At line 246 in file ..\CORE\startup_stm32f0xx.s + +Stack_Size 00000400 + +Symbol: Stack_Size + Definitions + At line 39 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 42 in file ..\CORE\startup_stm32f0xx.s + At line 245 in file ..\CORE\startup_stm32f0xx.s + +__Vectors_Size 000000C0 + +Symbol: __Vectors_Size + Definitions + At line 120 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 65 in file ..\CORE\startup_stm32f0xx.s +Comment: __Vectors_Size used once +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +External symbols + +SystemInit 00000000 + +Symbol: SystemInit + Definitions + At line 128 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 129 in file ..\CORE\startup_stm32f0xx.s +Comment: SystemInit used once +__main 00000000 + +Symbol: __main + Definitions + At line 127 in file ..\CORE\startup_stm32f0xx.s + Uses + At line 131 in file ..\CORE\startup_stm32f0xx.s +Comment: __main used once +__use_two_region_memory 00000000 + +Symbol: __use_two_region_memory + Definitions + At line 239 in file ..\CORE\startup_stm32f0xx.s + Uses + None +Comment: __use_two_region_memory unused +3 symbols +391 symbols in table diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/stm32f0xx.h b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/stm32f0xx.h new file mode 100644 index 0000000..d14400b --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/stm32f0xx.h @@ -0,0 +1,3222 @@ +/** + ****************************************************************************** + * @file stm32f0xx.h + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32F0xx devices. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The device used in the target application + * - To use or not the peripheral’s drivers in application code(i.e. + * code will be based on direct access to peripheral’s registers + * rather than drivers API), this option is controlled by + * "#define USE_STDPERIPH_DRIVER" + * - To change few application-specific parameters such as the HSE + * crystal frequency + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f0xx + * @{ + */ + +#ifndef __STM32F0XX_H +#define __STM32F0XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32F-0 device used in your + application + */ + +#if !defined (STM32F0XX) + #define STM32F0XX /*!< STM32F0XX: STM32F0xx devices */ +#endif +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + + - STM32F0xx devices are STM32F050xx microcontrollers where the Flash memory + density ranges between 32 and 64 Kbytes. + */ + +#if !defined (STM32F0XX) + #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)" +#endif /* STM32F0XX */ + +#if !defined USE_STDPERIPH_DRIVER +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_STDPERIPH_DRIVER*/ +#endif /* USE_STDPERIPH_DRIVER */ + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/ +#endif /* HSE_VALUE */ + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup + Timeout value + */ +#if !defined (HSI_STARTUP_TIMEOUT) +#define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */ +#endif /* HSI_STARTUP_TIMEOUT */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal High Speed oscillator in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#endif /* HSI_VALUE */ + +#if !defined (HSI14_VALUE) +#define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#endif /* HSI14_VALUE */ + +#if !defined (LSI_VALUE) +#define LSI_VALUE ((uint32_t)40000) /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +#endif /* LSI_VALUE */ + +#if !defined (LSE_VALUE) +#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +/** + * @brief STM32F0xx Standard Peripheral Library version number V1.0.0 + */ +#define __STM32F0XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32F0XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __STM32F0XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F0XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F0XX_STDPERIPH_VERSION ((__STM32F0XX_STDPERIPH_VERSION_MAIN << 24)\ + |(__STM32F0XX_STDPERIPH_VERSION_SUB1 << 16)\ + |(__STM32F0XX_STDPERIPH_VERSION_SUB2 << 8)\ + |(__STM32F0XX_STDPERIPH_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief STM32F0xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +#define __CM0_REV 0 /*!< Core Revision r0p0 */ +#define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */ +#define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/*!< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ + +/****** STM32F-0 specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ + RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ + FLASH_IRQn = 3, /*!< FLASH Interrupt */ + RCC_IRQn = 4, /*!< RCC Interrupt */ + EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + TS_IRQn = 8, /*!< TS Interrupt */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */ + ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 15, /*!< TIM2 Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 Interrupt */ + TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */ + TIM14_IRQn = 19, /*!< TIM14 Interrupt */ + TIM15_IRQn = 20, /*!< TIM15 Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Interrupt */ + I2C2_IRQn = 24, /*!< I2C2 Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 Interrupt */ + USART1_IRQn = 27, /*!< USART1 Interrupt */ + USART2_IRQn = 28, /*!< USART2 Interrupt */ + CEC_IRQn = 30 /*!< CEC Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm0.h" +#include "system_stm32f0xx.h" +#include + +/** @addtogroup Exported_types + * @{ + */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ + __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ + __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ + __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ + uint32_t RESERVED3; /*!< Reserved, 0x24 */ + __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ + uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ + __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; +} ADC_Common_TypeDef; + +/** + * @brief HDMI-CEC + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x1C */ +} COMP_TypeDef; + + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ +} CRC_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + uint32_t RESERVED[6]; /*!< Reserved, 0x14 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + uint32_t RESERVED1; /*!< Reserved, 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!
    © COPYRIGHT 2012 STMicroelectronics
    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_CONF_H +#define __STM32F0XX_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Comment the line below to disable peripheral header file inclusion */ +//#include "stm32f0xx_adc.h" +//#include "stm32f0xx_cec.h" +//#include "stm32f0xx_crc.h" +//#include "stm32f0xx_comp.h" +//#include "stm32f0xx_dac.h" +//#include "stm32f0xx_dbgmcu.h" +//#include "stm32f0xx_dma.h" +//#include "stm32f0xx_exti.h" +//#include "stm32f0xx_flash.h" +#include "stm32f0xx_gpio.h" +//#include "stm32f0xx_syscfg.h" +//#include "stm32f0xx_i2c.h" +//#include "stm32f0xx_iwdg.h" +//#include "stm32f0xx_pwr.h" +#include "stm32f0xx_rcc.h" +//#include "stm32f0xx_rtc.h" +//#include "stm32f0xx_spi.h" +//#include "stm32f0xx_tim.h" +#include "stm32f0xx_usart.h" +//#include "stm32f0xx_wwdg.h" +#include "stm32f0xx_misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function which reports + * the name of the source file and the source line number of the call + * that failed. If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F0XX_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/stm32f0xx_it.c b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/stm32f0xx_it.c new file mode 100644 index 0000000..ac4884a --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/stm32f0xx_it.c @@ -0,0 +1,125 @@ +/** + ****************************************************************************** + * @file IO_Toggle/stm32f0xx_it.c + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_it.h" + +/** @addtogroup STM32F0_Discovery_Peripheral_Examples + * @{ + */ + +/** @addtogroup IO_Toggle + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M0 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F0xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f0xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/stm32f0xx_it.h b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/stm32f0xx_it.h new file mode 100644 index 0000000..1e1b9c4 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/stm32f0xx_it.h @@ -0,0 +1,56 @@ +/** + ****************************************************************************** + * @file IO_Toggle/stm32f0xx_it.h + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0XX_IT_H +#define __STM32F0XX_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0XX_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/system_stm32f0xx.c b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/system_stm32f0xx.c new file mode 100644 index 0000000..87d9ab7 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/system_stm32f0xx.c @@ -0,0 +1,353 @@ +/** + ****************************************************************************** + * @file system_stm32f0xx.c + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F0xx devices, + * and is generated by the clock configuration tool + * STM32F0xx_Clock_Configuration_V1.0.0.xls + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f0xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz Range) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define + * in "stm32f0xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + * System Clock Configuration + *============================================================================= + * System Clock source | PLL(HSE) + *----------------------------------------------------------------------------- + * SYSCLK | 48000000 Hz + *----------------------------------------------------------------------------- + * HCLK | 48000000 Hz + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * HSE Frequency | 8000000 Hz + *----------------------------------------------------------------------------- + * PLL MUL | 6 + *----------------------------------------------------------------------------- + * VDD | 3.3 V + *----------------------------------------------------------------------------- + * Flash Latency | 1 WS + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f0xx_system + * @{ + */ + +/** @addtogroup STM32F0xx_System_Private_Includes + * @{ + */ + +#include "stm32f0xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Defines + * @{ + */ +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Variables + * @{ + */ +uint32_t SystemCoreClock = 48000000; +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */ + RCC->CFGR &= (uint32_t)0xF8FFB80C; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ + RCC->CFGR &= (uint32_t)0xFFC0FFFF; + + /* Reset PREDIV1[3:0] bits */ + RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; + + /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFFFEAC; + + /* Reset HSI14 bit */ + RCC->CR2 &= (uint32_t)0xFFFFFFFE; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + + /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */ + SetSysClock(); +} + +/** + * @brief Update SystemCoreClock according to Clock Register Values + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + break; + default: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, AHB/APBx prescalers and Flash + * settings. + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer and set Flash Latency */ + FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1; + + /* PLL configuration = HSE * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6); + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/system_stm32f0xx.h b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/system_stm32f0xx.h new file mode 100644 index 0000000..c36f1a5 --- /dev/null +++ b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/JC144演示demo_ STM32F030串口 UART/JC144 STM32F030串口 UART/User/system_stm32f0xx.h @@ -0,0 +1,104 @@ +/** + ****************************************************************************** + * @file system_stm32f0xx.h + * @author MCD Application Team + * @version V1.0.0 + * @date 23-March-2012 + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Header File. + ****************************************************************************** + * @attention + * + *

    © COPYRIGHT 2012 STMicroelectronics

    + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f0xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F0XX_H +#define __SYSTEM_STM32F0XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F0xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F0xx_System_Exported_types + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F0XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/图片与单片机固件/JC144 图片/1.jpg b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/图片与单片机固件/JC144 图片/1.jpg new file mode 100644 index 0000000..85cd77c Binary files /dev/null and b/开发资料/串口屏资料/JC144-SQQVGA-ST-01-V01 20250724/模块例程/图片与单片机固件/JC144 图片/1.jpg differ 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